數(shù)字電路英文版第十單元PPT課件

1、KEY TERMS Bidirectional Having two directions. In a bidirectional shift register, the stored data can be shifted right or left. Johnson counter A type of register in which a specified prestored pattern of 1s and 0s is shifted through the stages, creating a unique sequence of bit patterns.第1頁(yè)/共66頁(yè) Lo

2、ad To enter data into a shift register. Ring counter A register in which a certain pattern of 1s and 0s is continuously recirculated. Stage One storage element in a register.第2頁(yè)/共66頁(yè) Shift To move binary data from state to stage within a shift register or other storage device or to move binary data

3、into or out of the device. Universal shift register A register that has both serial and parallel input and output capability.第3頁(yè)/共66頁(yè) Shift registers consist of an arrangement of flip-flops and are important in applications involving the storage and transfer of data in a digital system.2.第4頁(yè)/共66頁(yè)D0Q

4、C0CLKD1QC1CLK1 is stored0 is storedThe flip-flop as a storage element.3.第5頁(yè)/共66頁(yè)DatainDataoutDatainDataout(a) Serial in/shift right/serial out(b) Serial in/shift left/serial out4.第6頁(yè)/共66頁(yè)DatainDataout(c) Parallel in/serial outData inData out(d) Serial in/ parallel out5.第7頁(yè)/共66頁(yè)Data inDataout(e) Para

5、llel in/ parallel out(f) Rotate right(g) Rotate left6.第8頁(yè)/共66頁(yè) The serial in/serial out shift register accepts data serially that is , one bit at a time on a single line. It produces the stored information on its output also in serial form.7.第9頁(yè)/共66頁(yè)DCDCDCDCQ0Q1Q2Q3Q3Serial data outputSerial data ou

6、tputSerial data inputCLKSerial in/ serial out shift register8.FF0FF1FF2FF3第10頁(yè)/共66頁(yè)DCDCDCDCFF0FF1FF2FF3CLKData inputRegisterinitiallyCLEAR0000Q3DCDCDCDCFF0FF1FF2FF31st dataAfter CLK10000Q3bit = 0CLK 19.第11頁(yè)/共66頁(yè)DCDCDCDCFF0FF1FF2FF32st dataAfter CLK20100Q3bit = 1CLK 2DCDCDCDCFF0FF1FF2FF33st dataAfter

7、 CLK31000Q3bit = 0CLK 310.第12頁(yè)/共66頁(yè)DCDCDCDCFF0FF1FF2FF34st dataAfter CLK40110Q3bit = 1CLK 4Four bit ( 1010 ) being entered serially into the register. 11.第13頁(yè)/共66頁(yè)DCDCDCDCFF0FF1FF2FF3After CLK401100CLKregistercontains1010DCDCDCDCFF0FF1FF2FF31st dataAfter CLK51001Q3bitCLK 5Q302nd date bit 12.第14頁(yè)/共66

8、頁(yè)DCDCDCDCFF0FF1FF2FF3After CLK70001CLK 70DCDCDCDCFF0FF1FF2FF3After CLK60010CLK 60Q3Q34th date bit 3rd date bit 13.第15頁(yè)/共66頁(yè)DCDCDCDCFF0FF1FF2FF3After CLK80000CLK 80Q3registeris CLEARFour bit ( 1010 ) being serially shiftedout of the register and replaced by all zeros. 14.第16頁(yè)/共66頁(yè)EXAMPLE 10-1 Q4Q3Q2Q

9、1Q0 =11010DCDCDCDCFF0FF1FF2FF3DCFF4Q0Q1Q2Q3Q4Data inputData outputCLK 15.第17頁(yè)/共66頁(yè)CLKData inputQ0Q1Q2Q3Q41111110000Data bitstoredafterpulseclockfive16.第18頁(yè)/共66頁(yè) Data bits are entered serially into this type of register in the same manner as discussed in Section 10-2. The difference is the way in whi

10、ch the data bits are taken out of the register; in the parallel output register, the output of each stage is available. 17.第19頁(yè)/共66頁(yè)Once the data are stored, each bit appears on its respective output line, and all bits are available simultaneously, rather than on a bit-by-bit basis as with the seria

11、l output.18.第20頁(yè)/共66頁(yè)DCDCDCDCFF0FF1FF2FF3DataCLKQ3inputQ0Q1Q2SRG 4DCQ3Q0Q1Q2Data inputCLK19.第21頁(yè)/共66頁(yè)EXAMPLE 10-2 The register contains 0110.SRG 4DCQ3Q0Q1Q2CLKQ0Q1Q2Q31111000020.第22頁(yè)/共66頁(yè) For a register with parallel data inputs, the bits are entered simultaneously into their respective stages on pa

12、rallel lines rather than on a bit-by-bit basis on one line as with serial data inputs. The serial output is the same as described in Section 10-2, once the data are completely stored in the register. 21.第23頁(yè)/共66頁(yè)DCDCDCDCdataCLKQ3outputQ0Q1Q2SHIFT/LOADD3D0D1D2SerialG3G1G2G6G5G422.第24頁(yè)/共66頁(yè)SRG 4CD3D0D

13、1D2SHIFT/LOADCLKSerial data out(b) Logic symbol23.Data in第25頁(yè)/共66頁(yè) Parallel entry of data was described in Section10-4, and parallel output of data has also been discussed previously. The parallel in/parallel out register employs both methods. Immediately following the simultaneous entry of all data

14、 bits, the bits appear on the parallel outputs.24.第26頁(yè)/共66頁(yè)DCDCDCDCQ0Q1Q2Q3D3CLKD0D1D2Parallel data outputParallel data input25.第27頁(yè)/共66頁(yè) A bidirectional shift register is one in which the data can be shift either left or right. It can be implemented by using gating logic that enables the transfer o

15、f a data bit from one stage to the next stage to the right or to the left, depending on the level of a control line.26.第28頁(yè)/共66頁(yè)DCDCDCDCCLKQ3Serial data inQ0Q1Q2R/LG8G6G7G4G3G2G1G527.第29頁(yè)/共66頁(yè)CLKQ0Q1Q2123456789Q3111111111111111100000000000000000000000( right )( right )( left )( left )0EXAMPLE 10-4 Q

16、3Q2Q1Q0=1011R/L28.第30頁(yè)/共66頁(yè) The Johnson Counter: In a Johnson counter the complement of the output of the last flip-flop is connected back to the D input of the first flip-flop.29.第31頁(yè)/共66頁(yè)Clock Pulse Q0 Q1 Q2 Q3 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1Four-bit

17、 Johnson sequence. 2n states30.第32頁(yè)/共66頁(yè)DCDCDCDCQ0Q1Q2FF1Q3FF2FF3FF0CLK(a) Four-bit Johnson counter31.第33頁(yè)/共66頁(yè)CLKQ0Q1Q212345678Q3Timing sequence for a 4-bit Johnson counter32.第34頁(yè)/共66頁(yè) The Ring Counter : The ring counter utilizes one flip-flop for each state in its sequence.33.第35頁(yè)/共66頁(yè)DCDCDCDCQ0Q1

18、Q2FF1CLRFF3PRECLKDCDCQ3Q4Q5A 6-bit ring counter 34.第36頁(yè)/共66頁(yè)Clock Pulse Q0 Q1 Q2 Q3 Q4 Q5 0 1 0 0 0 0 0 1 0 1 0 0 0 0 2 0 0 1 0 0 0 3 0 0 0 1 0 0 4 0 0 0 0 1 0 5 0 0 0 0 0 1Six-bit ring counter sequence.35.第37頁(yè)/共66頁(yè)CLKQ0Q1Q212345678Q3Q5Q436.第38頁(yè)/共66頁(yè)Time DelaySRG 8ACCLKData in123456789Data outData i

19、n1 us8 usQ7Q7CLK 1MHz第39頁(yè)/共66頁(yè)EXAMPLE 10-6 Determine the amount of time delay between the serial input and each output in Figure 10-29. Show a timing diagram to illustrate.SRG 8*ACCLK 500 kHzQ7Q0Q1Q2Q3Q4Q6Q5CLRData inB* Data shift from Q0 toward Q7第40頁(yè)/共66頁(yè)CLK123456789Data inQ6Q0Q1Q2Q3Q4Q5Q72 us16 u

20、s第41頁(yè)/共66頁(yè)第42頁(yè)/共66頁(yè)第43頁(yè)/共66頁(yè)第44頁(yè)/共66頁(yè)第45頁(yè)/共66頁(yè)第46頁(yè)/共66頁(yè)第47頁(yè)/共66頁(yè)SRG 4Data BitsCQ7D0Q3+V+SH/LDSRG 87419574195D4D1D2D3D6D5D7Start bitStop bitCLKC第48頁(yè)/共66頁(yè)SRG 4Data BitsCQ7D0Q3+V+SH/LDSRG 87419574195D4D1D2D3D6D5D7Start bitStop bitCLKC43. See Figure as follow for one possible implementation.第49頁(yè)/共66頁(yè)Q0

21、Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VLOADENPENTCLRD3 D2 D1 D0Q3 Q2 Q1 Q074LS163JKCLRPREQRCO+5V+5V+5VParallel Data Out ( HIGH) Para

22、llel Data Out (LOW) Data In CLK 第50頁(yè)/共66頁(yè)Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VQ0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 74LS16474LS199SRSLS1S0CLRBACLR+5VLOADENPENTCLRD3 D2 D1 D0Q3 Q2 Q1 Q074LS163JKCLRPR

23、EQRCO+5V+5V+5VParallel Data Out ( HIGH) Parallel Data Out (LOW) Data In CLK 42. Portions of the circuit that require modification for 16-bit conversion.7476第51頁(yè)/共66頁(yè)Digital System Design with VHDL Combinational building blocks 1.Decoder 1.1 2 to 4 decoder第52頁(yè)/共66頁(yè) library ieee; use ieee.std_logic_11

24、64.all; entity decoder is port ( a: in std_ulogic_vector(1 downto 0); z: out std_ulogic_vector(3 downto 0); end entity decoder; 第53頁(yè)/共66頁(yè) architecture when_else of decoder is begin z = “0001” when a = “00” else “0010” when a = “01” else “0100” when a = “10” else “1000” when a = “11” else “XXXX” ; en

25、d architecture when_else;第54頁(yè)/共66頁(yè)Seven-segment display library ieee; use ieee.std_logic_1164.all; entity seven_seg is port ( a: in integer range 0 to 15; z: out std_ulogic_vector(6 downto 0); end entity seven_seg;第55頁(yè)/共66頁(yè) architecture with_select of seven_seg is begin z = “1111110” when 0, “011000

26、0” when 1, “1101101” when 2, “1111001” when 3, “0110011” when 4, “1011011” when 5, “1011111” when 6, 第56頁(yè)/共66頁(yè) “1010010” when 7, “1111111” when 8, “1111011” when 9, “1001111” when 10 to 15; end architecture with_select;第57頁(yè)/共66頁(yè)Multiplexers 4 to 1 multiplexer library ieee; use ieee.std_logic_1164.al

27、l; entity mux is port ( a, b, c, d: in std_ulogic; s: in std_ulogic_vector(1 downto 0); y: out std_ulogic); end entity mux;第58頁(yè)/共66頁(yè) architecture mux1 of mux is begin with s select y = a when “00” ; b when “01” ; c when “10” ; d when “11” ; “X” when others; end architecture mux1;第59頁(yè)/共66頁(yè) architecture mux2 of mux is begin y = a when s = “00” else; b when s = “01” else; c when s = “10” else; d when s = “11” else; “X”; end architecture mux2;第60頁(yè)/共66頁(yè)VHDL