DAC芯片TLC5620-verilog代碼

1、DAC芯片 TLC5620 Verilog 代碼GND1U141VDDREFA213LDACREFB312DACAREFC4IIDACBREFD510DACCDATA69DACDcilk18LOADTLC5620是TI公司的DA轉(zhuǎn)換芯片，F(xiàn)面的代碼實現(xiàn)的簡單的DA轉(zhuǎn)換功能說明：數(shù)碼管1顯示通道， 數(shù)碼管2顯示RNG直，數(shù)碼管3和4顯示CODE直。按鍵1切換通道, 按鍵2改變RNG直(0或1)，按鍵3改變CODE直，按鍵4未使用。/* DAC11 位數(shù)據(jù)輸入說明：Bit10:9通道選擇 00:CH 代 01:CHB; 10:CHC; 11:CHDBit8 RNG 0:參考電壓到地 1:兩倍參考電

2、壓到地Bit7:0 DAC轉(zhuǎn)換代碼，圍 0255.輸岀電壓 Vo=REF*(CODE/256)*(1+RNG)*/moduledac(elk,rst_ n,dac_clk,dac_data,dac_load,sw1_ n, sw2_ n, sw3_ n,sw4_ n,digit_o,cs)；in putelk;/ 輸入時鐘50MHzin putrst_ n;/ 復(fù)位in putsw1_ n, sw2_ n, sw3_ n, sw4_ n;/ 按鍵outputdae_elk;/ DAC 時鐘 MAX=1MHzoutputdae_data;/ DAC數(shù)據(jù)輸岀outputdae_load;/加載信號

3、/電路圖中LDAC已經(jīng)接地，因此略去output 7:0 digit_o;/數(shù)碼管輸出output 3:0es;/ 數(shù)碼管片選parameterDAC_Idle = 3'b001,/狀態(tài)參數(shù)DAC_Se nd = 3'b010,DAC_Store = 3'b100;/： parameter/ 字模MSK_0=8'hC0,/ '0'MSK_1=8'hF9,/ '1'MSK_2=8'hA4,/ '2'MSK_3=8'hB0,/ '3'MSK_4=8'h99,/ '

4、4'MSK_5=8'h92,/ '5'MSK_6=8'h82,/ '6'MSK_7=8'hF8,/ '7'MSK_8=8'h80,/ '8'MSK_9=8'h90,/ '9'MSK_A=8'h88,/ 'A'MSK_B=8'h83,/ 'B'MSK_C=8'hC6,/ 'C'MSK_D=8'hA1,/ 'D'MSK_E=8'h86,/ 'E'MSK_

5、F=8'h8E;/ 'F'/=/*按鍵局部*/reg 3:0key_rst;/保存按鍵前一個狀態(tài)always (posedge clk or n egedge rst_n)if (!rst_ n)key_rst <= 4'b1111;else key_rst <= sw4_ n, sw3_ n, sw2_ n,sw1_ n;reg3:0key_rst_r;/保存按鍵下一個狀態(tài)always (posedge clk or n egedge rst_n)if (!rst_ n)key_rst_r <= 4'b1111;else key_rs

6、t_r <= key_rst;/檢測是否有1wire3:0 key_val = key_rst_r & (key_rst);到0跳變reg19:0t;/ 計數(shù)器always (posedge clk or n egedge rst_n)if (!rst_ n)t <= 20'd0;else if(key_val)/有按鍵按下(由1變?yōu)?)計數(shù)器開始計時 20mst <= 20'd0;elset <=t + 1'b1;/去抖動后的按鍵檢測，仍然用兩級存放器reg3:0 low_sw;always (posedge clk or n eged

7、ge rst_n)if (!rst_ n)low_sw <= 4'b1111;else if (ent =20'hfffff)/鎖存到low_sw中l(wèi)ow_sw <= sw4_ n, sw3_ n, sw2_ n,sw1_ n;20ms后的按鍵狀態(tài)reg3:0 low_sw_r;always (posedge elk or n egedge rst_ n)if (!rst_ n)low_sw_r <= 4'b1111;elselow_sw_r <= low_sw;wire3:0 led_etrl = low_sw_r & (low_sw)

8、;reg 10:0 rData;always (posedge elk or n egedge rst_n)if(!rst_ n)rData <= 11'd255;elsebeginif (led_etrl0 = 1)rData10:9 <= rData10:9 + 1'b1;if (led_etrl1 = 1)rData8 <= rData8;if (led_etrl2 = 1)rData7:0 <= rData7:0 + 8'd8;/ S1 鍵按下/ 通道切換/ S2 鍵按下/ RNG位變化/ S3 鍵按下/ CODE變化end/* */*

9、DAC控制局部*/分頻計數(shù)器64分頻reg 5:0div_c nt;regdiv_clk;/ 分頻時鐘注意不是DAC輸入時鐘always (posedge clk or n egedge rst_n) if (!rst_ n) beg indiv_c nt <= 6'd0;div_clk <= 1'b z;end else begi ndiv_c nt <= div_c nt + 1'b1;if (div_c nt = 6'd63)div_clk <= 1'b1;elsediv_clk <= 1'b0;end /*

10、*/reg 2:0regcurre nt_state ,n ext_state;rDac_load;regbit_c nt_rst;/位計數(shù)器復(fù)位信號wiredat_se nd_do ne;/時序進程always (posedge clk or n egedge rst_n) if (!rst_ n)curre nt_state <= DAC_Idle;elsecurre nt_state <= n ext_state;/組合進程always (curre nt_state or div_clk or dat_se nd_done) begi nrDac_load<=1

11、9;b1;bit_c nt_rst <= 1'b0;n ext_state <= DAC_ldle;case (curre nt_state)DAC_Idle: beginbit_c nt_rst <= 1'b1;n ext_state <= DAC_Se nd;end/空閑時直接進入send狀態(tài)DAC_Se nd: beginif (dat_se nd_do ne)n ext_state <= DAC_Store;elsen ext_state <= DAC_Se nd;end/數(shù)據(jù)發(fā)送完成DAC_Store: beginbit_c nt_

12、rst <= 1'b1;rDac_load<= 1'b0;if (div_clk)n ext_state <= DAC_Idle;elsen ext_state <= DAC_Store;end/ LOAD變低進展鎖存endcaseend/*/reg 4:0 bit_cnt;/ 位計數(shù)器 對 div_clk 計數(shù)always (posedge clk or n egedge rst_n) begi nif (!rst_ n)bit_c nt <= 5'd0;else if (bit_c nt_rst)bit_c nt <= 5'

13、;d0;else if (div_clk)bit_c nt <= bit_c nt + 1'b1;end assig n dat_se nd_done = (bit_c nt = 5'd24);吠*reg rDac_data;always (bit_c nt4:1 or rData) beg incase (bit_c nt4:1)/11位數(shù)據(jù)4'd1 : rDac_data <= rData10;4'd2 : rDac_data <= rData9;4'd3 : rDac_data <= rData8;4'd4 : rD

14、ac_data <= rData7;4'd5 : rDac_data <= rData6;4'd6 : rDac_data <= rData5;4'd7 : rDac_data <= rData4;4'd8 : rDac_data <= rData3;4'd9 : rDac_data <= rData2;4'd10: rDac_data <= rData1;4'd11: rDac_data <= rData0; default : rDac_data <= 1'b0;endca

15、se end吠*regrDac_clk;always (bit_c nt) beg in/ DAC CLKperiod=256Onsif (bit_cnt >= 2) && (bit_cnt <24)/rDac_clk <= bit_c nt0;elserDac_clk <= 1'b0;end吠*assig n dac_clk = rDac_clk;assig n dac_data = rDac_data;assig n dac_load = rDac_load;/*/*數(shù)碼管顯示局部*說明：數(shù)碼管1顯示通道 數(shù)碼管2顯示RNG值*數(shù)碼管3和4顯

16、示CODE值*/reg3:0cs;/片選信號reg16:0t2;/計數(shù)存放器2,確定掃描間隔reg3:0submsk;/保存要顯示的數(shù)據(jù)always (posedge clk or n egedge rst_n) if (!rst_ n)begint2 <=17'd0;/ 計數(shù)器2置零cs<= 4'b0111;endelse begi n/計數(shù)器2開始t2 <=t2 +1'b1;計數(shù)/ 溢出if (cnt2 =17'd0)了，又從0開始beginif (cs = 4'b0111)begincs<=4'b1110;subms

17、k <= rData3:0;CODE氐4位endelse if (cs = 4'b1110)begin cs<=4'b1101;submsk <= rData7:4;endelse if (cs = begin cs<= 4'b1011;submsk <= 3'b000,rData 8;endelse if (cs = 4'b1011)begincs<= 4'b0111;submsk <= 2'b00,rData10:9 + 1'b1;end/選擇第四個數(shù)碼管/顯示/選擇第一個數(shù)碼管/顯示

18、通道/ 選擇第三個數(shù)碼管/ 顯示CODE高4位4'b1101)/ 選擇第二個數(shù)碼管/ 顯示RNG值endendreg7:0digit_o;/數(shù)碼管輸出存放器always (submsk)case (submsk)4'h0:digit_o <= MSK_0;4'h1:digit_o <= MSK_1;4'h2:digit_o <= MSK_2;4'h3:digit_o <= MSK_3;4'h4:digit_o <= MSK_4;4'h 5:digit_o <= MSK_5;4'h6:digit_o <= MSK_6;4'h7:digit o <= MSK 7;4'h8:digit_