100進(jìn)制同步計(jì)數(shù)器設(shè)計(jì)報告

1、浙江萬里學(xué)院實(shí)驗(yàn)報告課程名稱：實(shí)驗(yàn)名稱：100進(jìn)制同步計(jì)數(shù)器設(shè)計(jì)專業(yè)班級：電子103姓名：徐強(qiáng) 學(xué)號:2010014092實(shí)驗(yàn)日期:一、實(shí)驗(yàn)?zāi)康模?、掌握計(jì)數(shù)器的原理及設(shè)計(jì)方法；2、設(shè)計(jì)一個0100的計(jì)數(shù)器；3、利用實(shí)驗(yàn)二的七段數(shù)碼管電路進(jìn)行顯示；二、實(shí)驗(yàn)要求：1、用VHDL語言進(jìn)行描寫；2、有計(jì)數(shù)顯示輸出；3、有清零端和計(jì)數(shù)使能端；三、實(shí)驗(yàn)結(jié)果：1.VHDL程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;PACKAGEmy_pkglSComp onentn d2-或門PORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDComp o

2、nent;Comp onen tled_decoderPORT(di n:in std_logic_vector(3dow ntoO);-四位二進(jìn)制碼輸入 seg:outstd_logic_vector(6downtoO);-輸出 LED 七段碼ENDComp onent;ComponentCNT60-2 位 BCD 碼 60 進(jìn)制計(jì)數(shù)器PORT(CR:INSTD_LOGIC;EN:INSTD_LOGIC;CLK:INSTD_LOGIC;OUTLOW:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0);OUTHIGH:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0

3、);ENDComponent;ComponentCNT100-帶使能和清零信號的 100 進(jìn)制計(jì)數(shù)器PORT(CLK:INSTD_LOGIC;EN:INSTD_LOGIC;CLR:INSTD_LOGIC;OUTLOW:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0);OUTHIGH:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0) );ENDComponent;Componentfreq_div-50MHZ 時鐘分頻出 1HzPORT(clkinput:INSTD_LOGIC;output:OUTSTD_LOGIC);ENDComponent;Component

4、jtd-交通燈控制器PORTCLKIN:INSTD_LOGIC;-50MHZR1,G1,R2,G2,R3,G3,R4,G4:OUTSTD_LOGIC;-紅綠燈信號輸出GAO,DI:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0)- 倒計(jì)時輸出 );ENDComponent;ENDmy_pkg;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEwork.my_pkg.ALL; - 打開程序包ENTITYDemo3ISPORT(CRl:INSTD_LOGIC;ENl:INSTD_LOGIC;CLKIN:INSTD_LOGIC;LEDLOW,LEDH

5、IGH:OUTSTD_LOGIC_VECTOR(6downto0);ENDDemo3;ARCHITECTUREbehvOFDemo3ISSIGNALCLKTEMP:STD_LOGIC;- 定義中轉(zhuǎn)信號SIGNALLEDLOWTEMP,LEDHIGHTEMP:STD_LOGIC_VECTOR(3downto0);BEGINu1:freq_divPORTMAP(CLKIN,CLKTEMP); -位置關(guān)聯(lián)方式 u2:CNT60PORTMAP(CR=>CRl,EN=>ENl,CLK=>CLKTEMP,OUTLOW=>LEDLOWTEMP,OUTH IGH=>LEDHIGH

6、TEMP);-名字關(guān)聯(lián)方式u3:led_decoderPORTMAP(LEDLOWTEMP,LEDLOW);-低位數(shù)碼管輸出u4:led_decoderPORTMAP(LEDHIGHTEMP,LEDHIGH);-高位數(shù)碼管輸出ENDbehv;LIBRARYieee;USEieee.std_logic_1164.all;ENTITYfreq_divISPORT(clkinput:INSTD_LOGIC;output:OUTSTD_LOGIC);ENDfreq_div;ARCHITECTURErtOFfreq_divISSIGNALcount_signal:INTEGERRANGE0TO25000

7、000;signalmid1:STD_LOGIC;BEGINPROCESS(clkinput)BEGINIF(clkinput'EVENTANDclkinput='1')THENifcount_signal=24999999then-50MHzdivisionto1Hz count_signal<=0;mid1<=notmid1;elsecount_signal<=count_signal+1;endif;output<=mid1;endif;ENDPROCESS;endrt;- 文件名： decoder.vhdlibraryIEEE;useIE

8、EE.STD_LOGIC_1164.ALL;entityled_decoderisPort(din:instd_logic_vector(3downto0);-四位二進(jìn)制碼輸入seg:outstd_logic_vector(6downto0);-輸出 LED 七段碼 endled_decoder;architectureBehavioralofled_decoderisbeginprocess(din)begincasediniswhen"0000"=> seg<="1000000"-0 when"0001"=>se

9、g<="1111001"-1 when"0010"=>seg<="0100100"-2 when"0011"=>seg<="0110000"-3 when"0100"=>seg<="0011001"-4 when"0101"=>seg<="0010010"-5 when"0110"=>seg<="0000010"

10、-6 when"0111"=>seg<="1011000"-7 when"1000"=>seg<="0000000"-8 when"1001"=>seg<="0010000"-9 whenothers=>seg<="0000110"-E endcase;endprocess; endBehavioral; LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_

11、LOGIC_UNSIGNED.ALL;ENTITYCNT60ISPORT(CR:INSTD_LOGIC; EN:INSTD_LOGIC; CLK:INSTD_LOGIC;OUTLOW:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0); OUTHIGH:BUFFERSTD_LOGIC_VECTOR(3DOWNTO0) );ENDCNT60;ARCHITECTUREbehavOFCNT60ISBEGINPROCESS(CLK,CR,EN)BEGINifCR='1'thenOUTHIGH<="0000"OUTLOW<="000

12、0"elsifEN='1'thenIFCLK'EVENTANDCLK='1'THENIFOUTHIGH="1001"ANDOUTLOW="1001"THENOUTHIGH<="0000"OUTLOW<="0000"ELSIFOUTLOW="1001"THENOUTHIGH<=OUTHIGH+1;OUTLOW<="0000"ELSEOUTLOW<=OUTLOW+1;ENDIF;ENDIF;ENDIF

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