數(shù)字電路與邏輯設(shè)計10

1、 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edDigital FundamentalsTenth EditionFloydChapter 10 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edQuiz 3 45 minutes Design a Moore

2、 FSM to detect a bit sequence 1110. If such sequence is found, output will be set to 1, otherwise, output will be set to 0. Overlap sequence, if exists, should be detected. show each design step and the last circuit using J-K flip flop. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Right

3、s ReservedFloyd, Digital Fundamentals, 10th edMemories store data in units from one to eight bits. The most common unit is the byte, which by definition is 8 bits. SummaryMemory UnitsComputer memories are organized into multiples of bytes called words. Generally, a word is defined as the number of b

4、its handled as one entity by a computer. By this definition, a word is equal to the internal register size (usually 16, 32, or 64 bits). For historical reasons, assembly language defines a word as exactly two bytes. In assembly language, a 32 bit entity is called a double-word and 64 bits is defined

5、 as a quad-word. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edThe location of a unit of data in a memory is called the address. In PCs, a byte is the smallest unit of data that can be accessed. SummaryMemory Units12345678In a 2-dimensio

6、nal array, a byte is accessed by supplying a row number. For example the blue byte is located in row 7. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edA 3-dimensional array is arranged as rows and columns. Each byte has a unique row and c

7、olumn address.SummaryMemory AddressingHow many bytes are shown? What is the location of the blue byte?b) Row 2, column 8This example is (of course) only for illustration. Typical computer memories have 256 MB or more of capacity.a) 64 B123456781 2 3 4 56 7 8 2009 Pearson Education, Upper Saddle Rive

8、r, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edIn order to read or write to a specific memory location, a binary code is placed on the address bus. Internal decoders decode the address to determine the specific location. Data is then moved to or from the data bus.SummaryMemory A

9、ddressingRowaddressdecoderAddress busData busWriteMemory arrayReadColumn address decoderThe address bus is a group of conductors with a common function. Its size determines the number of locations that can be accessed. A 32 bit address bus can access 232 locations, which is approximately 4G. 2009 Pe

10、arson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryMemory AddressingIn addition to the address bus and data bus, semiconductor memories have read and write control signals and chip select signals. Depending on the type of memory, other signal

11、s may be required.Chip Select (CS) or Chip Enable (CE) is used as part of address decoding. All other inputs are ignored if the Chip Select is not active.Read Enable (RE) and Write Enable (WE) signals are sent from the CPU to memory to control data transfer to or from memory. Output Enable (OE) is a

12、ctive during a read operation, otherwise it is inactive. It connects the memory to the data bus. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryRead and Write OperationsThe two main memory operations are called read and write. A si

13、mplified write operation is shown in which new data overwrites the original data. Data moves to the memory.The address is placed on the address bus.Data is placed on the data bus.A write command is issued.76543210000011111111111110001101000001101111110010000001010011001101011110110012011013Address r

14、egisterData registerAddress busAddress decoderByte organized memory arrayWriteData bus 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryRead and Write OperationsThe read operation is actually a “copy” operation, as the original data

15、is not changed. The data bus is a “two-way” path; data moves from the memory during a read operation.The address is placed on the address bus.A read command is issued.A copy of the data is placed in the data bus and shifted into the data register.76543210000011111111111110001101000001101100000110000

16、001010011001101011101110003110012Address registerData registerAddress busAddress decoderByte organized memory arrayReadData bus 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edRAM is for temporary data storage. It is read/write memory and

17、can store data only when power is applied, hence it is volatile. Two categories are static RAM (SRAM) and dynamic RAM (DRAM).SummaryRandom Access MemoryStaticRAM(SRAM)DynamicRAM(DRAM)AsynchronousSRAM(ASRAM)SynchronousSRAM withburst feature(SB SRAM)ExtendedData OutDRAM(EDO DRAM)BurstEDO DRAM(BEDODRAM

18、)Fast PageModeDRAM(FPM DRAM)SynchronousDRAM(SDRAM)Random-AccessMemory(RAM)Bits stored in a semiconductor latch or flip-flopBits stored as charge on a capacitor 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSRAM uses semiconductor latch m

19、emory cells. The cells are organized into an array of rows and columns. SummaryStatic RAMRow Select 1Row Select 2Row Select nRow Select 0Memory cellData Input/OutputBuffers and ControlData I/OBit 0Data I/OBit 1Data I/OBit 2Data I/OBit 3SRAM is faster than DRAM but is more complex, takes up more spac

20、e, and is more expensive. SRAMs are available in many configurations a typical large SRAM is organized as 512 k X 8 bits. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryAsynchronous Static RAMThe basic organization of an asynchrono

21、us SRAM is shown. Read cycle sequence: A valid address is put on the address bus Chip select is LOW Output enable is LOW Data is placed on the data busWrite cycle sequence: A valid address is put on the address bus Chip select is LOW Write enable is LOW Data is placed on the data busG2G1Address line

22、sAddress lines Eight input buffersI/O0I/O7Output dataCSOEWERowdecoderMemory arrayColumn I/OColumn decoder256 rows x128 columns x8 bitsInput data controlSee text Figure 10-12 for the waveforms 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th e

23、dSummaryDynamic RAM (DRAM)Dynamic RAMs (DRAMs) store data bits as a charge on a capacitor. 1 2DataselectorRowdecoderMemory array1024 rows1024 columns12ColumndecoderInput/Output buffersandSense amplifier12ColumnaddresslatchRowaddresslatchRefresh counterRefreshcontrolandtimingA0/A10A1/A11A2/A12A3/A13A

24、4/A14A5/A15A6/A16A7/A17A8/A18A9/A19CASRASAddresslinesDOUTDINR/WE102410241024DRAMs are simple and cost effective, but require refresh circuitry to prevent losing data. The address lines are multiplexed to reduce the number of address lines. Row address is latched when RAS is LOWColumn address is latc

25、hed when CAS is LOWAddressesRASCASMultiplexed address lines: 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryDynamic RAM (DRAM)A feature with some DRAMs is fast page mode. Fast page mode allows successive read or write operations fr

26、om a series of columns address that are all on the same row.RowaddressColumn 1addressColumn 2addressColumn 3addressColumn naddressValiddataValiddataValiddataValiddataAddressesRASCASR/WDOUTOther types of DRAMs have been developed to speed access and make the processor more efficient. These include ED

27、O DRAMs, BEDO DRAMs and SDRAMs, as described in the text. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryRead-Only Memory (ROM)The ROM family is all considered non-volatile, because it retains data with power removed. It includes v

28、arious members that can be either permanent memory or erasable. Read-OnlyMemory(ROM)ElectricallyErasablePROM(EEPROM)MaskROMErasablePROM(EPROM)UltravioletEPROM(UV EPROM)ProgrammableROM(PROM)ROMs are used to store data that is never (or rarely) changed such as system initialization files. ROMs are non

29、-volatile, meaning they retain the data when power is removed, although some ROMs can be reprogrammed using specialized equipment. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryRead-Only Memory (ROM)A ROM symbol is shown with typi

30、cal inputs and outputs. The triangles on the outputs indicate it is a tri-stated device.ROM 25640&EN7A0255DDDDTo read a value from the ROM, an address is placed on the address bus, the chip is enabled, and a short time later (called the access time), data appears on the data bus.Address input li

31、nesA0A1A2A3A4A5A6A7E0E1O0O1O2O3Data output linesAddress input linesData outputsAddress transitionData output transitiontaChip selectValid data on output linesValid address on input lines 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSumm

32、aryPROMs, EPROMs and EEPROMsPROMs are programmable ROM, in which a fused link is burned open during the programming process. Once the PROM is programmed, it cannot be reversed. An EPROM is an erasable PROM and can be erased by exposure to UV light through a window. To program it, a high voltage is a

33、pplied to VPP and OE is brought LOW.EPROM2048 8&EN01002047ADDDDDDDDO0O1O2O3O4O5O6O7A0A1A2A3A4A5A6A7A8A9A10CE/PGMOEVPPAnother type of erasable PROM is the EEPROM, which can be erased and programmed with electrical pulses. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFl

34、oyd, Digital Fundamentals, 10th edSummaryFlash MemoryFlash memories are high density read/write memories that are nonvolatile. They have the ability to retain charge for years with no applied power.Flash memory uses a MOS transistor with a floating gate as the basic storage cell. The floating gate c

35、an store charge (logic 0) when a positive voltage is applied to the control gate. With little or no charge, the cell stores a logic 1.ControlgateFloatinggateDrainSourceMOStransistorsymbollogic 0 is storedlogic 1 is storedThe flash memory cell can be read by applying a positive voltage to the control

36、 gate. If the cell is storing a 1, the positive voltage is sufficient to turn on the transistor; if it is storing a 0, the transistor is off. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryFlash MemoryFlash memories arranged in arr

37、ays with an active load. For simplicity, only one column is shown. When a specific row and column is selected during a read operation, the active load has current.Row select 0Row select 1Row select nReferenceActive load+VComparatorData out 0Bit line 0Column select 0One drawback to flash memory is th

38、at once a bit has been set to 0, it can be reset to a 1 only by erasing an entire block of memory. Another limitation is that flash memory has a large but finite number of read/write cycles. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed

39、SummaryMemory ExpansionMemory can be expanded in either word size or word capacity or both.To expand word size:m bitsm bitsAddressbusm bits2n bitsControlbusData busRAM 2m 2nDatain/outRAM 22m nRAM 12m nDatain/outDDn bitsn bitsNotice that the data bus size is larger, but the number of address is the s

40、ame. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edDatabusRAM 2M 8Addressbus21 bitsControlbus20 bitsENENRAM 21M 8RAM 11M 88 bits8 bits8 bits20 bitsSummaryMemory ExpansionTo expand word capacity, you need to add an address line as shown i

41、n this example Notice that the data bus size does not change.What is the purpose of the inverter?Only one of the ICs is enabled at any time depending on the logic on the added address line. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edS

42、ummarySIMMs and DIMMsSIMMs (single in-line memory modules) and DIMMs (dual in-line memory modules) are plug-in circuit boards containing the ICs and I/O brought out on edge connectors. SIMMs have a 32-bit data path with I/O on only one side whereas DIMMs have a 64-bit data path with I/O on both side

43、s of the board.SIMM or DIMMSocket on system board 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryFIFO MemoryFIFO means first in-first out. This type of memory is basically an arrangement of shift registers. It is used in applicatio

44、ns where two systems communicate at different rates.64-bit shift register64-bit shift register64-bit shift register64-bit shift registerInputbuffersOutputbufferMarker registerand controlsInputcontrollogicOutputcontrollogicDatainputI0I1I2I3Shift in (SI)Output ready (OR)Shift out (SO)O0O1O2O3Dataoutpu

45、tMemory array stores64 4-bit data wordsControl linesControl lines 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryLIFO MemoryLIFO means last in-first out. In microprocessors, a portion of RAM is devoted to this type of memory, which

46、 is called the stack. Stacks are very useful for temporary storage of internal registers, so that the processor can be interrupted but can easily return to a given task. A special register, called the stack pointer, keeps track of the location that data was last stored on the stack. This will be the

47、 next data to be taken from the stack when needed. FFEC000100100100101000000000Top-of-stackStack pointer 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryMagnetic Hard DriveThe magnetic hard drive is the backbone of computer mass sto

48、rage and is applied to other devices such as digital video recorders. Capacities of hard drives have increased exponentially, with 1 TB (1 trillion bytes!) drives available today.SpindlePlattersActuatorarmsRead/WriteheadsCasePlatters are arranged in tracks (circular shapes) and sectors (pie shaped).

49、 Files are listed in a File Allocation Table, (FAT) that keeps track of file names, locations, size, and more.Hard drive with cover removed 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSummaryOptical StorageThe compact disk (CD) uses a

50、laser to burn tiny pits into the media. Surrounding the pits are flat areas called lands. The CD can be read using a low-power IR laser that detects the difference between pits and lands. Binary data is encoded with a special method called negative non-return to zero encoding. A change from a pit to

51、 a land or a land to a pit represents a binary one, whereas no change represents a zero. A standard 120 mm CD can hold approximately 700 MB of data. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSelected Key Terms Address CapacitySRAMDRA

52、MPROMThe location of a given storage cell or group of cells in memory.The total number of data units (bits, nibbles, bytes, words) that a memory can store.Static random access memory; a type of volatile read/write semiconductor memory. Dynamic random access memory; a type of read/write memory that u

53、ses capacitors as the storage elements and is a volatile read/write memory. Programmable read-only memory; type of semiconductor memory. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th edSelected Key Terms EPROM Flash memoryFIFOLIFOHard disk

54、Erasable programmable read-only memory; a type of semiconductor memory device that typically uses ultraviolet light to erase data.A nonvolatile read/write random access semiconductor memory in which data are stored as charge on a floating gate of a certain type of FET.First in-first out memory. Last

55、 in-first out memoryA magnetic storage device; typically a stack of two or more rigid disks enclosed in a sealed housing. 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed1. Static RAM is a. nonvolatile read only memoryb. nonvolatile read/w

56、rite memoryc. volatile read only memoryd. volatile read/write memory 2008 Pearson Education 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed2. A nonvolatile memory is one that a. requires a clock b. must be refreshed regularly c. retains d

57、ata without power applied d. all of the above 2008 Pearson Education 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed3. The advantage of dynamic RAM over static RAM is thata. it is much fasterb. it does not require refreshingc. it is simpl

58、er and cheaperd. all of the above 2008 Pearson Education 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed4. The first step in a read or write operation for a random access memory is toa. place a valid address on the address busb. enable the memoryc. send or obtain the datad. start a refresh cycle 2008 Pearson Education 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed 2008 Pearson Edu