實驗三十一交通燈實驗

1、眾友科技 數(shù)字邏輯電路實驗三十一 交通燈實驗一、實驗目的 1、熟悉VHDL語言編程，了解實際設計中的優(yōu)化方案。 2、熟悉在Max+plus和ispDesignEXPERT軟件中使用硬件描述語言輸入，編譯的方法。 3、了解幾種硬件描述語言的語言規(guī)范（VHDL，AHDL，Verilog HDL等）。二、實驗硬件要求 1、數(shù)字邏輯電路實驗箱。 2、數(shù)字邏輯電路實驗箱實驗箱上交通燈模塊。 3、LATTICE 1032E適配板和ALTERA 7128適配板。三、實驗內容 1、用硬件描述語言實現(xiàn)交通燈實驗。 2、觀察實驗現(xiàn)象，并對比實際生活中的交通燈。四、實驗原理要完成本實驗，首先必須了解交通路燈的燃滅規(guī)

2、律。本實驗需要用到實驗箱上交通燈模塊中的發(fā)光二極管，即紅、黃、綠各三個。依人們的交通常規(guī)，“紅燈停，綠燈行，黃燈提醒”。其交通燈的燃滅規(guī)律為：初始態(tài)是兩個路口的紅燈全亮，之后，東西路口的綠燈亮，南北路口的紅燈亮，東西方向通車，延時一段時間后，東西路口綠燈滅，黃燈開始閃爍。閃爍若干次后，東西路口紅燈亮，而同時南北路口的綠燈亮，南北方向開始通車，延時一段時間后，南北路口的綠燈滅，黃燈開始閃爍。閃爍若干次后，再切換到東西路口方向，重復上述過程。在實驗中使用數(shù)碼管顯示時間。時間控制由TBJSA和DK兩個模塊聯(lián)合控制。其中TBJSA為計數(shù)器，將脈沖信號從0到15循環(huán)計數(shù)。DK控制在不同時間段的發(fā)光二極管

3、的輸出提示。五、實驗步驟 1、硬件連接（兩個顯示時間用的數(shù)碼管必須為同極性，或共陽或共陰）CPD：接1Hz左右的時鐘信號。CPS：接10KHz左右的時鐘信號。LR1-LR4：接交通燈模塊的R1-R4。LG1-LG4：接交通燈模塊的G1-G4。LY1-LY4：接交通燈模塊的Y1-Y4。D0-D6：接數(shù)碼管模塊的A，B，C，D，E，F(xiàn)，G。SEL0：接實驗箱數(shù)碼管模塊的右邊的數(shù)碼管SEL1：接實驗箱數(shù)碼管模塊的左邊的數(shù)碼管。 2、軟件下載 3、實驗記錄六、實驗VHDL語言程序LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY t1 ISPORT(cpd,

4、cps : INSTD_LOGIC;lr,lg,ly : OUTSTD_LOGIC_VECTOR(4 downto 1);d : OUT STD_LOGIC_VECTOR(6 downto 0);sel : OUT STD_LOGIC_VECTOR(2 downto 0);END t1;ARCHITECTURE a OF t1 ISCOMPONENT tbjsaPORT(cp : INSTD_LOGIC;q : OUTSTD_LOGIC_VECTOR(4 downto 0);END COMPONENT;COMPONENT tbjsbPORT(cp : INSTD_LOGIC;q : OUTST

5、D_LOGIC_VECTOR(2 downto 0);END COMPONENT;COMPONENT dkPORT(cp : IN STD_LOGIC;sj : INSTD_LOGIC_VECTOR(4 downto 1);lr,lg,ly : OUTSTD_LOGIC_VECTOR(4 downto 1);END COMPONENT;COMPONENT sxPORT(sj : IN STD_LOGIC_VECTOR(3 downto 0);kz : IN STD_LOGIC;d : OUTSTD_LOGIC_VECTOR(6 downto 0);END COMPONENT;SIGNAL ns

6、j : STD_LOGIC_VECTOR(4 downto 0);SIGNAL nwk : STD_LOGIC_VECTOR(2 downto 0);BEGINl_a: tbjsa PORT MAP (cpd,nsj);l_b: tbjsb PORT MAP (cps,nwk);l_c: dk PORT MAP (cpd,nsj(4 downto 1),lr,lg,ly);l_d: sx PORT MAP (nsj(3 downto 0),nwk(0),d);sel <= nwk;END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY

7、sx ISPORT(sj : IN STD_LOGIC_VECTOR(3 downto 0);kz : IN STD_LOGIC;d : OUTSTD_LOGIC_VECTOR(6 downto 0);END sx;ARCHITECTURE a OF sx ISSIGNAL nsjh,nsjl : STD_LOGIC_VECTOR(6 downto 0);BEGINwith sj selectnsjh <= "0000110" when "1111", "0000110" when "1110", "

8、;0000110" when "1101", "0000110" when "1100", "0000110" when "1011", "0000110" when "1010", "0000000" when others;with sj selectnsjl <= "0111111" when "0000", "0000110" when "00

9、01", "1011011" when "0010", "1001111" when "0011", "1100110" when "0100", "1101101" when "0101", "1111101" when "0110", "0000111" when "0111", "1111111" when "1

10、000", "1101111" when "1001", "0111111" when "1010", "0000110" when "1011", "1011011" when "1100", "1001111" when "1101", "1100110" when "1110", "1101101" when "

11、1111", "0000000" when others;with kz selectd <= nsjl when '0', nsjh when '1', "0000000" when others;END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY tbjsa ISPORT(cp : INSTD_LOGIC;q : OUTSTD_LOGIC_VECTOR(4 downto 0);END tbjsa;ARCHITECTURE a OF tbjsa IS

12、COMPONENT JKFF PORT (j : IN STD_LOGIC; k : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC);END COMPONENT;SIGNAL vcc : STD_LOGIC;SIGNAL njk,nq : STD_LOGIC_VECTOR(4 downto 0);BEGINvcc <= '1'njk(0) <= '1'njk(1) <= nq(0);njk(2) <=

13、nq(0)and nq(1);njk(3) <= nq(0)and nq(1)and nq(2);njk(4) <= nq(0)and nq(1)and nq(2)and nq(3);l1:FOR i IN 4 downto 0 GENERATEn_jk: JKFF PORT MAP (njk(i),njk(i),cp,vcc,vcc,nq(i);q(i) <= not nq(i);END GENERATE;END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY tbjsb ISPORT(cp : INSTD_LOGIC;q

14、 : OUTSTD_LOGIC_VECTOR(2 downto 0);END tbjsb;ARCHITECTURE a OF tbjsb ISCOMPONENT JKFF PORT (j : IN STD_LOGIC; k : IN STD_LOGIC; clk : IN STD_LOGIC; clrn: IN STD_LOGIC; prn : IN STD_LOGIC; q : OUT STD_LOGIC);END COMPONENT;SIGNAL vcc : STD_LOGIC;SIGNAL njk,nq : STD_LOGIC_VECTOR(1 downto 0);BEGINvcc &l

15、t;= '1'njk(0) <= '1'njk(1) <= nq(0);l1:FOR i IN 1 downto 0 GENERATEn_jk: JKFF PORT MAP (njk(i),njk(i),cp,vcc,vcc,nq(i);END GENERATE;q(0) <= nq(0);q(1) <= '0'q(2) <= nq(1);END a;LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY dk ISPORT(cp : IN STD_LOGIC;sj : INS

16、TD_LOGIC_VECTOR(4 downto 1);lr,lg,ly : OUTSTD_LOGIC_VECTOR(4 downto 1);END dk;ARCHITECTURE a OF dk ISSIGNAL ra,rb,ga,gb,ya,yb : STD_LOGIC;BEGINra <= sj(4);rb <= not sj(4);ga <= (not sj(4)and(sj(3)or(sj(2)and sj(1)or(sj(2)xor sj(1)and cp);gb <= sj(4)and(sj(3)or(sj(2)and sj(1)or(sj(2)xor sj(1)and cp);ya <= (not sj(4)and(not(sj(3)or sj(2)or sj(1);yb <= sj(4)and(not(sj(3)or sj(2)or sj(1);lr(1) <= ra;lr(2) <= rb;lr(3)