16位模型機的設(shè)計

1、16位CPU的設(shè)計要求：此模型機的功能是將存儲區(qū)的數(shù)據(jù)塊復(fù)制到另一個存儲區(qū)。匯編代碼如下：STARTLOADIR1,0010H;源操作數(shù)地址送R1LOADIR20030H;目的操作數(shù)地址送R2LOADIRG002FH;結(jié)束地址送R6NEXTLOADR3R1;取數(shù)STORER2,R3;存數(shù)BRANCHGTISTART;如果R1>R6則車專向STARTINCR1;修改源地址INCR2;修改目的地址BRANCHINEXT;轉(zhuǎn)向NEXT1 .16位CPU勺組成結(jié)構(gòu)2 .指令系統(tǒng)的設(shè)計一、指令格式1）單字指令格式操作弱源操作數(shù)目的操作數(shù)OpcodeSRCDST15141312115432102）雙

2、字指令格式操作碼源操作數(shù)目的操作數(shù)OpcodeSRCBST1514I3121154321016位操作數(shù)15M131211109876543210指令操作碼操作碼指令功能00001LOAD裝載數(shù)據(jù)到寄存器00010STORE將寄存器的數(shù)據(jù)存入到存儲器00100LOADI將立即數(shù)裝入到寄存器00101BRANCHI無條件轉(zhuǎn)移到由立即數(shù)指定的地址00110BRANCHGTIi如果源寄存器內(nèi)容大于目的寄存器的內(nèi)容，則轉(zhuǎn)移到由立即數(shù)指定的地址00111INC寄存器內(nèi)容加1指令依據(jù)以上設(shè)計的指令系統(tǒng)，則完成數(shù)據(jù)塊復(fù)制的程序如下:址地碼機器指令功能說明0002001LOADIR1,源操作數(shù)地址送R10H00

3、0H00100010H1HH0002002LOADIR2,目的操作數(shù)地址送R22H000H00300030H3HH0002006LOADIR6,結(jié)束地址送R64H000H002F002FH5HH0006H080BHLOADR3R1取數(shù)0007H101AHSTORER2,R3存數(shù)0008H0009H300EH0000HBRANCHGTI0000如果R1大于R6,則轉(zhuǎn)向地址0000000AH3801HINCR1修改源地址000BH3802HINCR2修改目的地址000CH000DH2800H0006HBRANCHI0006H轉(zhuǎn)向00006H,實現(xiàn)循環(huán)3.VHD毆計一、程序包：說明運算器的功能、移動

4、寄存器的操作、比較器的比較類型和用于CPU空制的狀態(tài)類型。libraryieee;usecpu_libissubtypet_shiftisunsigned(3downto0);constantshftpass:unsigned(3downto0):="0000"constantsftl:unsigned(3downto0):="0001"constantsftr:unsigned(3downto0):="0010"constantrotl:unsigned(3downto0):="0011"constantrotr

5、:unsigned(3downto0):="0100"subtypet_aluisunsigned(3downto0);constantalupass:unsigned(3downto0):="0000"constantandOp:unsigned(3downto0):="0001"constantorOp:unsigned(3downto0):="0010"constantnotOp:unsigned(3downto0):="0011"constantxorOp:unsigned(3downt

6、o0):="0100"constantplus:unsigned(3downto0):="0101"constantalusub:unsigned(3downto0):="0110"constantinc:unsigned(3downto0):="0111"constantdec:unsigned(3downto0):="1000"constantzero:unsigned(3downto0):="1001"subtypet_compisunsigned2downto0);c

7、onstanteq:unsigned(2downto0):="000"constantneq:unsigned(2downto0):="001"constantgt:unsigned(2downto0):="010"constantgte:unsigned(2downto0):="011"constantlt:unsigned(2downto0):="100"constantlte:unsigned(2downto0):="101"subtypet_regisstd_logi

8、c_vector(2downto0);typestateis(reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,load,store,move,10ad2,load3,load4,store2,store3,store4,move2,move3,move4,incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,bra

9、I4,braI5,braI6,10adi2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4);subtypebit16isstd_1ogic_vector(15downto0);endcpu_1ib;、基本部件的設(shè)計1）運算器的設(shè)計功能Sei輸入操作說明0000C=A通過PASS0001C=AANDB與0010C=AORB或0011C=NOTA辛0100C=AXORB異或0101C=A+B加法JoinC=A-B減法0111C=A+1加一1000C=A-1減11001c=o清。libraryieee;usealuisport(a,b:inbit16;sel:

10、int_alu;c:outbit16);endalu;architecturert1ofaluisbeginprocess(a,b,sel)begincaseseliswhenalupass=>c<=aafter1ns;whenandop=>c<=aandbafter1ns;whenorop=>c<=aorbafter1ns;whenxorop=>c<=axorbafter1ns;whennotop=>c<=notaafter1ns;whenplus=>c<=a+bafter1ns;whenalusub=>c<

11、=a-bafter1ns;wheninc=>c<=a+"0000000000000001"after1ns;whendec=>c<=a-"0000000000000001"after1ns;whenzero=>c<="0000000000000000"after1ns;whenothers=>c<="0000000000000000"after1ns;endcase;endprocess;endrt1;2)比較器rccmp比較類型操作說明00GE偌于）?"i

12、ii=brcoinpout=l001ueq（不等于）若竊二Bcoinpaut=l010尊（大于）若coinpout=lOilgte（大于等于）若tcompout=l100It（小于）若compout=l101依小于等于）若si<=b*compout=1其他cnmpoiit=Ocompcompoutsel2.Olibraryieee;usecompisport(a,b:inbit16;sel:int_comp;compout:outbit);endcomp;architecturert1ofcompisbeginprocess(a,b,sel)begincaseseliswheneq=&g

13、t;ifa=bthencompout<='1'after1ns;elsecompout<='0'after1ns;endif;whenneq=>ifa/=bthencompout<='1'after1ns;elsecompout<='0'after1ns;endif;whengt=>ifa>bthencompout<='1'after1ns;elsecompout<='0'after1ns;endif;whengte=>ifa>=bt

14、hencompout<='1'after1ns;elsecompout<='0'after1ns;endif;whenlt=>ifa<bthencompout<='1'after1ns;elsecompout<='0'after1ns;endif;whenlte=>ifa<=bthencompout<='1'after1ns;elsecompout<='0'after1ns;endif;whenothers=>compout<=

15、'0'after1ns;endcase;endprocess;tshift移位類型000直通001無符號數(shù)左移ow無符號蛾右蜃.on循環(huán)左將100循環(huán)右移其他輸出0endrt1;3）移位寄存器ishiftal5.O.sel2,.0yi5.olibraryieee;useshiftisport(a:inbit16;sel:int_shift;y:outbit16);endshift;architecturert1ofshiftisbeginprocess(a,sel)begincaseseliswhenshftpass=>y<=aafter1ns;whensftl=&

16、gt;y<=a(14downto0)&'0'after1ns;whensftr=>y<='0'&a(15downto1)after1ns;whenrotl=>y<=a(14downto0)&a(15)after1ns;whenrotr=>y<=a(0)&a(15downto1)after1ns;whenothers=>y<="0000000000000000"after1ns;endcase;endprocess;endrt1;4）寄存器a15.0q15.O

17、：elkiins14libraryieee;useregisport(a:inbit16;clk:instd_logic;q:outbit16);endreg;architecturert1ofregisbeginprocessbeginwaituntilclk'eventandclk='1'q<=aafter1ns;endprocess;endrt1;5)寄存器組libraryieee;useregarrayisport(data:inbit16;sel:int_reg;en,clk:instd_logic;q:outbit16);endregarray;arc

18、hitecturert1ofregarrayistypet_ramisarray(0to7)ofbit16;signaltemp_data:bit16;beginprocess(clk,sel)variableramdata:t_ram;beginifclk'eventandclk='1'thenramdata(conv_integer(sel):=data;endif;temp_data<=ramdata(conv_integer(sel)after1ns;endprocess;process(en,temp_data)beginifen='1'

19、thenq<=temp_dataafter1ns;elseq<="ZZZZZZZZZZZZZZZZ"after1ns;endif;endprocess;endrt1;6)三態(tài)寄存器#In<irBiiIiras”i*wiiumthwtiiibihifh>iireinimtiivIinsT8；elkIin11叫5一口q15.0T;trjneg一libraryieee;usetriregisport(a:inbit16;en,clk:instd_logic;q:outbit16);endtrireg;architecturert1oftriregissig

20、nalval:bit16;beginprocessbeginwaituntilclk'eventandclk='1'val<=a;endprocess;process(en,val)beginifen='1'thenq<=valafter1ns;elsifen='0'thenq<="ZZZZZZZZZZZZZZZZ”after1ns;elseq<="XXXXXXXXXXXXXXXX"after1ns;endif;endprocess;endrt1;7）控制器采用狀態(tài)機實現(xiàn),I-1-一p

21、a-3-，.W/44HGontroH11progCnyWiIock-firogCfiyRd伯鼎-*hsnPeq；15.01-8mMU-I1;1m成白犯dlshiftSc(2.曰1吟訓(xùn)3,0,QcipRp«lRilopRe5WTinstrWregs&ip.0-間母；憐酬IfiHAtLl1iristJ一，“一一一一libraryIEEE;usecontrolisport(clock,reset,compout:instd_logic;instrReg:inbit16;progCntrWr,progCntrRd,addrRegWr,outRegWr,outRegRd:outstd_

22、logic;shiftSel:outt_shift;aluSel:outt_alu;compSel:outt_comp;opRegRd,opRegWr,instrWr,regRd,regWr,rw,vma:outstd_logic;regSel:outt_reg);endcontrol;architecturertlofcontrolissignalcurrent_state,next_state:state;beginprocess(current_state,instrReg,compout)beginprogCntrWr<='0'progCntrRd<=

23、9;0'addrRegWr<='0'outRegWr<='0'outRegRd<='0'shiftSel<=shftpass;aluSel<=alupass;compSel<=eq;opRegRd<='0'opRegWr<='0'instrWr<='0'regSel<="000"regRd<='0'regWr<='0'rw<='0'vma<=

24、'0'casecurrent_stateiswhenreset1=>aluSel<=zeroafter1ns;shiftSel<=shftpass;next_state<=reset2;whenreset2=>aluSel<=zero;shiftSel<=shftpass;outRegWr<='1'next_state<=reset3;whenreset3=>outRegRd<='1'next_state<=reset4;whenreset4=>outRegRd<

25、='1'progCntrWr<='1'addrRegWr<='1'next_state<=reset5;whenreset5=>vma<='1'rw<='0'next_state<=reset6;whenreset6=>vma<='1'rw<='0'instrWr<='1'next_state<=execute;whenexecute=>caseinstrReg(15downto11)isw

26、hen"00000"=>next_state<=incPc;-nopwhen"00001"=>regSel<=instrReg(5downto3);regRd<='1'next_state<=load2;when"00010"=>regSel<=instrReg(2downto0);regRd<='1'next_state<=store2;-storewhen"00011"=>regSel<=instrReg(5

27、downtoaluSel<=alupass;shiftSel<=shftpass;next_state<=move2;when"00100"=>shiftsel<=shftpass;next_state<=loadI2;when"00101"=>shiftsel<=shftpass;next_state<=braI2;when"00110"=>progcntrRd<='1'progcntrRd<='1'regSel<=inst

28、rReg(53);regRd<='1'alusel<=inc;alusel<=inc;downto3);regRd<='1'next_state<=bgtI2;-BranchGTImmwhen"00111"=>regSel<=instrReg(2downto0);regRd<='1'alusel<=inc;shiftsel<=shftpass;next_state<=inc2;whenothers=>next_state<=incPc;endcase

29、;whenload2=>regSel<=instrReg(5downto3);regRd<='1'addrregWr<='1'next_state<=load3;whenload3=>vma<='1'rw<='0'next_state<=load4;whenload4=>vma<='1'rw<='0'regSel<=instrReg(2downto0);regWr<='1'next_state<

30、=incPc;whenstore2=>regSel<=instrReg(2downto0);regRd<='1'addrregWr<='1'next_state<=store3;whenstore3=>regSel<=instrReg(5downto3);regRd<='1'next_state<=store4;whenstore4=>regSel<=instrReg(5downto3);regRd<='1'rw<='1'next_sta

31、te<=incPc;whenmove2=>regSel<=instrReg(5downto3);regRd<='1'aluSel<=alupass;shiftsel<=shftpass;outRegWr<='1'next_state<=move3;whenmove3=>outRegRd<='1'next_state<=move4;whenmove4=>outRegRd<='1'regSel<=instrReg(2downto0);regWr<

32、='1'next_state<=incPc;whenloadI2=>progcntrRd<='1'alusel<=inc;shiftsel<=shftpass;outregWr<='1'next_state<=loadI3;whenloadI3=>outregRd<='1'next_state<=loadI4;whenloadI4=>outregRd<='1'progcntrWr<='1'addrregWr<=

33、9;1'next_state<=loadI5;whenloadI5=>vma<='1'rw<='0'next_state<=loadI6;whenloadI6=>vma<='1'rw<='0'regSel<=instrReg(2downto0);regWr<='1'next_state<=incPc;whenbraI2=>progcntrRd<='1'alusel<=inc;shiftsel<=shft

34、pass;outregWr<='1'next_state<=braI3;whenbraI3=>outregRd<='1'next_state<=braI4;whenbraI4=>outregRd<='1'progcntrWr<='1'addrregWr<='1'next_state<=braI5;whenbraI5=>vma<='1'rw<='0'next_state<=braI6;whenbraI6

35、=>vma<='1'rw<='0'progcntrWr<='1'next_state<=loadPc;whenbgtI2=>regSel<=instrReg(5downto3);regRd<='1'opRegWr<='1'next_state<=bgtI3;whenbgtI3=>opRegRd<='1'regSel<=instrReg(2downto0);regRd<='1'compsel<=g

36、t;next_state<=bgtI4;whenbgtI4=>opRegRd<='1'after1ns;regSel<=instrReg(2downto0);regRd<='1'compsel<=gt;ifcompout='1'thennext_state<=bgtI5;elsenext_state<=incPc;endif;whenbgtI5=>progcntrRd<='1'alusel<=inc;shiftSel<=shftpass;next_state&

37、lt;=bgtI6;whenbgtI6=>progcntrRd<='1'alusel<=inc;shiftsel<=shftpass;outregWr<='1'next_state<=bgtI7;whenbgtI7=>outregRd<='1'next_state<=bgtI8;whenbgtI8=>outregRd<='1'progcntrWr<='1'addrregWr<='1'next_state<=bgtI9

38、;whenbgtI9=>vma<='1'rw<='0'next_state<=bgtI10;whenbgtI10=>vma<='1'rw<='0'progcntrWr<='1'next_state<=loadPc;wheninc2=>regSel<=instrReg(2downto0);regRd<='1'alusel<=inc;shiftsel<=shftpass;outregWr<='1'n

39、ext_state<=inc3;wheninc3=>outregRd<='1'next_state<=inc4;wheninc4=>outregRd<='1'regsel<=instrReg(2downto0);regWr<='1'next_state<=incPc;whenloadPc=>progcntrRd<='1'next_state<=10adpc2;whenloadPc2=>progcntrRd<='1'addrRegWr

40、<='1'next_state<=10adpc3;when10adpc3=>vma<='1'rw<='0'next_state<=10adpc4;when10adpc4=>vma<='1'rw<='0'instrWr<='1'next_state<=execute;whenincPc=>progcntrRd<='1'a1use1<=inc;shiftse1<=shftpass;next_stat

41、e<=incPc2;whenincPc2=>progcntrRd<='1'alusel<=inc;shiftsel<=shftpass;outregWr<='1'next_state<=incPc3;whenincPc3=>outregRd<='1'next_state<=incPc4;whenincPc4=>outregRd<='1'progcntrWr<='1'addrregWr<='1'next_state<=incPc5;whenincPc5=>vma<='1'rw<='0'next_st