verilog CPU設(shè)計

1、通用計算機與單片機在硬件結(jié)構(gòu)上的比較通用計算機與單片機在硬件結(jié)構(gòu)上的比較 微型計算機系統(tǒng) 單片機系統(tǒng)微型計算機的組成框圖（由多個IC芯片組裝在一個主電路板上）數(shù)據(jù)RAMCPU并行I/O程序ROM定時/計數(shù)器串型端口中斷控制器擴展I/O端口系統(tǒng)總線（DB、AB、CB）所有基本單元都組裝在一個IC芯片上MCS-51單片機MCS-51 MCS-51 單片機內(nèi)部方框圖單片機內(nèi)部方框圖 時鐘電路時鐘電路4KROM程序存儲器程序存儲器256BRAM數(shù)據(jù)存儲器數(shù)據(jù)存儲器2X16位位定時定時/計數(shù)器計數(shù)器CPU處理器處理器64KB總線總線擴展控制器擴展控制器可編程可編程I/O端口端口P0-3可編程可編程串行口

2、串行口MCS-51單片機外型圖（單片機外型圖（DIP-40封裝）封裝） MCS-51單片機的邏輯符號圖單片機的邏輯符號圖VCCRSTXTAL1 P0口XTAL2/EA/PSENALE P1口P3口RXDTXD/INT0/INT1 P2口T0T1/WR/RDGND87C51EPROM型AT89C51ATMELFLASH型MCS-51MCS-51單片機的外形和邏輯符號單片機的外形和邏輯符號cpuABDB地址地址譯碼器譯碼器ROMRAMclockresetreadwrite1 1）振蕩周期）振蕩周期 指為單片機提供定時信號的振蕩源的周期，若為內(nèi)部產(chǎn)生方式時，為石指為單片機提供定時信號的振蕩源的周期，

3、若為內(nèi)部產(chǎn)生方式時，為石英晶體的振蕩周期。英晶體的振蕩周期。2 2）時鐘周期）時鐘周期 也稱為狀態(tài)周期，用也稱為狀態(tài)周期，用S表示。時鐘周期是計算機中最基本的時間單位，在表示。時鐘周期是計算機中最基本的時間單位，在一個時鐘周期內(nèi)，一個時鐘周期內(nèi)，CPUCPU完成一個最基本的動作。完成一個最基本的動作。MCS51單片機中一個時鐘周期單片機中一個時鐘周期為振蕩周期的為振蕩周期的2 2倍。倍。3 3）機器周期）機器周期 完成一個基本操作（例如，取指令、存儲器讀、存儲器寫等）所需要的完成一個基本操作（例如，取指令、存儲器讀、存儲器寫等）所需要的時間稱為機器周期。時間稱為機器周期。MCS51的一個機器周

4、期含有的一個機器周期含有6 6個時鐘周期。個時鐘周期。4 4）指令周期）指令周期 完成一條指令所需要的時間稱為指令周期。完成一條指令所需要的時間稱為指令周期。MCS5l的指令周期含的指令周期含1 14 4個機器周期不等，其中多數(shù)為單周期指令，還有個機器周期不等，其中多數(shù)為單周期指令，還有2 2周期和周期和4 4周期指令。周期指令。4 4周期指令只周期指令只有乘、除兩條指令。有乘、除兩條指令。P1P2S1振蕩周期時鐘周期機器周期機器周期指令周期指令周期XTAL2(OSC)S2S3S4S5S6S1S2S4S5S3S6P1P1P1P1P1P1P1P1P1P1P1P2P2P2P2P2P2P2P2P2P

5、2P2若MCS-51單片機外接晶振為12MHz時，則單片機的四個周期的具體值為：振蕩周期1/12MHz1/12s0.0833s時鐘周期1/6s0.167s機器周期1s指令周期14s單片機指令功能一覽表單片機指令功能一覽表 指令指令機器碼機器碼功能說明功能說明數(shù)據(jù)傳送類指令數(shù)據(jù)傳送類指令 操作碼操作碼 + 【操作數(shù)操作數(shù)】MOV A,RnE8EF 寄存器送累加器寄存器送累加器MOV A,dirE5 dir直接字節(jié)送累加器直接字節(jié)送累加器MOV A,#data74 data 立即數(shù)送累加器立即數(shù)送累加器NOP00空操作空操作MOV dir,#data75 dir data立即數(shù)送直接字節(jié)立即數(shù)送直

6、接字節(jié)MOVX A,DPTR E0外部外部RAM(16位地址位地址)讀操作讀操作 MOV A,#55NOPMOVX A,DPTR745500E00000000100100011ROM122333000000000100100011RAMA?DPTR0010data7.0enaclkrstaccum7.0accuminst2Parameter.Value.Type.data7.0accum7.0alu_enaopcode2.0clkalu_out7.0zeroaluinst3in7.0data_enadata7.0datactlinst4fetchpc_addr12.0ir_addr12.0ad

7、dr12.0adrinst5Parameter.Value.Type.clkzeroenaopcode2.0inc_pcload_accload_pcrdwrload_irdatactl_enahaltmachineinst6fetchrstclkenamachinectlinst7ir_addr12.0loadclkrstpc_addr12.0counterinst11clkresetfetchalu_enaclk_geninstParameter.Value.Type.VCCclkINPUTVCCresetINPUTVCCdata7.0BIDIRaddr12.0OUTPUTrdOUTPUT

8、wrOUTPUThaltOUTPUTdata7.0enaclkrstopc2.0iraddr12.0registerinst15data7.0enaclkrstaccum7.0accuminst2Parameter.Value.Type.data7.0accum7.0alu_enaopcode2.0alu_out7.0zeroaluclkresetfetchalu_enaclk_geninstParameter.Value.Type.VCCclkINPUTVCCresetINPUTdata7.0enaclkrstopc2.0iraddr12.0registerinst15cpuABDB地址地址

9、譯碼器譯碼器ROMRAMclockresetreadwriteD15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0高8位低8位地址碼指令碼 alu_ena累加器A指令寄存器IR算邏單元ALU數(shù)據(jù)控制地址選擇程序計數(shù)器PC控制狀態(tài)機時鐘信號ABDBhaltrdwrclkrstload_accinc_pcload_pcload_irfetchdatactl_ena累加器A指令寄存器IR算邏單元ALU數(shù)據(jù)控制地址選擇程序計數(shù)器PC控制狀態(tài)機時鐘信號ABDBhaltrdwrclkrstload_accfetchinc_pcload_pcload_i

10、ralu_enadatactl_enahaltload_irrdinc_pcalu_enafetchclk01234567halt指令指令累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567LDA 1000B000EE0110001001RAMEEload_accaddress000000011000B00000000001ROM0000020002累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機時鐘信號A

11、BDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567ADD 10015001EE1110001001RAM11load_accaddress000200031001500100020003ROM00040004累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567STO 1001D001EE0110001001RA

12、MFFwraddress000400051001D00100040005ROM00060006Idle S1 S2 S3 S4 S5 S6 S7 S8 S1 S2 S3 S4 S5 S6 S7 S8 S1 S2 S3 S4 S5 S6 S7 S8 idle always (posedge clk) if(reset) begin fetch=0; alu_ena=0; state=idle; end else begin case (state) default:state=idle; endcase endcase (state) S1: begin fetch=1; state=S2; e

13、nd S2: state=S3; S3: state=S4; S4: state=S5; S5: begin state=S6; fetch=0; end S6: begin state=S7; alu_ena=1; end S7: begin alu_ena=0; state=S8; end S8: state=S1; idle: state=S1; default:state=idle;endcase data7.0enaclkrstopc_iraddr15.0registerinst1resetclkload_iropcode2:0ir_addr12:0resetclkload_acca

14、lu_out7:0data7.0enaclkrstaccum7.0accuminst2data7.0enaclkrstaccum7.0accuminst2 in7.0data_enadata7.0datactlinst4data7:0alu_out7:0datactl_enafetchpc_addr12.0ir_addr12.0addr12.0adrinst5ir_addr12.0loadclkrstpc_addr12.0counterinst1000001010011100101110111 3b100: begin if(opcode=JMP) begin inc_pc,load_acc,

15、load_pc,rd=4b0010; wr,load_ir,datactl_ena,halt=4b0000; end else if(opcode=ADD|opcode=ANDD|opcode=XORR|opcode=LDA) begin inc_pc,load_acc,load_pc,rd=4b0001; wr,load_ir,datactl_ena,halt=4b0000; end else if(opcode=STO) begin inc_pc,load_acc,load_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b0010; end else

16、 begin inc_pc,load_acc,load_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b0000; end state=3b101; end 3b101: begin /operation if(opcode=ADD|opcode=ANDD|opcode=XORR|opcode=LDA) begin inc_pc,load_acc,load_pc,rd=4b0101; wr,load_ir,datactl_ena,halt=4b0000; end else if(opcode=SKZ & zero=1) begin inc_pc,

17、load_acc,load_pc,rd=4b1000; wr,load_ir,datactl_ena,halt=4b0000; end else if(opcode=JMP) begin inc_pc,load_acc,load_pc,rd=4b1010; wr,load_ir,datactl_ena,halt=4b0000; end else if(opcode=STO) begin inc_pc,load_acc,load_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b1010; end else begin inc_pc,load_acc,loa

18、d_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b0000; end state=3b110; end 3b110:/idle begin if(opcode=STO) begin inc_pc,load_acc,load_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b0010; end else if(opcode=ADD|opcode=ANDD|opcode=XORR|opcode=LDA) begin inc_pc,load_acc,load_pc,rd=4b0001; wr,load_ir,datact

19、l_ena,halt=4b0000; end else begin inc_pc,load_acc,load_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b0000; end state=3b111; end 3b111: begin if(opcode=SKZ & zero=1) begin inc_pc,load_acc,load_pc,rd=4b1000; wr,load_ir,datactl_ena,halt=4b0000; end else begin inc_pc,load_acc,load_pc,rd=4b0000; wr,loa

20、d_ir,datactl_ena,halt=4b0000; end state=3b000; end default: begin inc_pc,load_acc,load_pc,rd=4b0000; wr,load_ir,datactl_ena,halt=4b0000; state=3b000; end endcase end endtask /-end of task ctl_cycle- endmodulecpuABDB地址地址譯碼器譯碼器ROMRAMclockresetreadwriteaddr12.0rom_selram_seladdr_decodeinst8module addr_

21、decode(addr,rom_sel,ram_sel); output rom_sel,ram_sel; input 12:0addr; reg rom_sel,ram_sel; always (addr) casex(addr) 13b1_1xxx_xxxx_xxxx:rom_sel,ram_sel=2b01; 13b0_xxxx_xxxx_xxxx:rom_sel,ram_sel=2b10; 13b1_0 xxx_xxxx_xxxx:rom_sel,ram_sel=2b10; default:rom_sel,ram_sel=2b00; endcaseendmodulemodule add

22、r_decode(addr,rom_sel,ram_sel); output rom_sel,ram_sel; input 12:0addr; reg rom_sel,ram_sel; always (addr) casex(addr) 13b1_1xxx_xxxx_xxxx:rom_sel,ram_sel=2b01; 13b0_xxxx_xxxx_xxxx:rom_sel,ram_sel=2b10; 13b1_0 xxx_xxxx_xxxx:rom_sel,ram_sel=2b10; default:rom_sel,ram_sel=2b00; endcaseendmoduleaddr9.0e

23、nareadwritedata7.0raminst9module rom(data,addr,read,ena); output 7:0data; input 12:0addr; input ena,read; reg 7:0mem13h1fff:0; assign data=(read&ena)?memaddr:8hzz;endmoduleaddr12.0readenadata7.0rominst10D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0高8位低8位地址碼指令碼17.5 RISC_CPU 17.5 RISC_CPU

24、尋址方式和指令系統(tǒng)尋址方式和指令系統(tǒng)LDA 010FH8EH00H77H56HEDHFFHFFH00H 010FH 010EH 010DH010CH56H地址碼指令碼17.5 RISC_CPU 17.5 RISC_CPU 尋址方式和指令系統(tǒng)尋址方式和指令系統(tǒng)17.5 RISC_CPU 17.5 RISC_CPU 尋址方式和指令系統(tǒng)尋址方式和指令系統(tǒng)17.5 RISC_CPU 17.5 RISC_CPU 尋址方式和指令系統(tǒng)尋址方式和指令系統(tǒng)累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadatalo

25、ad_irrdinc_pcalu_enafetchclk01234567LDA 1000B000EE0110001001RAMEEload_accaddress000000011000B00000000001ROM0000020002累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567ADD 10015001EE1110001001RAM11load_accaddress000200031001500100020003

26、ROM00040004累加器指令寄存器算邏單元數(shù)據(jù)控制地址選擇程序計數(shù)器控制狀態(tài)機時鐘信號ABDBrdload_accfetchinc_pcload_iralu_enadataload_irrdinc_pcalu_enafetchclk01234567STO 1001D001EE0110001001RAMFFwraddress000400051001D00100040005ROM0006000600111_00000 /00 BEGIN: JMP TEST_JMP0011_1100 000_00000 /02 HLT0000_0000000_00000 /04 HLT0000_0000101_

27、11000 /06 JMP_OK: LDA DATA_10000_0000001_00000 /08 SKZ0000_0000000_00000 /0A HLT0000_0000101_11000 /0C LDA DATA_20000_0001001_00000 /0E SKZ0000_0000111_00000 /10 JMP SKZ_OK0001_0100000_00000 /12 HLT0000_0000110_11000 /14 SKZ_OK: STO TEMP0000_0010101_11000 /16 LDA DTAT_10000_0000110_11000 /18 STO TEM

28、P0000_0010101_11000 /1A LDA TEMP0000_0010001_00000 /1C SKZ0000_0000000_00000 /1E HLT0000_0000100_11000 /20 XORR DTAT_20000_0001001_00000 /22 SKZ0000_0000000_00000 /24 HLT0000_0000111_00000 /26 JMP XORR_OK0010_0100100_11000 /28 XORR_OK: XORR DATA_20000_0001001_00000 /2A SKZ0000_0000000_00000 /2C HLT0

29、000_0000 000_00000 /2E EDN: HLT0000_0000111_00000 /30 JMP BEGIN0000_00003C111_00000 /3C TST_JMP: JMP JMP_OK0000_0110000_00000 /3E HLT00 00000000 /1800 DATA_1 11111111 /1801 DATA_2 10101010 /1802 TEMP 17.6 RISC_CPU 17.6 RISC_CPU 模塊的調(diào)試模塊的調(diào)試cpuABDB地址地址譯碼器譯碼器ROMRAMclockresetreadwritedata7.0enaclkrstaccu

30、m7.0accuminst2Parameter.Value.Type.data7.0accum7.0alu_enaopcode2.0clkalu_out7.0zeroaluinst3in7.0data_enadata7.0datactlinst4fetchpc_addr12.0ir_addr12.0addr12.0adrinst5Parameter.Value.Type.clkzeroenaopcode2.0inc_pcload_accload_pcrdwrload_irdatactl_enahaltmachineinst6fetchrstclkenamachinectlinst7ir_add

31、r12.0loadclkrstpc_addr12.0counterinst11clkresetfetchalu_enaclk_geninstParameter.Value.Type.VCCclkINPUTVCCresetINPUTVCCdata7.0BIDIRaddr12.0OUTPUTrdOUTPUTwrOUTPUThaltOUTPUTdata7.0enaclkrstopc2.0iraddr12.0registerinst15include clk_gen.vinclude register.vinclude accum.vinclude adr.vinclude alu.vinclude

32、machine.vinclude machinectl.vinclude counter.vinclude datactl.vtimescale 1ns/1nsmodule cpu(clk,reset,halt,rd,wr,addr,data,opcode,fetch,ir_addr,pc_addr); input clk,reset; output rd,wr,halt; output 12:0addr; output 2:0opcode; output fetch; output 12:0ir_addr,pc_addr; inout 7:0data; wire clk,reset,halt

33、; wire 7:0data; wire 12:0addr; wire rd,wr， wire fetch,alu_ena; wire 2:0opcode; wire 12:0ir_addr,pc_addr; wire 7:0alu_out,accum; wire zero,inc_pc,load_acc,load_pc,load_ir,data_ena,contrl_ena;endmodulemodule cpu(clk,reset,halt,rd,wr,addr,data,opcode,fetch,ir_addr,pc_addr); clk_gen m_clkgen(.clk(clk),.

34、reset(reset),.fetch(fetch),.alu_ena(alu_ena); register m_register(.data(data),.ena(load_ir),.rst(reset),.clk(clk),.opc_iraddr(opcode,ir_addr); accum m_accum(.data(alu_out),.ena(load_acc),.clk(clk),.rst(reset),.accum(accum); alu m_alu(.data(data),.accum(accum),.clk(clk),.alu_ena(alu_ena),.opcode(opco

35、de),.alu_out(alu_out),.zero(zero); machinectl m_machinectl(.clk(clk),.rst(reset),.fetch(fetch),.ena(contrl_ena); machine m_machine(.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),.rd(rd),.wr(wr),.load_ir(load_ir), .clk(clk),.datactl_ena(data_ena),.halt(halt),.zero(zero),.ena(contrl_ena),.opcod

36、e(opcode); datactl m_datactl(.in(alu_out),.data_ena(data_ena),.data(data); adr m_adr(.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr),.addr(addr); counter m_counter(.clk(inc_pc),.rst(reset),.ir_addr(ir_addr),.load(load_pc),.pc_addr(pc_addr); endmoduleinclude cpu.vinclude ram.vinclude rom.vinclude a

37、ddr_decode.vtimescale 1ns/1nsdefine PERIOD 100module topcpu; reg reset_req,clock; integer test; reg (3*8):0mnemonic; reg 12:0PC_addr,IR_addr; wire 7:0data; wire 12:0addr; wire rd,wr,halt,ram_sel,rom_sel; wire 2:0opcode; wire fetch; wire 12:0ir_addr,pc_addr;.endmodulemodule topcpu; reg reset_req,cloc

38、k;. cpu t_cpu(.clk(clock),.reset(reset_req),.halt(halt),.rd(rd),.wr(wr),.addr(addr),.data(data), .opcode(opcode),.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr); ram t_ram(.addr(addr9:0),.read(rd),.write(wr),.ena(ram_sel),.data(data); rom t_rom(.addr(addr),.read(rd),.ena(rom_sel),.data(data); addr_decode t_addr_decode(.addr(addr),.ram_sel(ram_sel),.rom_sel(rom_sel); initial begin clock=1; $timeformat(-9,1,ns,12); display_debug_message; sys_reset; test1; $sto