數(shù)字邏輯設(shè)計(jì)復(fù)習(xí)：lesson 2

1、2016.06.08 UESTC數(shù)電加油站lesson-2一、組合電路重點(diǎn)知識(shí)回顧進(jìn)制轉(zhuǎn)換（10,2,8,16）補(bǔ)碼系統(tǒng)（概念、運(yùn)算）編碼（8421BCD,2421BCD,余3碼，格雷碼）關(guān)于函數(shù)的基本概念表達(dá)一個(gè)函數(shù)的方法，化簡(jiǎn)一個(gè)函數(shù)典型芯片的運(yùn)用（二進(jìn)制譯碼器、顯示譯碼器、數(shù)據(jù)選擇器、優(yōu)先編碼器、全加器、比較器、奇偶校驗(yàn)電路）競(jìng)爭(zhēng)冒險(xiǎn)卡諾圖：2、 Using Karnaugh maps, find a minimal sum-of-products expression for each of the following logic function F. Indicate the di

2、stinguished 1-cells in each map. F = WXYZ ( 0, 1, 2, 3, 4, 5, 7, 14, 15 )YZWX00000111100111100412151393715261410811YZWX0000011110011110卡諾圖應(yīng)用D1=? D0=? Z=?求D1的卡諾圖XQ1Q00001011110求D0的卡諾圖XQ1Q00001011110求Z的卡諾圖XQ1Q00001011110考試重點(diǎn)-時(shí)序部分-第7章1、鎖存器結(jié)構(gòu)與性能 2、D觸發(fā)器結(jié)構(gòu)性能及相關(guān)電路3、有限狀態(tài)機(jī)表達(dá)和分析計(jì)數(shù)器、序列信號(hào)發(fā)生器序列信號(hào)檢測(cè)器狀態(tài)分析、轉(zhuǎn)移列表設(shè)計(jì)、系

3、統(tǒng)分解設(shè)計(jì)4、同步狀態(tài)機(jī)的概念鎖存器與觸發(fā)器小結(jié)鎖存器和觸發(fā)器 電平有效和邊沿有效的區(qū)別按照邏輯功能的不同特點(diǎn)，通?？煞譃镾-R觸發(fā)器（鎖存器）D觸發(fā)器（鎖存器）J-K觸發(fā)器T觸發(fā)器每種觸發(fā)器的功能表特征方程狀態(tài)圖S-R Flip-Flops (Latches)SCRQQ時(shí)鐘S-R鎖存器0 00 11 01 1S R維持清 0置 10*Q功 能 表0 00 11 01 1S R維持清 0置 11*Q功 能 表1 11 00 10 0SL RL維持清 0置 11*Q0 1*0基本S-R鎖存器S QR Q（或非門）S QR Q（與非門）特征方程Q* = S+ RQSR=0（約束條件）J-K Fli

4、p-Flop0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1J K01001110QnQn+1狀態(tài)轉(zhuǎn)移真值表維持清0置1翻轉(zhuǎn)特征方程Q* = JQ + KQ0 00 11 01 1J K維持清 0置 1翻轉(zhuǎn)Q*功能表狀態(tài)圖D Flip-Flops (Latches) 特征方程：Q* = D01D=1D=0D=1D=0有使能端得D觸發(fā)器：Q* = END + ENQ D Q CLK QLogic SymbolA dynamic-input indicator T Flip-Flop 特征方程：Q* = QQQT有使能端的T觸發(fā)器： Q* = ENQ + ENQ E

5、N QT Q說(shuō)明： 傳統(tǒng)中文教材中認(rèn)為 T 觸發(fā)器的特征方程為： Q* = TQ + TQ 時(shí)序邏輯電路的幾個(gè)重要的方程、表和圖激勵(lì)方程 excitation equation輸出方程 output equation轉(zhuǎn)移方程 transition equation觸發(fā)器的特征方程狀態(tài)輸出表 state/output table轉(zhuǎn)移輸出表 transition /output table激勵(lì)輸出表excitation /output table狀態(tài)圖 state diagram時(shí)序圖 timing diagram邏輯功能 Logic function 下一 狀態(tài) 邏輯 F 狀態(tài) 存儲(chǔ)器時(shí)鐘 輸出

6、 邏輯 G 輸入輸出 時(shí)鐘信號(hào) 激勵(lì) 當(dāng)前狀態(tài) 下一 狀態(tài) 邏輯 F 狀態(tài) 存儲(chǔ)器 時(shí)鐘 輸出 邏輯 G 輸入 輸出 時(shí)鐘信號(hào)激勵(lì)當(dāng)前狀態(tài) 輸出流水線 存儲(chǔ)器時(shí)鐘Moore機(jī)：輸出只與狀態(tài)有關(guān)輸出Mealy機(jī)：輸出取決于狀態(tài)和輸入時(shí)鐘同步狀態(tài)機(jī)分析基本步驟：確定下一狀態(tài)函數(shù)F 和輸出函數(shù)G將F代入觸發(fā)器的特征方程得到下一狀態(tài)Q*利用Q*、G構(gòu)造狀態(tài)/輸出表畫出狀態(tài)圖、波形圖（可選）檢查電路是否可以自啟動(dòng)描述電路功能ENENQ0Q0Q1Q1ENMAXQ0Q1CLKD0D1當(dāng)前狀態(tài)激勵(lì)輸出輸入時(shí)鐘信號(hào)下一狀態(tài)邏輯 產(chǎn)生激勵(lì)信號(hào)狀態(tài)存儲(chǔ)器輸出邏輯EXAMPLE : a simple state ma

7、chine with two positive-edge triggered D flip-flops.ENENQ0Q0Q1Q1ENMAXQ0Q1CLKD0D1 1、excitation equation(由電路得到激勵(lì)方程) D0 = Q0EN + Q0EN D1 = Q1EN + Q1Q0EN + Q1Q0EN2、output equation(由電路得到輸出方程)MAX = Q1Q0EN 3、由激勵(lì)方程和觸發(fā)器特征方程得到 transition equation(轉(zhuǎn)移方程)（狀態(tài)方程） D觸發(fā)器特征方程：Q* = D Q0* = Q0EN + Q0EN Q1* = Q1EN + Q1Q0

8、EN + Q1Q0EN4、由轉(zhuǎn)移方程和輸出方程得到transition/output table001101100101101000000001Transition/output table狀態(tài)轉(zhuǎn)換表EN Q1 Q0 Q1* Q0* MAX0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Q0* = Q0EN + Q0ENQ1* = Q1EN + Q1Q0EN + Q1Q0ENMAX = Q1Q0ENS0 00 11 01 1EN0 100, 001, 010, 011, 001, 010, 011, 000, 1Q1*Q0*, MAXQ1Q05、State Di

9、agram (畫狀態(tài)圖)00EN=0MAX=001EN=1MAX=0EN=1MAX=1EN=0MAX=0EN=0MAX=0EN=0MAX=011EN=1MAX=010EN=1MAX=0邏輯功能描述：具有使能端EN的2位二進(jìn)制加法計(jì)數(shù)器電路輸出與輸入有關(guān) Mealy機(jī)S0 00 11 01 1EN0 100,001,010,011,001,010,011,000,1Q1*Q0*, MAXQ1Q0注意:狀態(tài)為00時(shí),輸入為EN=0,Some definitions(P552-553)a transition expression(轉(zhuǎn)移表達(dá)式) Each arc is labeled with a

10、transition expression; a transition is taken for input combinations for which the transition expression is 1. Transitions labeled “1” are always taken. Mutually exclusive (互斥的) No two transition expressions(轉(zhuǎn)移表達(dá)式) can equal 1 for the same input combination,since a machine cant have two next states f

11、or one input combination.all inclusive (完備的) For every possible input combination, some transition expression must equal 1, so that all next states are defined. 00EN=0MAX=001EN=1MAX=0EN=1MAX=1EN=0MAX=0EN=0MAX=0EN=0MAX=011EN=1MAX=010EN=1MAX=0 Analyze the clocked synchronous state machine shown in Fig

12、ure 5. (15)Write out the excitation equations, the state transition equations and the output equations of the circuit. (5)Fill out the transition/output table, and draw the state transition/output diagram, determine whether the circuit can start itself automatically. (8)Describe the logic function o

13、f the FSM.(2) 例題7.4 Clocked Synchronous State-Machine Design 同步狀態(tài)機(jī)的設(shè)計(jì)Construct a state/output table (狀態(tài)輸出表) corresponding to the word description.(Optional)Minimize the number of states.State assignment.（choose a set of state variables）Substitute the state-variable combination into a state/output ta

14、ble to create a transition/output tableChoose a flip-flop type for the state memory.Construct an excitation table ,get excitation equation and output equation.Draw a logic diagram.1、logic abstraction，get state table(diagram) 邏輯抽象，得到狀態(tài)圖（表）2、State AssignmentUse binary integer 000111 as the code of S0

15、S7 Count the clock signal, input can not be needed. Moore machineC-out signal is output variable.Design a 3 bits modulo-8 binary counterS0/0S1/0S3/0S4/0S2/0S5/0S7/1S6/00001111101010010100111003、construct transition/output table，get transition equation and output equation S0/0S1/0S3/0S4/0S2/0S5/0S7/1

16、S6/00 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1Q2 Q1 Q0Q2*Q1*Q0*CS0S1S2S3S4S5S6S70 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 00000000100011111010100101001110001Q1Q0Q2Q0* 00 01 11 101 0 0 11 0 0 13、construct transition/output table，get transition equation and output equationQ0* = Q00 0 00 0 10 1 00 1 11 0 01

17、 0 11 1 01 1 1Q2 Q1 Q0Q2*Q1*Q0*C0 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0000000010 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 000000001Q2 Q1 Q0Q2*Q1*Q0*C01Q1Q0Q2Q1* 00 01 11 100 1 0 10 1 0 1Q0* = Q0Q1* = Q1Q0 + Q1Q03、construct transition/output table，get transition e

18、quation and output equation0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 000000001Q2 Q1 Q0Q2*Q1*Q0*CQ0* = Q0Output equation：C = Q3 Q2 Q1Q1* = Q1Q0 + Q1Q001Q1Q0Q2Q2* 00 01 11 100 0 1 01 1 0 1Q2* = Q2Q1Q0 + Q2Q1 + Q2Q03、construct transition/output table，get transition

19、equation and output equationQ0* = Q0Q1* = Q1Q0 + Q1Q0Q2* = Q2Q1Q0 + Q2Q1 + Q2Q04、choose a flip-flop，get excitation equation 翻轉(zhuǎn)Q* = Q（T filp-flop）Q* = ENQ + ENQQ1* = Q1Q0 + Q1Q0= Q2Q1Q0 + Q2 (Q1+Q0)= Q2Q1Q0 + Q2 (Q1Q0)EN1 = Q0EN2 = Q1Q0EN0 = 1Choose T flip-flop with enable5、draw logic diagramEN0 = 1E

20、N1 = Q0EN2 = Q1Q0C = Q3 Q2 Q11CLKQ0Q1Q2CQ* = ENQ + ENQChoose T flip-flop with enableQ0* = Q0Q1* = Q1Q0 + Q1Q0Q2* = Q2Q1Q0 + Q2Q1 + Q2Q0例題.Transition/output table for a sequential circuit is shown in Table 2, X is input and Y is output, the sequential circuit is a modulus ( ？) up/down counter.例：A mod

21、e 5 counterstate diagramState assignmentbinary code Gray codeS0 0 0 0 0 0 0S1 0 0 1 0 0 1S2 0 1 0 0 1 1S3 0 1 1 0 1 0S4 1 0 0 1 1 0Q2 Q1 Q0 Q2 Q1 Q0Transition/output tablebinary codeGray code說(shuō)明： 最小冒險(xiǎn)法 所有未用狀態(tài) “安全”狀態(tài). 最小成本法 所有未用狀態(tài)的下一狀態(tài)作為無(wú)關(guān)項(xiàng) 電路的激勵(lì)方程簡(jiǎn)單，不夠安全.Unused state Minimal risk or minimal cost desi

22、gnMinimal riskMinimal costExcitation and output equationsMinimal risk design, choose D flip-flopExcitation/output tablevariable bus excitation register array outputLogic diagramExcitation and output equationsMinimal cost design, choose D flip-flopExcitation/output tableExcitation and output equation

23、sRisk checkExcitation/output tableMinimal cost designLogic diagram1、get transition diagramA represent input data；Z represent the result of detection。start，wait the first1 STASTA/0A1/0Get a 1 from A A1STA/0A11/0Get 11 A11OK/1A11/0Get 110 OKSTA/0A1/0Design a 110 sequence detectorState:SA0 1S*/ZIf 110

24、occurs successively，output is 1。Mealy machine1、get transition tableSTASTA/0A1/0A1STA/0A11/0A11OK/1A11/0OKSTA/0A1/0狀態(tài)SA0 1S*/Z2、state minimizationIdentify equivalent states.If two states1:produce the same values 2:for each input combination,have the sameNext stateSTA/1S*/ZSTA/0STAA1/03、state assignment000110000111狀態(tài)說(shuō)明狀態(tài)編碼0Q1Q00001111001A01000ddZ00/0Q1Q00001111001A00/000/101/010/010/0dd/ddd/d4、get state equation and output equatio