紀(jì)祿平計(jì)算機(jī)組成原理PPT第版CPU子系統(tǒng)MIPS多周期數(shù)據(jù)通路

1、3.5.4 多周期MIPS處理器（數(shù)據(jù)通路）1指令周期 時(shí)鐘周期 時(shí)鐘周期 指令周期 多個(gè)機(jī)器(工作)周期 1、單周期CPU 2、多周期CPU CPU的指令周期對(duì)比 CPI = 1CPI 12多周期處理器的特點(diǎn)指令的執(zhí)行需多個(gè)時(shí)鐘周期不同的指令所需的時(shí)鐘周期數(shù)不同時(shí)鐘周期比單周期處理器短復(fù)用主要部件，以簡(jiǎn)化數(shù)據(jù)通路單個(gè)ALU用于所有計(jì)算單個(gè)存儲(chǔ)器用于指令和數(shù)據(jù)的存儲(chǔ)需要增加寄存器暫存數(shù)據(jù)用于跨時(shí)鐘周期是流水線(xiàn)等高級(jí)技術(shù)的基礎(chǔ)，主流模式控制器更復(fù)雜，組合邏輯/微程序方式控制信號(hào)不僅與指令有關(guān)，還與當(dāng)前時(shí)序狀態(tài)有關(guān)3與單周期CPU相比，數(shù)據(jù)通路的結(jié)構(gòu)特點(diǎn)：各指令共享ALU增設(shè)若干暫存器指令存儲(chǔ)與數(shù)

2、據(jù)存儲(chǔ)合并1個(gè)存儲(chǔ)器(存儲(chǔ)指令+數(shù)據(jù))，1個(gè)通用運(yùn)算器；多個(gè)暫存器；4多周期處理器的設(shè)計(jì)思路指令執(zhí)行過(guò)程按存儲(chǔ)單元級(jí)的信息傳送，細(xì)分為多步，每步安排1個(gè)時(shí)鐘周期:共享硬件以簡(jiǎn)化數(shù)據(jù)通路（1+1+多）取指令；指令譯碼后從寄存器取數(shù)、計(jì)算轉(zhuǎn)移地址；執(zhí)行：運(yùn)算、存儲(chǔ)器地址計(jì)算，或分支判斷；存儲(chǔ)器讀/寫(xiě)；寄存器堆寫(xiě)回；1個(gè)存儲(chǔ)器(指令+數(shù)據(jù))；1個(gè)通用運(yùn)算器；多個(gè)暫存器；從R型指令數(shù)據(jù)通路開(kāi)始，逐步擴(kuò)展，最后再合并。5PCIRMDRABALUF1、 數(shù)據(jù)通路設(shè)計(jì)（表3-26，11條指令）PCWriteAddr RDWDMemReadMemWrite存儲(chǔ)器operationzeroIRWrite(1)

3、R型運(yùn)算指令add rd,rs,rt# $rd$rs+$rt+4PCRN1RN2WNRD1RD2RegWriteWD寄堆(1) IRMemPC, PC PC+4(2) ARegrs, BRegrt(3) FA op B(4) RegrdFIRABFrsrtrd按信息傳送過(guò)程劃分：6(2) 擴(kuò)展I型訪(fǎng)存指令lw rt, offset(rs)# $rtMem$rs+E(offset)(1) IRMemPC, PC PC+4(2) ARegrs(3) FA+E(offset)(4) MDRMemF+4PCIRMDRABALUFPCWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1

4、RN2WNRD1RD2RegWriteWD寄堆operationzeroIRWritePCAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆E(5) RegrtMDRIRMDRAFrsrtrdimm已涵蓋了I型運(yùn)算指令！比如:addi rt, rs, imm7sw rt, offset(rs)# Mem$rs+E(offset) $rt(1) IRMemPC, PCPC+4(2) ARegrs, BRegrt (3) FA+E(offset)+4PCALUFPCWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2W

5、NRD1RD2RegWriteWD寄堆operationzeroIRWritePCAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆E(4) MemFBMDRIRABABIRFrsrtrdimm8beq rs, rt, offset#PC (PC+4)+(E(offset)2), if $rs=$rt+4PCALUFPCWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆operationzeroIRWritePCAddr RDWDMemReadMemWrite存儲(chǔ)器RN1R

6、N2WNRD1RD2RegWriteWD寄堆EMDRIRAB(1) IRMemPC; PCPC+4, (2) ARegrs, BRegrt; FPC+E(offset)2 (3) PCF, if zero=1; NOP(不修改PC), if zero=0 ABFIR(2) 擴(kuò)展I型分支指令rsrtrdimm29j address#PC(PC+4)31:28U(address2)+4PCALUFPCWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆operationzeroIRWritePCAddr RDWDMemReadMemW

7、rite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆EMDRIRAB(1) IRMemPC; PCPC+4, (2) PCPC31:28U(address2) 2(3) 擴(kuò)展J型j address指令2Ursrtrdaddress, 26 imm11條目標(biāo)指令的數(shù)據(jù)通路設(shè)計(jì)已完成！IR4 10未整合的數(shù)據(jù)通路PC的來(lái)源：ALU_A的來(lái)源：ALU_B的來(lái)源：寄堆WD的來(lái)源：WN的來(lái)源：Addr來(lái)源：符號(hào)擴(kuò)展器：0擴(kuò)展(andi等), 符號(hào)擴(kuò)展(addi等) rt+4PCALUFPCWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWr

8、iteWD寄堆operationzeroIRWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆EMDRIRAB22Ursrdaddressimm4PC+4(ALU),分支地址(F)，轉(zhuǎn)移地址(U)MDR, F;rt, rd;PC, F；PC, A;4, B, E(offset), E(offset)211+4PCALUPCWriteRN1RN2WNRD1RD2RegWriteWD寄堆operationzeroIRWriteAddr RDWDMemReadMemWrite存儲(chǔ)器RN1RN2WNRD1RD2RegWriteWD寄堆EMDRAB22UIRF