數(shù)字邏輯設(shè)計(jì)及應(yīng)用17課件

1、Chapter 7 Sequential Logic Design Principles( 時(shí)序邏輯設(shè)計(jì)原理 ) Latches and Flip-Flops (鎖存器和觸發(fā)器 ) Clocked Synchronous State-Machine Analysis (同步時(shí)序分析) Clocked Synchronous State-Machine Design (同步時(shí)序設(shè)計(jì))Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)1Chapter 7 Sequential Logic DesIntroductionCombinational cir

2、cuitOutputs depend solely on the present combination of the circuit inputs valuesDigitalSystemb=0F=0DigitalSystemif b=0, then F=0if b=1, then F=1b=1F=1(a)DigitalSystemb=0F=0DigitalSystemb=1F=1DigitalSystemb=0F=1Cannot determine value ofF solely from presentinput value(b) Vs. sequential circuit: Has

3、“memory” that impacts outputs too2IntroductionCombinational circBasic Concepts (基本概念)Logic Circuits are Classified into Two Types (邏輯電路分為兩大類)：Combinational Logic Circuit （組合邏輯電路）Sequential Logic Circuit （時(shí)序邏輯電路）Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)3Basic Concepts (基本概念)Logic CirBasic Conc

4、epts (基本概念)Combinational Logic Circuit （組合邏輯電路）Outputs Depend Only on its Current Inputs.(任何時(shí)刻的輸出僅取決與當(dāng)時(shí)的輸入)Character of Circuit: No Feedback Circuit, No Memory Device(電路特點(diǎn)：無反饋回路、無記憶元件)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)4Basic Concepts (基本概念)CombinatiBasic Concepts (基本概念)Sequential Logic

5、 Circuit （時(shí)序邏輯電路）Outputs Depend Not Only on its Current Inputs, But also on the Past Sequence of Inputs.(任一時(shí)刻的輸出不僅取決與當(dāng)時(shí)的輸入，還取決于過去的輸入序列)Character of Circuit: Have Feedback Circuit, Have Memory Device(電路特點(diǎn)：有反饋回路、有記憶元件)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)5Basic Concepts (基本概念)SequentiaBasic

6、 Concepts (基本概念)Sequential Logic Circuit （時(shí)序邏輯電路）Finite-State Machine: Have Finite States.(有限狀態(tài)機(jī)：有有限個(gè)狀態(tài)。）A Clock Signal is Active High if state changes occur at the clock Rising Edge or when the clock is High, and Active Low in the complementary case.(時(shí)鐘信號(hào)高電平有效是指在時(shí)鐘信號(hào)的上升沿或時(shí)鐘的高電平期間發(fā)生變化。） Digital Logi

7、c Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)6Basic Concepts (基本概念)SequentiaBasic Concepts (基本概念)Sequential Logic Circuit （時(shí)序邏輯電路）Clock Period: The Time between Successive transitions in the same direction.(時(shí)鐘周期：兩次連續(xù)同向轉(zhuǎn)換之間的時(shí)間。）Clock Frequency: The Reciprocal of the Clock Period(時(shí)鐘頻率：時(shí)鐘周期的倒數(shù)。） Digital Logic D

8、esign and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)Figure 7-17Basic Concepts (基本概念)SequentiaBasic Concepts (基本概念)Sequential Logic Circuit （時(shí)序邏輯電路）Clock Tick: The First Edge of Pulse in a clock period or sometimes the period itself.(時(shí)鐘觸發(fā)沿：時(shí)鐘周期內(nèi)的第一個(gè)脈沖邊沿，或時(shí)鐘本身。）Duty Cycle: The Percentage of time that the clock signal is

9、 at its asserted level. (占空比：時(shí)鐘信號(hào)有效時(shí)間與時(shí)鐘周期的百分比。） Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)Figure 7-18Basic Concepts (基本概念)Sequentia思考：能否只用一片1位全加器進(jìn)行串行加法？C1S0X0 Y0C0X YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn Yn串行加法器C1C2X YCI COSC2S1X1 Y1C1反饋利用反饋和時(shí)鐘控制C3S2X2 Y2C2Digital Logic Design and Appl

10、ication (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)9思考：能否只用一片1位C1S0X0 Y0C0X 暫存X YCI COSCi+1SiXi YiCiX YCI COSX YCI COSX YCI COSC0S0S1SnX0 Y0X1 Y1Xn Yn串行加法器C1C1時(shí)鐘控制需要具有記憶功能的邏輯單元，能夠暫存運(yùn)算結(jié)果。利用反饋和時(shí)鐘控制Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)10暫存X YCi+1SiXi YiCiX 7.1 Bistable Elements (雙穩(wěn)態(tài)元件)QQ_L1100QQ_LIt has Two Stable State: Q

11、 = 1 ( HIGH ) and Q = 0 ( LOW ) (電路有兩種穩(wěn)定狀態(tài)：Q = 1 ( 1態(tài) ) 和 Q = 0 ( 0態(tài) ) Bistable Circuit（雙穩(wěn)電路）0011Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)117.1 Bistable Elements (雙穩(wěn)態(tài)元件)7.1 Bistable Elements (雙穩(wěn)態(tài)元件)QQ_L1100QQ_LWhen Power is first Applied to the circuit, it Randomly Comes up in One State or th

12、e Other and Stays there Forever. ( 只要一接電源，電路就隨機(jī)出現(xiàn)兩種狀態(tài)中的一種，并永久地保持這一狀態(tài)。)0011Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)127.1 Bistable Elements (雙穩(wěn)態(tài)元件)Vin1Vout1Vin2Vout2Vout2Vin2= Vin2= Vout2穩(wěn)態(tài) stable亞穩(wěn)態(tài) metastableQQ_LVin1 Vout1Vin2 Vout2Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)13Vin1Vout1V

13、in2Vout2Vout2Vin2= VMetastable Behavior(亞穩(wěn)態(tài)特性)Random Noise will tend to Drive a circuit that is Operating at the Metastable Point toward one of the Stable operating point.( 隨機(jī)噪聲會(huì)驅(qū)動(dòng)工作于亞穩(wěn)態(tài)點(diǎn)的電路轉(zhuǎn)移到一個(gè)穩(wěn)態(tài)的工作點(diǎn)上去 )QQ_LDigital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)14Metastable Behavior(亞穩(wěn)態(tài)特性)Ran所有的時(shí)序電路對(duì)亞穩(wěn)態(tài)都

14、是敏感的Metastable Behavior(亞穩(wěn)態(tài)特性)穩(wěn)態(tài)穩(wěn)態(tài)亞穩(wěn)態(tài)Apply a definite Pulse Width from a Stable state to the Other.(從一個(gè)“穩(wěn)態(tài)”轉(zhuǎn)換到另一個(gè)“穩(wěn)態(tài)”需加一定寬度的脈沖（足夠的驅(qū)動(dòng)）)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)15所有的時(shí)序電路對(duì)亞穩(wěn)態(tài)都是敏感的Metastable Beh7.2 Latches and Flip-Flops(鎖存器與觸發(fā)器) The Basic Building Blocks of most Sequential Circu

15、its.(大多數(shù)時(shí)序電路的基本構(gòu)件)Latches（鎖存器）根據(jù)輸入，直接改變其輸出（無使能端）有使能端時(shí)，在使能信號(hào)的有效電平之內(nèi)都可根據(jù)輸入直接改變其輸出狀態(tài)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)167.2 Latches and Flip-Flops(鎖7.2 Latches and Flip-Flops(鎖存器與觸發(fā)器) The Basic Building Blocks of most Sequential Circuits.(大多數(shù)時(shí)序電路的基本構(gòu)件)Flip-Flops（ F/F,觸發(fā)器）只在時(shí)鐘信號(hào)的有效邊沿改變其輸出狀

16、態(tài)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)177.2 Latches and Flip-Flops(鎖S-R Latch (S-R鎖存器)S-R Latch with Enable (具有使能端的S-R鎖存器)D Latch (D鎖存器)Edge-Triggered D Flip-Flops (邊沿觸發(fā)式D觸發(fā)器)Edge-Triggered D Flip-Flops with Enable (具有使能端的邊沿觸發(fā)式D觸發(fā)器)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)7.2 Latch

17、es and Flip-Flops(鎖存器與觸發(fā)器)18S-R Latch (S-R鎖存器)Digital LogiScan Flip-Flops (掃描觸發(fā)器)Master/Slave Flip-Flops (S-R、J-K） (主從式觸發(fā)器)Edge-Triggered J-K Flip-Flops (邊沿觸發(fā)式J-K觸發(fā)器)T Flip-Flop (T觸發(fā)器)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)7.2 Latches and Flip-Flops(鎖存器與觸發(fā)器)19Scan Flip-Flops Digital Logic S

18、-R Latches (S-R鎖存器)QQLRS（1）S = R = 0電路維持原態(tài)工作原理：00QQL或非門 非門 Qn+1 = Qn QLn+1 = QLn新態(tài)原態(tài)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)20S-R Latches (S-R鎖存器)QQLRS（1）S QQLRS工作原理：10（2）S = 0, R = 1a. 原態(tài)：Qn=0，QLn=101新態(tài)：Qn+1=0，QLn+1=1b. 原態(tài)：Qn=1，QLn=0新態(tài)：Qn+1=0，QLn+1=1鎖存器清0：Qn+1=0 QLn+1=1即使S,R無效（=0）鎖存器仍能鎖定0態(tài)R

19、eset10(a)QQLRS1001(b)00101Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)S-R Latches (S-R鎖存器)21QQLRS工作原理：10（2）S = 0, R = 1a. QQLRS工作原理：01（3）S = 1, R = 0a. 原態(tài)：Qn=1，QLn=010新態(tài)：Qn+1=1，QLn+1=0b. 原態(tài)：Qn=0，QLn=1新態(tài)：Qn+1=1，QLn+1=0鎖存器置1：Qn+1=1 QLn+1=0即使S,R無效（=0）鎖存器仍能鎖定1態(tài)Set01(a)QQLRS0110(b)00110Digital Logic

20、Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)S-R Latches (S-R鎖存器)22QQLRS工作原理：01（3）S = 1, R = 0a. QQLRS工作原理：（3）S = R = 100Qn+1 = QLn+1 = 0當(dāng)S,R無效（=0）時(shí)，11QQN00亞穩(wěn)態(tài)，對(duì)噪聲敏感狀態(tài)不確定“禁止”Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)S-R Latches (S-R鎖存器)23QQLRS工作原理：（3）S = R = 100Qn+1 =S QR QL(邏輯符號(hào))S QR Q(邏輯符號(hào))QQLRSResetSe

21、t(清0)(置1)0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1S R0100110*0*QnQn+1狀態(tài)轉(zhuǎn)移真值表0 00 11 01 1S R維持原態(tài)0 11 0 0* 0*Q QL(功 能 表)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)S-R Latches (S-R鎖存器)Logic SymbolFunction Table24S Q(邏輯符號(hào))S Q(邏輯符號(hào))狀態(tài)圖00011101 00 01 11 10QnSRQn+1Qn+1 = S + RQnSR = 0特征方程約束條件01S=1,R=0S=0,R=1S=XR=0S=0R=X0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1S R0100110*0*QnQn+1狀態(tài)轉(zhuǎn)移真值表Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)25狀態(tài)圖000111