文本教案數(shù)電exam

1、Sum of Digital Logic and Systems1Chapter 1Fundamentals of Digital LogicNumber systemsdecimal (r=10)binary (r=2)octal (r=8)Base Conversionshexadecimal (r=16)IntegerFraction10進(jìn)制28163.Signed Binary Numbers8421BCDconversionsSign-magnitude system 1s complement system 2s complement system Shift code syste

2、mPositive number Negative numberChapter 2Logic Gates2AND， OR, NAND，NOR, XOR， XNOR,NOTAND-OR,AND-OR- NOTOC、TSL(wire-AND線與),TGSymbol ， Expression,Function,1. Logic Gate2. TTL GateVT = 1.4VRT = 2k閾值電壓閾值電阻3. MOS Gate看 懂Chapter 3Logic Algebra3各種方法化簡(jiǎn)邏輯函數(shù) （公式法、Kmap、VEM、隨意項(xiàng)）Chapter 4Combinational Logic Circ

3、uitCombinational Circuit AnalysisCombinational Circuit DesignDecoderActive-high,Active-low,74138符號(hào),功能,實(shí)現(xiàn)函數(shù)74151, 74153，符號(hào),功能,實(shí)現(xiàn)函數(shù)Half Adder,Full Adder,Carry look-ahead符號(hào)， 功能，輸出表達(dá)式符號(hào)，功能，輸出，級(jí)聯(lián)4. MUX5. Adder6. ComparatorChapter 54Flip-Flop1. Waveforms :positive edge negative edgeRS JK-FF,D-FF,T-FF符號(hào)， 真

4、值表， 特征方程， 功能， 波形Chapter6SequentialLogic Circuits5Sequential Circuit AnalysisSequential Circuit Design計(jì)數(shù)器，串行信號(hào)檢測(cè)電路IC Counter74161, 74163,74160,74290IC Register74194,環(huán)形計(jì)數(shù)器，扭環(huán)計(jì)數(shù)器計(jì)數(shù)器：連接電路，狀態(tài)圖，判斷電路計(jì)數(shù)模值6Chapter 7Pulse Circuits555 TimerSchmitt Trigger功能，Vco555 Timer3.One-Shots555 TimerTW = 1.1RCV = VT+ - V

5、T-VittVo(Q)TW74121 TW = 0.7RC觸發(fā)方式A1 A2 B=1;A1A2=0 4.Astable Multivibrators555 Timer占空比可調(diào)： TH, TL, T, f, q占空比不可調(diào)：TH, TL,T, f, qHLSchmitt-FFT, T , T, f, qViCVOD2D1R2R1Chapter 8Design of Digital Systems7ASMControllerData Processor每態(tài)一個(gè)觸發(fā)器，MUX-decoder-D-FFChapter9Digital Analog Conversions1. DACBinary We

6、ightedR-2RLadderDACVO ,FSR,Resolution= VOmin ,AD7533偏移碼，補(bǔ)碼VOmin ,VO max2. ADC1）Flash ADCRounding-off Flash ADC112ns 2 n81sNo-carry Method2）Parallel/Serial ADC兩步 3） Successive Approximation ADC 4）Dual-Slop ADC采樣點(diǎn)Chapter 109Memory and Programmable Logic DeviceRAM:technical parameterexpansion address rangeChapter 11VHDLRM:Q &