數(shù)字系統(tǒng)設(shè)計(jì)：第三章 組合邏輯電路行為級(jí)描述

第三章組合邏輯電路行為級(jí)描述34/szxt/知識(shí)儲(chǔ)備階段：熟悉軟件，開(kāi)發(fā)板設(shè)計(jì)性實(shí)驗(yàn)：數(shù)字頻率計(jì)的設(shè)計(jì)PCM基群幀同步檢測(cè)電路設(shè)計(jì)與實(shí)現(xiàn)簡(jiǎn)單綜合設(shè)計(jì)：多功能秒表設(shè)計(jì)

（可自主選題）復(fù)雜設(shè)計(jì)階段：基于AltiumSOPC平臺(tái)的復(fù)雜設(shè)計(jì)（此部分為可選）本章目錄概述數(shù)據(jù)流描述行為級(jí)描述基本邏輯門(mén)電路的設(shè)計(jì)組合邏輯電路——概述數(shù)字電路按其完成邏輯功能的不同特點(diǎn)，劃分為組合邏輯電路和時(shí)序邏輯電路兩大類(lèi)。組合邏輯電路在邏輯功能上的特點(diǎn)是任意時(shí)刻的輸出僅僅取決于該時(shí)刻的輸入，與電路原來(lái)的狀態(tài)無(wú)關(guān)而時(shí)序邏輯電路在邏輯功能上的特點(diǎn)是任意時(shí)刻的輸出不僅取決于當(dāng)時(shí)的輸入信號(hào)，而且還取決于電路原來(lái)的狀態(tài)，或者說(shuō)，還與以前的輸入有關(guān)。組合邏輯電路——概述3-8譯碼器如右圖的3-8譯碼器，Y1到Y(jié)8的輸出值只與A1、A2、A3和片選信號(hào)S1、S2、S3的當(dāng)前輸入值有關(guān)，而與A1、A2、A3、S1、S2和S3以前任一時(shí)刻的任意輸入狀態(tài)無(wú)關(guān)，因此是一個(gè)典型的組合邏輯電路，而并非時(shí)序邏輯電路組合邏輯電路——概述從邏輯上講，組合電路在任一時(shí)刻的輸出狀態(tài)僅由該時(shí)刻的信號(hào)決定，而與電路原來(lái)的狀態(tài)無(wú)關(guān)。組合邏輯電路：——電路無(wú)記憶功能從結(jié)構(gòu)上講，組合電路都是單純由邏輯門(mén)組成，且輸出不存在反饋路徑。（不含存儲(chǔ)單元）組合邏輯電路框圖常用的組合邏輯電路：簡(jiǎn)單門(mén)電路、選擇器、譯碼器、三態(tài)門(mén)等組合邏輯電路——概述傳統(tǒng)的設(shè)計(jì)方法：采用標(biāo)準(zhǔn)組件進(jìn)行設(shè)計(jì)（1）邏輯問(wèn)題的描述。將設(shè)計(jì)問(wèn)題轉(zhuǎn)化為一個(gè)邏輯問(wèn)題（2）邏輯函數(shù)簡(jiǎn)化。將第一步的函數(shù)化簡(jiǎn)，求得描述設(shè)計(jì)

問(wèn)題的最簡(jiǎn)表達(dá)式（3）邏輯函數(shù)轉(zhuǎn)換。根據(jù)使用的門(mén)電路類(lèi)型，將表達(dá)式變

換為所需形式（4）畫(huà)邏輯圖，并考慮實(shí)際工程問(wèn)題。組合邏輯電路的設(shè)計(jì)方法：組合邏輯電路——概述使用可編程邏輯器件，用硬件語(yǔ)言描述的EDA設(shè)計(jì)方法（1）邏輯問(wèn)題的描述。將設(shè)計(jì)問(wèn)題轉(zhuǎn)化為一個(gè)邏輯問(wèn)題（2）根據(jù)邏輯問(wèn)題，用硬件描述語(yǔ)言進(jìn)行描述（3）對(duì)描述進(jìn)行綜合，仿真測(cè)試（4）生成最終網(wǎng)表，下載到芯片組合邏輯電路的設(shè)計(jì)方法：組合邏輯電路——概述傳統(tǒng)的設(shè)計(jì)方法EDA設(shè)計(jì)方法設(shè)計(jì)方式人工為主電腦輔助為主設(shè)計(jì)過(guò)程復(fù)雜簡(jiǎn)單可讀性低高移植性低高錯(cuò)誤修正麻煩容易正確性檢驗(yàn)麻煩容易兩種設(shè)計(jì)方法的比較：ECE448–FPGAandASICDesignwithVHDL數(shù)據(jù)流描述VHDL設(shè)計(jì)風(fēng)格（DesignStyles）組件和互連結(jié)構(gòu)VHDL設(shè)計(jì)風(fēng)格數(shù)據(jù)流并行語(yǔ)句行為

(時(shí)序)

寄存器

狀態(tài)機(jī)指令解碼順序語(yǔ)句適合綜合的子集Testbenches可綜合的VHDLVHDL數(shù)據(jù)流設(shè)計(jì)風(fēng)格可綜合VHDL代碼可綜合VHDL代碼VHDL數(shù)據(jù)流設(shè)計(jì)風(fēng)格寄存器傳輸級(jí)(RTL)設(shè)計(jì)描述

組合邏輯

組合邏輯寄存器…本節(jié)主題數(shù)據(jù)流VHDL

并行信號(hào)賦值

()

條件并行信號(hào)賦值(when-else)

選擇并行信號(hào)賦值(with-select-when)

generate使用

(for-generate)并行語(yǔ)句數(shù)據(jù)流VHDL并行信號(hào)賦值()條件并行信號(hào)賦值(when-else)選擇并行信號(hào)賦值(with-select-when)generate(for-generate)主要語(yǔ)句并行語(yǔ)句數(shù)據(jù)流VHDL:例子xycinscout數(shù)據(jù)流VHDL:例子(1)LIBRARYieee;USEieee.std_logic_1164.all;ENTITYfulladdIS PORT(

x:IN STD_LOGIC;

y

:IN STD_LOGIC;cin :IN STD_LOGIC; s:OUT STD_LOGIC;

cout :OUT STD_LOGIC);ENDfulladd;數(shù)據(jù)流VHDL:例子(2)ARCHITECTUREdataflowOFfulladdISBEGIN s<=xXORyXORcin;

cout<=(xANDy)OR(cinANDx)OR(cinANDy);ENDdataflow;邏輯操作邏輯操作邏輯操作優(yōu)先級(jí)andornandnorxornotxnornotandornandnorxorxnorHighestLowest僅在VHDL-93或以后

需要實(shí)現(xiàn):y=ab+cd不正確y<=aandborcandd;

等價(jià)于y<=((aandb)orc)andd;等價(jià)于y=(ab+c)d正確y<=(aandb)or(candd);沒(méi)有隱含的優(yōu)先級(jí)21E.g.,status<='1';even<=(p1andp2)or(p3andp4);arith_out<=a+b+c-1;最后一個(gè)語(yǔ)句的實(shí)現(xiàn)22帶有一個(gè)反饋回路的

信號(hào)賦值語(yǔ)句一個(gè)信號(hào)同時(shí)出現(xiàn)在并行賦值語(yǔ)句的兩邊E.g.,

q<=((notq)and(noten))or(danden);語(yǔ)法上錯(cuò)誤構(gòu)成了一個(gè)閉合的反饋回路必須避免數(shù)據(jù)流VHDL并行信號(hào)賦值()條件并行信號(hào)賦值(when-else)選擇并行信號(hào)賦值(with-select-when)generate(for-generate)主要語(yǔ)句并行語(yǔ)句條件并行信號(hào)賦值target_signal<=value1

when

condition1

else

value2

when

condition2

else...

valueN-1

when

conditionN-1

else

valueN;When-Else通常實(shí)現(xiàn)的電路結(jié)構(gòu)target_signal<=value1

when

condition1

else

value2

when

condition2

else...

valueN-1

when

conditionN-1

else

valueN;When-Else.…ValueNValueN-1ConditionN-1Condition2Condition1Value2Value1TargetSignal…010101262-to-1muxSel是布爾數(shù)據(jù)類(lèi)型如果sel為真,從“T”端口的輸入連接到輸出端口.如果sel為假，從“F”端口的輸入連接到輸出端口.27282930E.g.,31E.g.,3233E.g.,操作關(guān)系操作邏輯和關(guān)系操作優(yōu)先順序=/=<<=>>=not=/=<<=>>=andornandnorxorxnorHighestLowest

比較a=bc不正確…whena=bandcelse…等價(jià)于…when(a=b)andcelse…正確…whena=(bandc)else…優(yōu)先邏輯和關(guān)系操作

VHDL操作數(shù)據(jù)流VHDL并行信號(hào)賦值()條件并行信號(hào)賦值(when-else)選擇并行信號(hào)賦值(with-select-when)generate(for-generate)主要語(yǔ)句并行語(yǔ)句選擇并行信號(hào)賦值with

choice_expression

select

target_signal<=expression1

when

choices_1,

expression2

when

choices_2,...

expressionN

when

choices_N;With–Select-When通常實(shí)現(xiàn)的電路結(jié)構(gòu)with

choice_expression

select

target_signal<=expression1

when

choices_1,

expression2

when

choices_2,...

expressionN

when

choices_N;With–Select-Whenchoices_1choices_2choices_Nexpression1target_signalchoiceexpressionexpression2expressionN選擇_k的允許格式WHENvalueWHENvalue_1|value_2|....|valueNWHENOTHERS選擇_k的允許格式-例子

WITHselSELECT y<=aWHEN"000",cWHEN"001"|"111",dWHENOTHERS;42句法簡(jiǎn)化語(yǔ)法:withselect_expressionselectsignal_name<=value_expr_1whenchoice_1,value_expr_2whenchoice_2,value_expr_3whenchoice_3,...value_expr_nwhenchoice_n;43select_expression離散型或1-D陣列有限的可能值choice_i一個(gè)值Choices必須互不相關(guān)最后的選擇項(xiàng)可以使用others

44E.g.,4-to-1mux45能用“11”取代others?46E.g.,2-to-22

二進(jìn)制譯碼器47E.g.,4-to-2優(yōu)先編碼器48能使用‘-’嗎?49E.g.,簡(jiǎn)單ALU50E.g.,真值表51概念實(shí)現(xiàn)multiplexing電路實(shí)現(xiàn)(k+1)-to-152select_expression包含5values:c0,c1,c2,c3,c45354E.g.,553.條件信號(hào)賦值vs.選擇信號(hào)賦值條件和選擇信號(hào)賦值語(yǔ)句的轉(zhuǎn)換比較56從

選擇

賦值到條件賦值57從條件賦值到選擇賦值

58比較選擇信號(hào)賦值:適合功能表描述的電路E.g.,二進(jìn)制解碼器,multiplexer針對(duì)具有輸入優(yōu)先及的電路，效率較低59條件信號(hào)賦值:更適合具有優(yōu)先級(jí)的條件或操作的電路E.g.,優(yōu)先編碼器能處理復(fù)雜的條件.e.g.,MLUExampleMLUBlock原理圖BANEG_ANEG_BIN0IN1IN2IN3OUTPUTSEL1SEL0MUX_4_1L0L1NEG_YYY1A1B1MUX_0MUX_1MUX_2MUX_3010101MLU:Entity申明LIBRARYieee;USEieee.std_logic_1164.all;ENTITYmluIS PORT( NEG_A:INSTD_LOGIC; NEG_B:INSTD_LOGIC; NEG_Y:INSTD_LOGIC; A:INSTD_LOGIC; B:INSTD_LOGIC; L1:INSTD_LOGIC; L0:INSTD_LOGIC; Y:OUTSTD_LOGIC );ENDmlu;MLU:Architecture定義ARCHITECTUREmlu_dataflowOFmluIS

SIGNALA1:STD_LOGIC;SIGNALB1:STD_LOGIC;SIGNALY1:STD_LOGIC;SIGNALMUX_0:STD_LOGIC;SIGNALMUX_1:STD_LOGIC;SIGNALMUX_2:STD_LOGIC;SIGNALMUX_3:STD_LOGIC;SIGNALL:

STD_LOGIC_VECTOR(1DOWNTO0);MLU-Architecture主體BEGIN A1<=

NOTAWHEN(NEG_A='1')ELSE A; B1<=

NOTBWHEN(NEG_B='1')ELSE B; Y

<=

NOTY1WHEN(NEG_Y='1')ELSE Y1;

MUX_0

<=

A1ANDB1; MUX_1

<=

A1ORB1; MUX_2

<=

A1XORB1; MUX_3

<=

A1XNORB1;L<=L1&L0;

with(L)select

Y1

<=

MUX_0WHEN"00",

MUX_1WHEN"01",

MUX_2WHEN"10",

MUX_3WHENOTHERS;

ENDmlu_dataflow;ECE448–FPGAandASICDesignwithVHDL采用DataflowVHDL

描述常用的組合邏輯ECE448–FPGAandASICDesignwithVHDL線(xiàn)和總線(xiàn)信號(hào)SIGNAL

a:STD_LOGIC;

SIGNAL

b:STD_LOGIC_VECTOR(7DOWNTO0);wireabusb18拼接線(xiàn)和總線(xiàn)SIGNAL

a:STD_LOGIC_VECTOR(3DOWNTO0);SIGNAL

b:STD_LOGIC_VECTOR(4DOWNTO0);SIGNAL

c:STD_LOGIC;SIGNALd:STD_LOGIC_VECTOR(9DOWNTO0);d<=a&b&c;4510abcd分割總線(xiàn)SIGNAL

a:STD_LOGIC_VECTOR(3DOWNTO0);SIGNAL

b:STD_LOGIC_VECTOR(4DOWNTO0);SIGNAL

c:STD_LOGIC;SIGNALd:STD_LOGIC_VECTOR(9DOWNTO0);a<=d(9downto6);b<=d(5downto1);c<=d(0);4510abcdECE448–FPGAandASICDesignwithVHDL固定的移位和旋轉(zhuǎn)固定移位VHDL操作A(3)A(2)A(1)A(0)‘0’A(3)A(2)A(1)A>>1SIGNALA:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALAshiftR:STD_LOGIC_VECTOR(3DOWNTO0);AshiftR<=AshiftRA固定的旋轉(zhuǎn)操作A(3)A(2)A(1)A(0)A(2)A(1)A(0)A(3)A<<<1SIGNALA:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALArotL:STD_LOGIC_VECTOR(3DOWNTO0);ArotL<=ArotLAECE448–FPGAandASICDesignwithVHDLBuffers(b)Equivalentcircuit(c)Truthtablexfe(a)Atri-statebuffer00110101ZZ01fexxfe=0e=1xfTri-stateBufferTri-stateBuffer–example(1)LIBRARYieee;USEieee.std_logic_1164.all;ENTITYtri_stateISPORT(ena:INSTD_LOGIC; input:INSTD_LOGIC;output:OUTSTD_LOGIC);ENDtri_state;Tri-stateBuffer–example(2)ARCHITECTUREdataflowOFtri_stateISBEGINoutput<=inputWHEN(ena=‘1’)ELSE‘Z’;ENDdataflow;ECE448–FPGAandASICDesignwithVHDLMultiplexers2-to-1Multiplexer(a)Graphicalsymbol(b)Truthtable01fsw0w1fsw0w1012-to-1MultiplexerVHDL代碼LIBRARYieee;USEieee.std_logic_1164.all;ENTITYmux2to1IS PORT( w0,w1,s :IN STD_LOGIC; f :OUT STD_LOGIC);ENDmux2to1;ARCHITECTUREdataflowOFmux2to1IS BEGIN f<=w0WHENs='0'ELSEw1;ENDdataflow;兩個(gè)multiplexers的串聯(lián)s1w3w101s2w201y兩個(gè)multiplexers串聯(lián)

VHDL代碼

LIBRARYieee;USEieee.std_logic_1164.all;ENTITYmux_cascadeIS PORT( w1,w2,w3:INSTD_LOGIC; s1,s2:INSTD_LOGIC; f :OUT STD_LOGIC);ENDmux_cascade;ARCHITECTUREdataflowOFmux2to1IS BEGIN f<=w1WHENs1=‘1'ELSEw2WHENs2=‘1’ELSEw3;ENDdataflow;fs1w0w10001(b)Truthtablew0w1s0w2w310110011101fs10s0w2w3(a)Graphicsymbol4-to-1Multiplexer4-to-1Multiplexer的VHDLLIBRARYieee;USEieee.std_logic_1164.all;ENTITYmux4to1IS PORT( w0,w1,w2,w3 :IN STD_LOGIC; s :IN STD_LOGIC_VECTOR(1DOWNTO0); f :OUT STD_LOGIC);ENDmux4to1;ARCHITECTUREdataflowOFmux4to1IS BEGIN WITHsSELECT f<=w0WHEN"00", w1WHEN"01", w2WHEN"10", w3WHENOTHERS;ENDdataflow;ECE448–FPGAandASICDesignwithVHDL解碼器2-to-4Decoder0011101y3w10w0xx11011En00100y2010