基于FPGA的UART模塊設(shè)計(jì)報(bào)告

第2部分UART模塊模塊框圖和功能簡(jiǎn)介UART模塊的主要作用是提供串口控制程序，與PC上位機(jī)進(jìn)行通信，將鍵盤按鍵對(duì)應(yīng)的ASCII碼輸出到串口終端上，通過上位機(jī)觀察鍵盤按鍵的ASCII碼，驗(yàn)證PS/2接口模塊的輸出結(jié)果的正確性。該模塊的輸入輸出示意圖如REF_Ref295250634\r\h圖1所示：UART模塊I/O端口其中，key_data是鍵盤按鍵對(duì)應(yīng)ASCII碼；key_int則為對(duì)應(yīng)的中斷信號(hào)，默認(rèn)時(shí)該信號(hào)始終保持高，當(dāng)鍵盤有鍵被按下，經(jīng)過PS/2模塊譯碼后將對(duì)應(yīng)的ASCII碼送到key_data上，然后將key_int拉低一個(gè)周期，表示新鍵被按下，UART模塊可以讀取key_data上的信號(hào)并能通過串口發(fā)送出去。clk和rst_n分別為系統(tǒng)時(shí)鐘（50MHz）和復(fù)位信號(hào)（低電平有效）；rs232_rx和rs232_tx分別為串口的接收信號(hào)線和發(fā)送信號(hào)線。模塊內(nèi)部框圖如REF_Ref295251586\r\h圖2所示：UART模塊內(nèi)部框圖UART模塊主要由三個(gè)子模塊構(gòu)成：speed_select、my_uart_rx和my_uart_tx。speed_select的主要功能是由系統(tǒng)時(shí)鐘產(chǎn)生串口通信所需要的波特率時(shí)鐘。由于本開發(fā)板的系統(tǒng)時(shí)鐘為50MHz，不同波特率對(duì)應(yīng)的分頻系數(shù)見下表：波特率分頻系數(shù)9600520719200260338400130157600867115200433speed_select的原理圖符合如REF_Ref295252303\r\h圖3所示：speed_select模塊原理圖在speed_select中，bps_start為時(shí)鐘使能信號(hào)，當(dāng)發(fā)送或接收模塊需要發(fā)送或接收數(shù)據(jù)時(shí)，將該信號(hào)線拉高，使能speed_select模塊產(chǎn)生對(duì)應(yīng)波特率所需要的時(shí)鐘，由clk_bps輸出。clk和rst_n分別為時(shí)鐘信號(hào)和復(fù)位信號(hào)。my_uart_rx則是串口接收模塊，主要功能是從主模塊的rs232_rx信號(hào)線上接收數(shù)據(jù)，完成串并轉(zhuǎn)換，然后輸出，其原理圖符合如REF_Ref295253364\r\h圖4所示：my_uart_rx模塊原理圖在my_uart_rx模塊中，bps_start為波特率時(shí)鐘使能信號(hào)，當(dāng)從rs232_rx信號(hào)線上檢測(cè)到下降沿（起始位）時(shí)，即將bps_start信號(hào)置位，從而使能發(fā)送波特率時(shí)鐘模塊（speed_rx，speed_select的一個(gè)實(shí)例），產(chǎn)生波特率時(shí)鐘，從clk_bps輸入。rx_data為接收到的數(shù)據(jù)的并行輸出。在本設(shè)計(jì)的UART模塊中，并不需要通過串口向開發(fā)板發(fā)送數(shù)據(jù)，因此如果出現(xiàn)了上位機(jī)通過串口向開發(fā)板發(fā)送數(shù)據(jù)的情況，不做別的響應(yīng)，僅將數(shù)據(jù)傳回。因此，rx_data被送到my_uart_tx模塊中。rx_int為接收數(shù)據(jù)中斷信號(hào)，每次數(shù)據(jù)接收完畢后，my_uart_rx模塊即在該信號(hào)線上產(chǎn)生一個(gè)周期的低電平。my_uart_tx檢測(cè)到該信號(hào)線上出現(xiàn)下降沿，即讀取rx_data中的數(shù)據(jù)。my_uart_tx模塊有兩個(gè)功能，一是將my_uart_rx模塊接收到的數(shù)據(jù)再發(fā)送回去，二是將ps/2模塊檢測(cè)到的按鍵的ASCII碼發(fā)送到串口上，該模塊原理圖符合如REF_Ref295253398\r\h圖5所示：my_uart_tx模塊原理圖由于需完成兩個(gè)功能，該模塊配套需要兩個(gè)波特率時(shí)鐘產(chǎn)生電路，分別由bps_start和bps_start_key使能，產(chǎn)生的波特率時(shí)鐘信號(hào)由clk_bps和clk_bps_key輸入。rx_data為接收到的數(shù)據(jù)，rx_int為接收數(shù)據(jù)中斷信號(hào)。key_data則為按鍵ASCII碼數(shù)據(jù)，key_int則為按鍵ASCII碼數(shù)據(jù)中斷信號(hào)，每當(dāng)在key_int上檢測(cè)到下降沿，my_uart_tx模塊就會(huì)讀取key_data上的數(shù)據(jù)并發(fā)送到rs232_tx上。綜合報(bào)告Copyright(c)1995-2007Xilinx,Inc.Allrightsreserved.CPU:0.00/0.20s|Elapsed:0.00/0.00s-->Parameterxsthdpdirsetto./xstCPU:0.00/0.20s|Elapsed:0.00/0.00sTABLEOFCONTENTS1)SynthesisOptionsSummary2)HDLCompilation3)DesignHierarchyAnalysis4)HDLAnalysis5)HDLSynthesis5.1)HDLSynthesisReport6)AdvancedHDLSynthesis6.1)AdvancedHDLSynthesisReport7)LowLevelSynthesis8)PartitionReport9)FinalReport9.1)Deviceutilizationsummary9.2)PartitionResourceSummary9.3)TIMINGREPORT=========================================================================*SynthesisOptionsSummary*=========================================================================----SourceParametersInputFileName:"my_uart_top.prj"InputFormat:mixedIgnoreSynthesisConstraintFile:NO----TargetParametersOutputFileName:"my_uart_top"OutputFormat:NGCTargetDevice:xc3s500e-4-fg320----SourceOptionsTopModuleName:my_uart_topAutomaticFSMExtraction:YESFSMEncodingAlgorithm:AutoSafeImplementation:NoFSMStyle:lutRAMExtraction:YesRAMStyle:AutoROMExtraction:YesMuxStyle:AutoDecoderExtraction:YESPriorityEncoderExtraction:YESShiftRegisterExtraction:YESLogicalShifterExtraction:YESXORCollapsing:YESROMStyle:AutoMuxExtraction:YESResourceSharing:YESAsynchronousToSynchronous:NOMultiplierStyle:autoAutomaticRegisterBalancing:No----TargetOptionsAddIOBuffers:YESGlobalMaximumFanout:500AddGenericClockBuffer(BUFG):24RegisterDuplication:YESSlicePacking:YESOptimizeInstantiatedPrimitives:NOUseClockEnable:YesUseSynchronousSet:YesUseSynchronousReset:YesPackIORegistersintoIOBs:autoEquivalentregisterRemoval:YES----GeneralOptionsOptimizationGoal:SpeedOptimizationEffort:1KeepHierarchy:NORTLOutput:YesGlobalOptimization:AllClockNetsReadCores:YESWriteTimingConstraints:NOCrossClockAnalysis:NOHierarchySeparator:/BusDelimiter:<>CaseSpecifier:maintainSliceUtilizationRatio:100BRAMUtilizationRatio:100Verilog2001:YESAutoBRAMPacking:NOSliceUtilizationRatioDelta:5==================================================================================================================================================*HDLCompilation*=========================================================================Compilingverilogfile"speed_select.v"inlibraryworkCompilingverilogfile"my_uart_tx.v"inlibraryworkModule<speed_select>compiledCompilingverilogfile"my_uart_rx.v"inlibraryworkModule<my_uart_tx>compiledCompilingverilogfile"my_uart_top.v"inlibraryworkModule<my_uart_rx>compiledModule<my_uart_top>compiledNoerrorsincompilationAnalysisoffile<"my_uart_top.prj">succeeded.=========================================================================*DesignHierarchyAnalysis*=========================================================================Analyzinghierarchyformodule<my_uart_top>inlibrary<work>.Analyzinghierarchyformodule<speed_select>inlibrary<work>.Analyzinghierarchyformodule<my_uart_rx>inlibrary<work>.Analyzinghierarchyformodule<my_uart_tx>inlibrary<work>.=========================================================================*HDLAnalysis*=========================================================================Analyzingtopmodule<my_uart_top>.Module<my_uart_top>iscorrectforsynthesis.Analyzingmodule<speed_select>inlibrary<work>.Module<speed_select>iscorrectforsynthesis.Analyzingmodule<my_uart_rx>inlibrary<work>.Module<my_uart_rx>iscorrectforsynthesis.Analyzingmodule<my_uart_tx>inlibrary<work>.Module<my_uart_tx>iscorrectforsynthesis.=========================================================================*HDLSynthesis*=========================================================================Performingbidirectionalportresolution...SynthesizingUnit<speed_select>.Relatedsourcefileis"speed_select.v".WARNING:Xst:1780-Signal<uart_ctrl>isneverusedorassigned.Found1-bitregisterforsignal<clk_bps_r>.Found13-bitupcounterforsignal<cnt>.Summary: inferred1Counter(s). inferred1D-typeflip-flop(s).Unit<speed_select>synthesized.SynthesizingUnit<my_uart_rx>.Relatedsourcefileis"my_uart_rx.v".WARNING:Xst-Property"use_dsp48"isnotapplicableforthistechnology.Found1-bitregisterforsignal<rx_int>.Found1-bittristatebufferforsignal<bps_start_r>.Found1-bitregisterforsignal<Mtridata_bps_start_r>.Found4-bitregisterforsignal<num>.Found4-bitadderforsignal<num$addsub0000>createdatline93.Found1-bitregisterforsignal<rs232_rx0>.Found1-bitregisterforsignal<rs232_rx1>.Found1-bitregisterforsignal<rs232_rx2>.Found1-bitregisterforsignal<rs232_rx3>.Found8-bitregisterforsignal<rx_data_r>.Found8-bitregisterforsignal<rx_temp_data>.Summary: inferred26D-typeflip-flop(s). inferred1Adder/Subtractor(s). inferred1Tristate(s).Unit<my_uart_rx>synthesized.SynthesizingUnit<my_uart_tx>.Relatedsourcefileis"my_uart_tx.v".Found1-bittristatebufferforsignal<bps_start_key_r>.Found1-bittristatebufferforsignal<bps_start_r>.Found1-bitregisterforsignal<key_en>.Found1-bitregisterforsignal<key_int0>.Found1-bitregisterforsignal<key_int1>.Found1-bitregisterforsignal<key_int2>.Found1-bitregisterforsignal<Mtridata_bps_start_key_r>.Found1-bitregisterforsignal<Mtridata_bps_start_r>.Found4-bitregisterforsignal<num>.Found4-bitadderforsignal<num$share0000>.Found1-bitregisterforsignal<rs232_tx_r>.Found1-bitregisterforsignal<rx_int0>.Found1-bitregisterforsignal<rx_int1>.Found1-bitregisterforsignal<rx_int2>.Found8-bitregisterforsignal<tx_data>.Found1-bitregisterforsignal<tx_en>.Summary: inferred23D-typeflip-flop(s). inferred1Adder/Subtractor(s). inferred2Tristate(s).Unit<my_uart_tx>synthesized.SynthesizingUnit<my_uart_top>.Relatedsourcefileis"my_uart_top.v".Unit<my_uart_top>synthesized.INFO:Xst:1767-HDLADVISOR-Resourcesharinghasidentifiedthatsomearithmeticoperationsinthisdesigncansharethesamephysicalresourcesforreduceddeviceutilization.Forimprovedclockfrequencyyoumaytrytodisableresourcesharing.=========================================================================HDLSynthesisReportMacroStatistics#Adders/Subtractors:24-bitadder:2#Counters:313-bitupcounter:3#Registers:321-bitregister:284-bitregister:28-bitregister:2#Tristates:31-bittristatebuffer:3==================================================================================================================================================*AdvancedHDLSynthesis*=========================================================================LoadingdeviceforapplicationRf_Devicefromfile'3s500e.nph'inenvironmentD:\Xilinx91i.=========================================================================AdvancedHDLSynthesisReportMacroStatistics#Adders/Subtractors:24-bitadder:2#Counters:313-bitupcounter:3#Registers:52Flip-Flops:52==================================================================================================================================================*LowLevelSynthesis*=========================================================================WARNING:Xst:2042-Unitmy_uart_tx:2internaltristatesarereplacedbylogic(pull-upyes):bps_start,bps_start_key.WARNING:Xst:2041-Unitmy_uart_rx:1internaltristateisreplacedbylogic(pull-upyes):bps_start.Optimizingunit<my_uart_top>...Optimizingunit<my_uart_rx>...Optimizingunit<my_uart_tx>...Mappingallequations...Buildingandoptimizingfinalnetlist...Foundareaconstraintratioof100(+5)onblockmy_uart_top,actualratiois1.FinalMacroProcessing...ProcessingUnit<my_uart_top>:INFO:Xst:741-HDLADVISOR-A2-bitshiftregisterwasfoundforsignal<my_uart_tx/key_int1>andcurrentlyoccupies2logiccells(1slices).Removingtheset/resetlogicwouldtakeadvantageofSRL16(andderived)primitivesandreducethisto1logiccells(1slices).Evaluateiftheset/resetcanberemovedforthissimpleshiftregister.Themajorityofsimplepipelinestructuresdonotneedtobeset/resetoperationally.INFO:Xst:741-HDLADVISOR-A2-bitshiftregisterwasfoundforsignal<my_uart_tx/rx_int1>andcurrentlyoccupies2logiccells(1slices).Removingtheset/resetlogicwouldtakeadvantageofSRL16(andderived)primitivesandreducethisto1logiccells(1slices).Evaluateiftheset/resetcanberemovedforthissimpleshiftregister.Themajorityofsimplepipelinestructuresdonotneedtobeset/resetoperationally.Unit<my_uart_top>processed.=========================================================================FinalRegisterReportMacroStatistics#Registers:91Flip-Flops:91==================================================================================================================================================*PartitionReport*=========================================================================PartitionImplementationStatus-------------------------------NoPartitionswerefoundinthisdesign.-------------------------------=========================================================================*FinalReport*=========================================================================FinalResultsTopLevelOutputFileName:my_uart_topOutputFormat:NGCOptimizationGoal:SpeedKeepHierarchy:NODesignStatistics#IOs:13CellUsage:#BELS:233#GND:1#INV:4#LUT1:36#LUT2:13#LUT2_D:3#LUT3:11#LUT3_D:1#LUT3_L:1#LUT4:77#LUT4_D:7#LUT4_L:3#MUXCY:36#MUXF5:3#VCC:1#XORCY:36#FlipFlops/Latches:91#FDC:52#FDCE:35#FDE:1#FDPE:1#FDSE:2#ClockBuffers:1#BUFGP:1#IOBuffers:12#IBUF:11#OBUF:1=========================================================================Deviceutilizationsummary:---------------------------SelectedDevice:3s500efg320-4NumberofSlices:92outof46561%NumberofSliceFlipFlops:91outof93120%Numberof4inputLUTs:156outof93121%NumberofIOs:13NumberofbondedIOBs:13outof2325%NumberofGCLKs:1outof244%---------------------------PartitionResourceSummary:---------------------------NoPartitionswerefoundinthisdesign.---------------------------=========================================================================TIMINGREPORTNOTE:THESETIMINGNUMBERSAREONLYASYNTHESISESTIMATE.FORACCURATETIMINGINFORMATIONPLEASEREFERTOTHETRACEREPORTGENERATEDAFTERPLACE-and-ROUTE.ClockInformation:-----------------------------------------------------+------------------------+-------+ClockSignal|Clockbuffer(FFname)|Load|-----------------------------------+------------------------+-------+clk|BUFGP|91|-----------------------------------+------------------------+-------+AsynchronousControlSignalsInformation:--------------------------------------------------------------------------------+-----------------------------+-------+ControlSignal|Buffer(FFname)|Load|----------------------------------------+-----------------------------+-------+my_uart_rx/rst_n_inv(rst_n_inv1_INV_0:O)|NONE(my_uart_rx/rx_data_r_1)|88|----------------------------------------+-----------------------------+-------+TimingSummary:---------------SpeedGrade:-4Minimumperiod:6.019ns(MaximumFrequency:166.141MHz)Maximumcombinationalpathdelay:NopathfoundTimingDetail:--------------Allvaluesdisplayedinnanoseconds(ns)=========================================================================Timingconstraint:DefaultperiodanalysisforClock'clk'Clockperiod:6.019ns(frequency:166.141MHz)Totalnumberofpaths/destinationports:1233/120-------------------------------------------------------------------------Delay:6.019ns(LevelsofLogic=4)Source:speed_key/cnt_2(FF)Destination:speed_key/cnt_11(FF)SourceClock:clkrisingDestinationClock:clkrisingDataPath:speed_key/cnt_2tospeed_key/cnt_11GateNetCell:in->outfanoutDelayDelayLogicalName(NetName)----------------------------------------------------FDC:C->Q30.5910.706speed_key/cnt_2(speed_key/cnt_2)LUT4_L:I0->LO10.7040.135speed_key/cnt_or000016(speed_key/cnt_or0000_map8)LUT4:I2->O110.7040.937speed_key/cnt_or000025(speed_key/cnt_or0000_map13)LUT4_D:I3->O20.7040.526speed_key/cnt_or000048(speed_key/cnt_or0000)LUT2:I1->O10.7040.000speed_key/Mcount_cnt_eqn_111(speed_key/Mcount_cnt_eqn_11)FDC:D0.308speed_key/cnt_11----------------------------------------Total6.019ns(3.715nslogic,2.304nsroute)(61.7%logic,38.3%route)=========================================================================Timingconstraint:DefaultOFFSETINBEFOREforClock'clk'Totalnumberofpaths/destinationports:57/57-------------------------------------------------------------------------Offset:4.812ns(LevelsofLogic=3)Source:rst_n(PAD)Destination:speed_key/cnt_7(FF)DestinationClock:clkrisingDataPath:rst_ntospeed_key/cnt_7GateNetCell:in->outfanoutDelayDelayLogicalName(NetName)----------------------------------------------------IBUF:I->O71.2180.883rst_n_IBUF(rst_n_IBUF)LUT2_D:I0->O90.7040.995speed_key/cnt_or000048_SW0(N365)LUT4:I0->O10.7040.000speed_key/Mcount_cnt_eqn_71(speed_key/Mcount_cnt_eqn_7)FDC:D0.308speed_key/cnt_7----------------------------------------Total4.812ns(2.934nslogic,1.878nsroute)(61.0%logic,39.0%route)=========================================================================Timingconstraint:DefaultOFFSETOUTAFTERforClock'clk'Totalnumberofpaths/destinationports:1/1-------------------------------------------------------------------------Offset:4.283ns(LevelsofLogic=1)Source:my_uart_tx/rs232_tx_r(FF)Destination:rs232_tx(PAD)SourceClock:clkrisingDataPath:my_uart_tx/rs232_tx_rtors232_txGateNetCell:in->outfanoutDelayDelayLogicalName(NetName)----------------------------------------------------FDPE:C->Q10.5910.420my_uart_tx/rs232_tx_r(my_uart_tx/rs232_tx_r)OBUF:I->O3.272rs232_tx_OBUF(rs232_tx)----------------------------------------Total4.283ns(3.863nslogic,0.420nsroute)(90.2%logic,9.8%route)=========================================================================CPU:20.38/20.62s|Elapsed:21.00/21.00s-->Totalmemoryusageis300512kilobytesNumberoferrors:0(0filtered)Numberofwarnings:4(0filtered)Numberofinfos:3(0filtered)源代碼UART模塊頂層設(shè)計(jì)`timescale1ns/1psmodulemy_uart_top( clk,rst_n, rs232_rx,rs232_tx, key_data,key_int );inputclk; //50MHz主時(shí)鐘inputrst_n; //低電平復(fù)位信號(hào)input[7:0]key_data;//鍵盤ASCII碼信號(hào)線inputkey_int; //鍵盤終端信號(hào),下降沿有效。先將數(shù)據(jù)送到key_data上，然后輸入key_int信號(hào)（低），保留一定時(shí)間后再拉高inputrs232_rx; //RS232接收數(shù)據(jù)信號(hào)outputrs232_tx; // RS232發(fā)送數(shù)據(jù)信號(hào)wirebps_start1,bps_start2,bps_start3; //接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位wireclk_bps1,clk_bps2,clk_bps3; wire[7:0]rx_data; //接收數(shù)據(jù)寄存器，//----------------------------------------------------speed_select speed_rx( .clk(clk), //波特率選擇模塊 .rst_n(rst_n), .bps_start(bps_start1), .clk_bps(clk_bps1) );my_uart_rx my_uart_rx( .clk(clk), //接收數(shù)據(jù)模塊 .rst_n(rst_n), .rs232_rx(rs232_rx), .rx_data(rx_data), .rx_int(rx_int), .clk_bps(clk_bps1), .bps_start(bps_start1) );/////////////////////////////////////////// speed_select speed_tx( .clk(clk), //波特率選擇模塊 .rst_n(rst_n), .bps_start(bps_start2), .clk_bps(clk_bps2) );speed_select speed_key( .clk(clk), //波特率選擇模塊 .rst_n(rst_n), .bps_start(bps_start3), .clk_bps(clk_bps3) ); my_uart_tx my_uart_tx( .clk(clk), //發(fā)送數(shù)據(jù)模塊 .rst_n(rst_n), .rx_data(rx_data), .rx_int(rx_int), .rs232_tx(rs232_tx), .clk_bps(clk_bps2), .bps_start(bps_start2), .key_data(key_data), .key_int(key_int), .clk_bps_key(clk_bps3), .bps_start_key(bps_start3) );endmodulespeed_select模塊`timescale1ns/1psmodulespeed_select( clk,rst_n, bps_start,clk_bps );inputclk; //50MHz主時(shí)鐘inputrst_n; //低電平復(fù)位信號(hào)inputbps_start; //接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位outputclk_bps; //clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)`define BPS_PARA 5207 //波特率為9600時(shí)的分頻計(jì)數(shù)值50`define BPS_PARA_2 2603 //波特率為9600時(shí)的分頻計(jì)數(shù)值的一半，用于數(shù)據(jù)采樣reg[12:0]cnt; //分頻計(jì)數(shù)regclk_bps_r; //波特率時(shí)鐘寄存器//----------------------------------------------------------reg[2:0]uart_ctrl; //uart波特率選擇寄存器//----------------------------------------------------------always@(posedgeclkornegedgerst_n) if(!rst_n)cnt<=13'd0; elseif((cnt==`BPS_PARA)||!bps_start)cnt<=13'd0; //波特率計(jì)數(shù)清零 elsecnt<=cnt+1'b1; //波特率時(shí)鐘計(jì)數(shù)啟動(dòng)always@(posedgeclkornegedgerst_n) if(!rst_n)clk_bps_r<=1'b0; elseif(cnt==`BPS_PARA_2)clk_bps_r<=1'b1; //clk_bps_r高電平為接收數(shù)據(jù)位的中間采樣點(diǎn),同時(shí)也作為發(fā)送數(shù)據(jù)的數(shù)據(jù)改變點(diǎn) elseclk_bps_r<=1'b0;assignclk_bps=clk_bps_r;endmodule串口接收模塊`timescale1ns/1psmodulemy_uart_rx( clk,rst_n, rs232_rx,rx_data,rx_int, clk_bps,bps_start );inputclk; //50MHz主時(shí)鐘inputrst_n; //低電平復(fù)位信號(hào)inputrs232_rx; //RS232接收數(shù)據(jù)信號(hào)inputclk_bps; //clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)outputbps_start; //接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位output[7:0]rx_data; //接收數(shù)據(jù)寄存器，保存直至下一個(gè)數(shù)據(jù)來到outputrx_int; //接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平//----------------------------------------------------------------regrs232_rx0,rs232_rx1,rs232_rx2,rs232_rx3; //接?帳菁拇嫫鰨瞬ㄓ?wireneg_rs232_rx; //表示數(shù)據(jù)線接收到下降沿always@(posedgeclkornegedgerst_n)begin if(!rst_n)begin rs232_rx0<=1'b0; rs232_rx1<=1'b0; rs232_rx2<=1'b0; rs232_rx3<=1'b0; end elsebegin rs232_rx0<=rs232_rx; rs232_rx1<=rs232_rx0; rs232_rx2<=rs232_rx1; rs232_rx3<=rs232_rx2; endend //下面的下降沿檢測(cè)可以濾掉<20ns-40ns的毛刺(包括高脈沖和低脈沖毛刺)， //這里就是用資源換穩(wěn)定（前提是我們對(duì)時(shí)間要求不是那么苛刻，因?yàn)檩斎胄盘?hào)打了好幾拍） //（當(dāng)然我們的有效低脈沖信號(hào)肯定是遠(yuǎn)遠(yuǎn)大于40ns的）assignneg_rs232_rx=rs232_rx3&rs232_rx2&~rs232_rx1&~rs232_rx0; //接收到下降沿后neg_rs232_rx置高一個(gè)時(shí)鐘周期//----------------------------------------------------------------regbps_start_r;reg[3:0]num; //移位次數(shù)regrx_int; //接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平always@(posedgeclkornegedgerst_n) if(!rst_n)begin bps_start_r<=1'bz; rx_int<=1'b0; end elseif(neg_rs232_rx)begin //接收到串口接收線rs232_rx的下降沿標(biāo)志信號(hào) bps_start_r<=1'b1; //啟動(dòng)串口準(zhǔn)備數(shù)據(jù)接收 rx_int<=1'b1; //接收數(shù)據(jù)中斷信號(hào)使能 end elseif(num==4'd12)begin //接收完有用數(shù)據(jù)信息 bps_start_r<=1'b0; //數(shù)據(jù)接收完畢，釋放波特率啟動(dòng)信號(hào) rx_int<=1'b0; //接收數(shù)據(jù)中斷信號(hào)關(guān)閉 endassignbps_start=bps_start_r;//----------------------------------------------------------------reg[7:0]rx_data_r; //串口接收數(shù)據(jù)寄存器，保存直至下一個(gè)數(shù)據(jù)來到//----------------------------------------------------------------reg[7:0]rx_temp_data; //當(dāng)前接收數(shù)據(jù)寄存器always@(posedgeclkornegedgerst_n) if(!rst_n)begin rx_temp_data<=8'd0; num<=4'd0; rx_data_r<=8'd0; end elseif(rx_int)begin //接收數(shù)據(jù)處理 if(clk_bps)begin //讀取并保存數(shù)據(jù),接收數(shù)據(jù)為一個(gè)起始位，8bit數(shù)據(jù)，1或2個(gè)結(jié)束位 num<=num+1'b1; case(num) 4'd1:rx_temp_data[0]<=rs232_rx; //鎖存第0bit 4'd2:rx_temp_data[1]<=rs232_rx; //鎖存第1bit 4'd3:rx_temp_data[2]<=rs232_rx; //鎖存第2bit 4'd4:rx_temp_data[3]<=rs232_rx; //鎖存第3bit 4'd5:rx_temp_data[4]<=rs232_rx; //鎖存第4bit 4'd6:rx_temp_data[5]<=rs232_rx; //鎖存第5bit 4'd7:rx_temp_data[6]<=rs232_rx; //鎖存第6bit 4'd8:rx_temp_data[7]<=rs232_rx; //鎖存第7bit default:; endcase end elseif(num==4'd12)begin //我們的標(biāo)準(zhǔn)接收模式下只有1+8+1(2)=11bit的有效數(shù)據(jù) num<=4'd0; //接收到STOP??后結(jié)束,num清零 rx_data_r<=rx_temp_data; //把數(shù)據(jù)鎖存到數(shù)據(jù)寄存器rx_data中 end endassignrx_data=rx_data_r; endmodule串口接收模塊`timescale1ns/1psmodulemy_uart_tx( clk,rst_n, rx_data,rx_int,rs232_tx, clk_bps,bps_start, key_data,key_int,clk_bps_key,bps_start_key //鍵盤輸入數(shù)據(jù) );inputclk; //50MHz主時(shí)鐘inputrst_n; //低電平復(fù)位信號(hào)inputclk_bps; //clk_bps_r高電平為接收數(shù)據(jù)位的中間采樣點(diǎn),同時(shí)也作為發(fā)送數(shù)據(jù)的數(shù)據(jù)改變點(diǎn)input[7:0]rx_data; //接收數(shù)據(jù)寄存器inputrx_int; //接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平,在該模塊中利用它的下降沿來啟動(dòng)串口發(fā)送數(shù)據(jù)input[7:0]key_data;//鍵盤按鍵對(duì)應(yīng)的ASCII碼inputkey_int;//向串口發(fā)送鍵盤按鍵ASCII碼的中斷信號(hào),不需??發(fā)送數(shù)據(jù)時(shí)該數(shù)據(jù)線應(yīng)時(shí)鐘為高inputclk_bps_key;//鍵盤輸入數(shù)據(jù)對(duì)應(yīng)的波特率時(shí)鐘outputbps_start_key; //開始產(chǎn)生波特率??鐘，該信號(hào)送給鍵盤ASCII碼對(duì)應(yīng)的那??speed_select??擇模塊outputrs232_tx; //RS232發(fā)送數(shù)據(jù)信號(hào)outputbps_start; //接收或者要發(fā)送數(shù)據(jù)，波特率時(shí)鐘啟動(dòng)信號(hào)置位//---------------------------------------------------------regrx_int0,rx_int1,rx_int2; //rx_int信號(hào)寄存器，捕捉下降沿濾波用wireneg_rx_int; //rx_int下降沿標(biāo)志位regkey_int0,key_int1,key_int2; //key_int信號(hào)寄存器，捕捉下降沿濾波用wirene