實(shí)驗(yàn)六 VGA顯示控制器設(shè)計(jì)

實(shí)驗(yàn)六VGA顯示控制器的設(shè)計(jì)(1)實(shí)驗(yàn)?zāi)康模簩W(xué)習(xí)VGA圖像顯示控制器的設(shè)計(jì)。(2)實(shí)驗(yàn)原理：55個(gè)信號(hào)R、G、B：三基色信號(hào)HS：行同步信號(hào)VS：場同步信號(hào)VGA工業(yè)標(biāo)準(zhǔn)要求的頻率：時(shí)鐘頻率(Clockfrequency)：25.175MHz(像素輸出的頻率)行頻(Linefrequency)：31469Hz場頻(Fieldfrequency)：59.94Hz(每秒圖像刷新頻率)VGA行掃描、場掃描時(shí)序示意圖實(shí)現(xiàn)電路【例13-1】LIBRARYIEEE;--VGA顯示器彩條發(fā)生器USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOLORISPORT(CLK,HS,VS,R,G,B:OUTSTD_LOGIC);--行場同步/紅，綠，蘭ENDCOLOR;ARCHITECTUREbehavOFCOLORISSIGNALHS1,VS1,FCLK,CCLK:STD_LOGIC;SIGNALMMD:STD_LOGIC_VECTOR(1DOWNTO0);--方式選擇SIGNALFS:STD_LOGIC_VECTOR(3DOWNTO0);SIGNALCC:STD_LOGIC_VECTOR(4DOWNTO0);--行同步/橫彩條生成SIGNALLL:STD_LOGIC_VECTOR(8DOWNTO0);--場同步/豎彩條生成SIGNALGRBX:STD_LOGIC_VECTOR(3DOWNTO1);--X橫彩條SIGNALGRBY:STD_LOGIC_VECTOR(3DOWNTO1);--Y豎彩條SIGNALGRBP:STD_LOGIC_VECTOR(3DOWNTO1);SIGNALGRB:STD_LOGIC_VECTOR(3DOWNTO1);BEGINGRB(2)<=(GRBP(2)XORMD)ANDHS1ANDVS1;GRB(3)<=(GRBP(3)XORMD)ANDHS1ANDVS1;GRB(1)<=(GRBP(1)XORMD)ANDHS1ANDVS1;PROCESS(MD)BEGINIFMD'EVENTANDMD='0'THENIFMMD="10"THENMMD<="00";ELSEMMD<=MMD+1;ENDIF;--三種模式ENDIF;ENDPROCESS;PROCESS(MMD)BEGINIFMMD="00"THENGRBP<=GRBX;--選擇橫彩條ELSIFMMD="01"THENGRBP<=GRBY;--選擇豎彩條ELSIFMMD="10"THENGRBP<=GRBXXORGRBY;--產(chǎn)生棋盤格ELSEGRBP<="000";ENDIF;ENDPROCESS;PROCESS(CLK)BEGINIFCLK'EVENTANDCLK='1'THEN--13MHz13分頻IFFS=13THENFS<="0000";ELSEFS<=(FS+1);ENDIF;ENDIF;ENDPROCESS;FCLK<=FS(3);CCLK<=CC(4);PROCESS(FCLK)BEGINIFFCLK'EVENTANDFCLK='1'THENIFCC=29THENCC<="00000";ELSECC<=CC+1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CCLK)BEGINIFCCLK'EVENTANDCCLK='0'THENIFLL=481THENLL<="000000000";ELSELL<=LL+1;ENDIF;ENDIF;ENDPROCESS;PROCESS(CC,LL)BEGINIFCC>23THENHS1<='0';--行同步ELSEHS1<='1';ENDIF;IFLL>479THENVS1<='0';--場同步ELSEVS1<='1';ENDIF;ENDPROCESS;PROCESS(CC,LL)BEGINIFCC<3THENGRBX<="111";--橫彩條ELSIFCC<6THENGRBX<="110";ELSIFCC<9THENGRBX<="101";ELSIFCC<13THENGRBX<="100";ELSIFCC<15THENGRBX<="011";ELSIFCC<18THENGRBX<="010";ELSIFCC<21THENGRBX<="001";ELSEGRBX<="000";ENDIF;IFLL<60THENGRBY<="111";--豎彩條ELSIFLL<130THENGRBY<="110";ELSIFLL<180THENGRBY<="101";ELSIFLL<240THENGRBY<="100";ELSIFLL<300THENGRBY<="011";ELSIFLL<360THENGRBY<="010";ELSIFLL<420THENGRBY<="001";ELSEGRBY<="000";ENDIF;ENDPROCESS;HS<=HS1;VS<=VS1;R<=GRB(2);G<=GRB(3);B<=GRB(1);ENDbehav;(2)實(shí)驗(yàn)內(nèi)容1：根據(jù)圖13-3和程序13-1，完成VGA彩條信號(hào)顯示的驗(yàn)證性實(shí)驗(yàn)。根據(jù)圖13-3引腳鎖定：R、G、B分別接PIO68、PIO69、PIO70；HS、VS分別接PIO71、PIO73；CLK接clock9（13MHz），MD接PIO0，控制顯示模式。接上VGA顯示器，選擇模式5，下載COLOR.SOF；控制鍵1，觀察顯示器工作（如果顯示不正常，將GW48系統(tǒng)右側(cè)開關(guān)撥以下，最后再撥回到“TO_MCU”）。(3)實(shí)驗(yàn)內(nèi)容2：設(shè)計(jì)可顯示橫彩條與棋盤格相間的VGA彩條信號(hào)發(fā)生器。(4)實(shí)驗(yàn)內(nèi)容3：設(shè)計(jì)可顯示英語字母的VGA信號(hào)發(fā)生器電路。（5）實(shí)驗(yàn)報(bào)告：根據(jù)以上的實(shí)驗(yàn)內(nèi)容寫出實(shí)驗(yàn)報(bào)告，包括程序框圖說明、各模塊工作原理、軟件編譯過程中遇到的問題、硬件測試和實(shí)驗(yàn)過程。下面是能力培養(yǎng)VGA圖像控制器框圖【例13-2】LIBRARYieee;--圖象顯示頂層程序USEieee.std_logic_1164.all;ENTITYimgIS port (clk50MHz:INSTD_LOGIC; hs, vs, r,g,b:OUTSTD_LOGIC);ENDimg;ARCHITECTUREmodelstruOFimgIScomponentvga640480--VGA顯示控制模塊 PORT(clk:INSTD_LOGIC; rgbin:INSTD_LOGIC_VECTOR(2downto0); hs,vs,r,g,b:OUTSTD_LOGIC; hcntout,vcntout:OUTSTD_LOGIC_VECTOR(9downto0) );endcomponent;componentimgrom--圖象數(shù)據(jù)ROM，數(shù)據(jù)線3位；地址線13位 PORT(inclock:INSTD_LOGIC; address:INSTD_LOGIC_VECTOR(11downto0); q:OUTSTD_LOGIC_VECTOR(2downto0) );endcomponent;signal rgb:STD_LOGIC_VECTOR(2downto0);signal clk25MHz:std_logic;signal romaddr:STD_LOGIC_VECTOR(11downto0);signal hpos,vpos :std_logic_vector(9downto0);BEGINromaddr<=vpos(5downto0)&hpos(5downto0);process(clk50MHz)beginifclk50MHz'eventandclk50MHz='1'thenclk25MHz<=notclk25MHz;endif;endprocess;i_vga640480:vga640480PORTMAP(clk=>clk25MHz,rgbin=>rgb,hs=>hs,vs=>vs,r=>r,g=>g,b=>b,hcntout=>hpos,vcntout=>vpos);i_rom:imgromPORTMAP(inclock=>clk25MHz,address=>romaddr,q=>rgb);END；【例13-3】LIBRARYIEEEuseIEEE.std_logic_1164.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;entityvga640480is port( clk :inSTD_LOGIC; hs, vs, r,g,b :outSTD_LOGIC; rgbin :instd_logic_vector(2downto0); hcntout,vcntout :outstd_logic_vector(9downto0) );endvga640480;architectureONEofvga640480issignalhcnt,vcnt :std_logic_vector(9downto0); beginhcntout<=hcnt;vcntout<=vcnt;process(clk)begin if(rising_edge(clk))then if(hcnt<800)then hcnt<=hcnt+1; elsehcnt<=(others=>'0');endif; endif; endprocess;process(clk)begin if(rising_edge(clk))then if(hcnt=640+8)then if(vcnt<525)then vcnt<=vcnt+1; elsevcnt<=(others=>'0'); endif;endif; endif; endprocess;process(clk)begin if(rising_edge(clk))then if((hcnt>=640+8+8)and(hcnt<640+8+8+96))thenhs<='0'; elsehs<='1'; endif; endif;endprocess;process(vcnt)begin if((vcnt>=480+8+2)and(vcnt<480+8+2+2))thenvs<='0'; elsevs<='1';endif;endprocess;process(clk)begin if(rising_edge(clk))then if(hcnt<640andvcnt<480)then r<=rgbin(2);g<=rgbin(1);b<=rgbin(0); elser<='0';g<='0';b<='0';endif; endif;endprocess;endONE;13-2.VGA圖像顯示控制器設(shè)計(jì)(1)實(shí)驗(yàn)內(nèi)容1：根據(jù)圖13-4和程序例13-2/3，設(shè)計(jì)與生成圖象數(shù)據(jù)；根據(jù)例13-2中imgrom元件的接口，定制放置圖象數(shù)據(jù)的ROM。(2)實(shí)驗(yàn)內(nèi)容2：硬件驗(yàn)證例13-2/3，選擇模式5，引腳連接方式仍同圖13-4，只是時(shí)鐘輸入clk50MHz接clock0，選擇頻率50MHz的時(shí)鐘信號(hào)。在EDA系統(tǒng)上接上VGA顯示器，下載后觀察圖形顯示情況。(3)實(shí)驗(yàn)內(nèi)容3：為此設(shè)計(jì)增加一個(gè)鍵，控制輸出圖象的正色與補(bǔ)色。(4)實(shí)驗(yàn)內(nèi)容4：為了顯示更大的圖象，用外部ROM取代FPGA的內(nèi)部ROM，即imgrom元件，電路結(jié)構(gòu)參考圖13-4，引腳鎖定參考電路結(jié)構(gòu)圖NO.5圖中的ROM27C020/27C040與FPGA的引腳連接情況。示例程序可下載./VGA88/vgarom.sof，或./VGAbb/vgarom.sof，clock0接50MHz，GW48EDA系統(tǒng)左下角的撥碼開關(guān)的“ROM使能”撥向下（如果顯示不正常，將EDA系統(tǒng)右側(cè)開關(guān)撥以下，最后再撥回到“TO_MCU”）。選擇模式5，鍵1控制圖象的正色與補(bǔ)色顯示。注意，實(shí)驗(yàn)結(jié)束后將撥碼開關(guān)的“ROM使能”撥向上還原。下面是Imgrom模塊里的幾個(gè)MIF數(shù)據(jù)（清華的標(biāo)志）。如果位數(shù)不同，請(qǐng)修改ROM的地址寬度。1號(hào)WIDTH=1;DEPTH=16384;ADDRESS_RADIX=UNS;DATA_RADIX=UNS;CONTENTBEGIN [0..309]:0; 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