時(shí)序電路設(shè)計(jì)ASM

SynchronousSequentialCircuitsAnalysisofSynchronousSSLCDesignofSynchronousSSLCThereverseofanalysisClassicalapproach(Statediagrams)Flowchartapproach(analogoustothoseusedincomputerprogramming)References:Handouts;VictorP.Nelson,DigitalLogicCircuitAnalysisandDesign,清華大學(xué)出版社,1997,pp547~5522023/1/16294CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgorithmicStateMachinesAlgorithmicStateMachine(ASM)ASMChartsStateAssignmentsASMTablesASMRealizations2023/1/16295CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgorithmicStateMachine(ASM)PartitioningofDigitalSystemModelofASMTimingofASMASMVersaMealy/MooreAlgorithm:awelldefinedprocedureconsistingofafinitenumberofstepstothesolutionofaproblem2023/1/16296CopyrightreservedbyProf.Luo,TsinghuaUniv.PartitioningofDigitalSystemController(ASM)Controlledarchitecture(Dataprocessor)StatusinformationInputdataOutputdataExternalinputsDataprocessor:provideforthemanipulationofdataFlip-flops,shiftregisters,counters,adders/subtracters,comparatorsShiftleft,shiftright,subtract,increment,reset,etcController:supplyatimesequenceofcommandstodataprocessorhardwarealgorithm,ASMAclockedsynchronoussequentialnetworkhavingseveralstates,eachassociatedwiththeproductionofasetofcommands2023/1/16297CopyrightreservedbyProf.Luo,TsinghuaUniv.TwoApplicationsofASMDataprocessor+ControllerIncorporatingMSIASMasacontrollerNodataprocessorASMasastand-alonesequentialnetworkmodelAclassicalMealynetworkorMoorenetwork2023/1/16298CopyrightreservedbyProf.Luo,TsinghuaUniv.ModelofASMNextstatefunction(CSLC)Memory(Stateregister)NextstateStatetimeTStateOutputsInputsStateoutputfunction(CSLC)Conditionaloutputfunction(CSLC)PresentstateConditionalOutputsMealyMoore2023/1/16299CopyrightreservedbyProf.Luo,TsinghuaUniv.TimingofASMTimeiTTransitionperiodStableperiodStatetimeNextstatereplacespresentstateNextstatereplacespresentstateTransitionperiodStableperiodStatetimeNextstatereplacespresentstate(i+1)T(i+2)T2023/1/16300CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMVersaMealy/MooreDefineBehaviorASMinvolvesamorephysicalinterpretationofnetworkoperationThenextstateandoutputfunctionsaredefinedfortheentirestableperiodofastatetimeMealy/MooredefinesonlyatthesamplinginstantsBothconditionalandstateoutputscanoccurinthesameASM2023/1/16301CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgorithmicStateMachinesAlgorithmicStateMachine(ASM)ASMChartsStateAssignmentsASMTablesASMRealizations2023/1/16302CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMChartsAblockdiagramstructuresuperficiallysimilartotheflowchartsusedinsoftwaredesignWhat’sthedifference?ThreeBasicComponentsASMBlocksASMChartsStateDiagramversaASMCharts2023/1/16303CopyrightreservedbyProf.Luo,TsinghuaUniv.What’sthedifference?TimeInterpretationSoftware:describethesequenceofevents/tasksASM:describeasequenceoftimeintervalsEachASMBlockwithacollectionofboxlikesymbolscorrespondstoasingletimeinterval,i.e.,astatetime2023/1/16304CopyrightreservedbyProf.Luo,TsinghuaUniv.ThreeBasicComponentsStateBoxDecisionBoxConditionalOutputBoxEntrypathExitpath(tostate/decisionbox)StatecodeStateoutputlist(optional)Logic-1whenassertedStatename2023/1/16305CopyrightreservedbyProf.Luo,TsinghuaUniv.DecisionBoxProvidefornextstatealternativesandconditionaloutputsbasedonthelogicvalueofaBooleanexpressioninvolvingtheexternalinputsandthestatusinformation1EntrypathConditionfalseexitpathCondition(Booleanexpression)Conditiontrueexitpath01EntrypathConditionfalseexitpathConditiontrueexitpath0(tostate/decision/conditionalbox)2023/1/16306CopyrightreservedbyProf.Luo,TsinghuaUniv.ConditionalOutputBoxFromadecisionbox,toadecision/stateboxNotimedependenceasthedecisionboxEntrypathExitpathConditionaloutputlist2023/1/16307CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMBlocksConstructusingthebasicASMcomponentsConsistoftheinterconnectionofasinglestateboxalongwithacollectionofdecisionandconditionaloutputboxesOneentrypath,oneormoreexitpathsLinkpath:apaththroughanASMblockfromitsstateboxtoanexitpath2023/1/16308CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMBlocksz1z2z4z5x1z301x201x301EntrypathExitpath1Exitpath2Exitpath32023/1/16309CopyrightreservedbyProf.Luo,TsinghuaUniv.EquivalentASMBlocksz1x1z201x201x301Exitpath1Exitpath2z1x1+x2x3z201Exitpath1Exitpath22023/1/16310CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMChartsz1z2z311170000z1z21106z11004z30011z20102z2z30113z1z31015Mod-8binarycounter2023/1/16311CopyrightreservedbyProf.Luo,TsinghuaUniv.BinaryMultiplierConventionalmultiplicationThenumberofbitsintheproductoftwoN-bitsintegersis2NbitsAlternateapproachAdd+ShiftThenumberofbitsinthesumoftwoN-bitsintegersisN+1bits1010110110101010101000001000001000001010MultiplierDigit101010010100000000101000101011010011001001100101101010000010100000102023/1/16312CopyrightreservedbyProf.Luo,TsinghuaUniv.ArchitectureforBinaryMultiplierFlip-FlopCRegisterARegisterMParalleladderRegisterBSRINIT0INITINITADDM1MultiplicandMultiplierSumCoutProductCounterZerodetectorINITDECREAMNController(ASM)INITADDDECREAMSRCOMPLETEM1SZZ2023/1/16313CopyrightreservedbyProf.Luo,TsinghuaUniv.ThesignalsassociatedwithASMInputsS=1,themultiplicationprocessistostartM1=1,addmultiplicand;M1=0,add0z=1,thecontentofthecounteriszeroOutputsINIT=1,initialization;C=0,A=0;N=thenumberofbitsinthemultiplier;M=multiplier,B=multiplicandDECREM=1,enablethecounterfordecrementingADD=1,A=A+B,C=0ifnocarry;C=1ifhavingcarrySR=1,rightshiftC+A+MCOMPLETE=1,themultiplicationprocessiscompleted2023/1/16314CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMChartsforBinaryMultiplierDECREM02M11ADDSR03z1COMPLETE01S1INIT2023/1/16315CopyrightreservedbyProf.Luo,TsinghuaUniv.Flip-FlopCRegisterARegisterMParalleladderRegisterBSRINIT0INITINITADDM1MultiplicandMultiplierSumCoutCounterZerodetectorINITDECREAMNController(ASM)INITADDDECREAMSRCOMPLETEM1SZ000010101101041000000111113111010101010+000011Shift:A+M=01010110Z=002001Shift:A+M=001010112023/1/16316CopyrightreservedbyProf.Luo,TsinghuaUniv.StateDiagramVersaASMChartsz10Ax1z1z20Cx1z20Bx1z1z20A/10x1B/01C/1110102023/1/16317CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgorithmicStateMachinesAlgorithmicStateMachine(ASM)ASMChartsStateAssignmentsASMTablesASMRealizations2023/1/16318CopyrightreservedbyProf.Luo,TsinghuaUniv.StateAssignmentsz3z40Cx31z1Dz3Ez10Ax11z20Bx11z30x2z21000111100ABC-1ED--Q2Q3Q1000001011101100MinimumstatelocusAB,000001,1bitchangeBA,001000,1bitchangeBC,001011,1bitchangeBD,001101,1bitchangeCD,011101,2bitchangeDE,101100,1bitchangeEA,100000,1bitchange8statelocus2023/1/16319CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgorithmicStateMachinesAlgorithmicStateMachine(ASM)ASMChartsStateAssignmentsASMTablesASMRealizations2023/1/16320CopyrightreservedbyProf.Luo,TsinghuaUniv.ASMTransitionTablesLinkpathPresentstateInputsx1x2x3NextstateOutputsz1z2z3z4L1A0––A1000L2A1––B1100L3B00–A0000L4B01–C0100L5B1––D0010L6C––0C0011L7C––1D0011L8D–––E1000L9E–––A00102023/1/16321CopyrightreservedbyProf.Luo,TsinghuaUniv.AssignedASMTransitionTablesLinkpathPresentstateQ1Q2Q3Inputsx1x2x3NextstateQ+1Q+2Q+3Outputsz1z2z3z4L1A0000––A0001000L2A0001––B0011100L3B00100–A0000000L4B00101–C0110100L5B0011––D1010010L6C011––0C0110011L7C011––1D1010011L8D101–––E1001000L9E100–––A00000102023/1/16322CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgebraicRepresentationofAssignedASMTransitionTables2023/1/16323CopyrightreservedbyProf.Luo,TsinghuaUniv.Simplificationwithdon’tcarestatesUsingK-maps2023/1/16324CopyrightreservedbyProf.Luo,TsinghuaUniv.AssignedASMExcitationTablesLinkpathP-stateQ1Q2Q3Inputsx1x2x3NextstateD1D2D3J1K1J2K2J3K3Outputsz1z2z3z4L1A0000––A0000–0–0–1000L2A0001––B0010–0–1–1100L3B00100–A0000–0––10000L4B00101–C0110–1––00100L5B0011––D1011–0––00010L6C011––0C0110––0–00011L7C011––1D1011––1–00011L8D101–––E100–00––11000L9E100–––A000–10–0–00102023/1/16325CopyrightreservedbyProf.Luo,TsinghuaUniv.AlgorithmicStateMachinesAlgorithmicStateMachine(ASM)ASMChartsStateAssignmentsASMTablesASMRealizations2023/1/16326CopyrightreservedbyProf.Luo,TsinghuaUniv.RealizationsUsingDiscreteGates

andDFlip-flopsz1z2z3z4Q1Q2Q3Q2Q2Q3Q3Q3Q3x1Q2x3Q1x2Q2x1x2Q3x2Q3Q1x1Q2Q3x1Q12023/1/16327CopyrightreservedbyProf.Luo,TsinghuaUniv.RealizationsUsingMultiplexersVariable-enteredKarnaughmapsP-stateQ1Q2Q3Inputsx1x2x3Q+1Q+2Q+3D1D2D3A0000––000A0001––001B00100–000B00101–01