《微機(jī)原理及應(yīng)用實(shí)踐(英文版)》Chapter 2 　 8086 MICROPROCESSOR ARCHITECTURE

Chapter２MICROPROCESSOR-BASEDSYSTEMS2.1Introduction2.2Architectureof8086Microprocessor2.38086CPURegisters2.48086PinsandFunctions2.58086MemoryOrganization2.68086MemoryandI/OOperationCyclesOBJECTIVES

Uponfinishingthischapter,youwilllearn:

Architectureof8086CPU(theoperationoftheexecutionunitandthebusinterfaceunit)

8086CPURegisters(theinternalregistersarray)

PinsandFunctionsof8086/8088CPU

MemorySegmentationandaddressorganization

MemoryandI/Ooperationcycles

2.1Introduction

Sincethe80x86microprocessorfamilyhasatypicalbasicstructure,itsarrivalonthecomputerscenehasquicklytakentheleadinthepersonalcomputermarket.Inotherwords,the80x86processorisusedeverywhere,fromdedicatedcontrolsystemstofastnetworkfileservers.Today,thePentiumofferscompatibilitywithallprevious80x86machines,withmanynewarchitecturalimprovements.

Intel8086isa16bitmicroprocessor,andithas16bitdatabusand20bitaddressbus.However,thedifferentmicroprocessorhasdifferentinternalarchitectureanddifferentfeatures,buttheinternalarchitectureofIntel8088microprocessorissameas8086microprocessorexcept8088microprocessorhas8bitdatabus.

Theybothemployparallelprocessing—thatis,theyareimplementedwithseveralsimultaneouslyoperatingprocessingunits.Theycandirectlyaddress1megabytesofmemory.Thememoryusedby8086microprocessorisbytesandeachbytecanbeaddresseduniquelywith20bitaddresses.

Theexternalmemoryof8086microprocessorisdividedintotwobanks:evenbankandoddbank.Theevenbankofmemoryisaccessedbyevenaddresslike00000H,00002H,00004H…upto0FFFFEHandoddbankofmemoryisaddressedbyoddaddresseslike00001H,00003H,00005H…upto0FFFFFH.A16bitwordof8086microprocessorisstoredintwoconsecutiveaddressesasbytes.Aninstructionwordof8086microprocessoraccessesmemorystartingwithevenaddress.

Intel8086microprocessor,developedbyIntelCorporation,hasthreeversions:Intel8086,Intel8086-2andIntel8086-4.Theyaresimilarinarchitectureexcepttheirspeedofoperation:maximumclockfrequencyof5MHz,8MHzand4MHzrespectively.

Inthischapter,wewillpresentthefeaturesofthe80x86microprocessorfamilyandmainlydiscussthearchitectureof8086microprocessor.Pinfunction,modeofoperation,clockgenerationandbustimingetcof8086microprocessorwillbecovered,leavingthehardwareandsoftwaredetailstotheupcomingchapters.Fromthischapteryouwilllearnthatthe80x86isamachinewithmanypossibilities.

2.2Architectureof8086Microprocessor

Figure2.1illustratestheinternalarchitectureofthe8086processor.Itcontainstwoprocessingunits:theBusInterfaceUnit(BIU)andtheExecutionUnit(EU).Eachunithasdedicatedfunctionsandbothoperateatthesametime.Inessence,thisparallelprocessingeffectivelymakesthefetch,decodingandexecutionofinstructionsindependenton8088/8086microprocessorsystems.BIUandEUareshownonbothsidesofthedottedlineinFigure2.1.Therewillbeabriefintroductiontothetwopartsbelow.

TheBIUisthe8086’sconnectiontotheoutsideworld.Byinterface,wemeanthepathbywhichitconnectstoexternaldevices,likememoryorI/Odevices.TheBIUisresponsibleforperformingallexternalbusoperations.1Itsfunctionsincludeaddressgeneration,instructionfetching,instructionqueuing,readingandwritingofdataoperandformemory,inputtingoroutputtingdataforinput/outputperipherals,andbuscontrollogic.Theseinformationtransferstakeplaceoverthesystembus.

Thisbusincludesa16-bitbidirectionaldatabus,a20-bitaddressbus,andthesignalcontrolbusneededtocontroltransfersoverthebus,butfordatabustherearesomedifferencesherewiththe8088microprocessor.TheBIUisnotonlyresponsibleforperformingbusoperations;italsoperformsotherfunctionsrelatedtoinstructionanddataacquisition.Forinstance,itisresponsibleforinstructionqueuingandaddressgeneration.AswecanseeinFigure2.1,toimplementthesefunctions,theBIUcontainsthesegmentregisters,theinstructionpointer,theaddressgenerationadder,buscontrollogic,andaninstructionqueue.Figure2.1Internalstructureof8086CPU(CourtesyofIntelCorporation)

[ReadingMaterial]TheBIUusesamechanismknownasaninstructionqueuetoimplementapipelinedarchitecture.Thisqueuepermitsthe8086toprefetchupto6bytes(4bytesforthe8088)ofinstructioncode.Wheneverthequeueisnotfull—thatis,ithasroomforatleast2morebytes,andatthesametime,theexecutionunitisnotaskingittoreadorwritedatafrommemory—theBIUisfreetolookaheadintheprogrambyprefetchingthenextsequentialinstructions.Prefetchedinstructionsareheldinthefirst-infirst-out(FIFO)queue.

Wheneverabyteisloadedattheinputendofthequeue,itisautomaticallyshiftedupthroughtheFIFOtotheemptylocationnearesttheoutput.Herethecodeishelduntiltheexecutionunitisreadytoacceptit.Sinceinstructionsarenormallywaitinginthequeue,thetimeneededtofetchmanyinstructionsofthemicrocomputer’sprogramiseliminated.IfthequeueisfullandtheEUisnotrequestingaccesstodatainmemory,theBIUdoesnotneedtoperformanybusoperations.Theseintervalsofnobusactivity,whichoccurbetweenbusoperations,areknownasidlestates.

TheEUisresponsiblefordecodingandexecutinginstructions.NoticeinFigure2.1thatitconsistsoftheArithmeticLogicalUnit(ALU)withtemporary-operandregisters,statusandcontrolflags,general-purposeregisters,andEUcontrolsystem.TheEUaccessinstructionsfromtheoutputendoftheinstructionqueueanddatafromthegeneral-purposeregistersormemory.Itreadsoneinstructionbyteaftertheother,decodesthem,generatesdataaddressesifnecessary,passesaddressestotheBIUandrequestsittoperformthereadorwriteoperationstomemoryorI/O,andfinallyperformstheoperationspecifiedbytheinstruction.

TheALUperformsthearithmetic,logic,andshiftoperationsrequiredbyaninstruction,sometimesitusetemporaryoperandregisters.Duringexecutionoftheinstruction,theEUmaytestthestatusandcontrolflags,andupdatestheseflagsbasedontheresultsofexecutingtheinstruction.Sothefetching,decodingandexecutionofinstructionformsonecycle,andtheseprocessesaredrivenbyEUcontrolsystem.

[ReadingMaterial]Thearithmeticandlogicalunit(ALU)iswheremostoftheactiontakesplaceinsidetheCPU.Forexample,ifyouwanttoaddthevaluefivetotheAXregister,theCPUwilloperatelikethis:

CopiesthevaluefromAXintotheALU;

SendsthevaluefivetotheALU;

InstructstheALUtoaddthesetwovaluestogether;

MovestheresultbackintotheAXregister.

Asamatteroffact,theALUisoneofthe8086microprocessor’smajorlogicfunctions.Itcontainstheprocessor’sdataprocessinglogic.Figure2.2illustratestheoperationstructureofALU.

TheALUhastwoinputports.OnthediagramtheyarelabeledIN.TheALUalsohasoneoutputport,labeledOUT,inadditionalonemarkinformation-flagregister.Aninputportismadeupofthelogiccircuitsusedtogetadatawordoutofalogicdevice.Mostlogicdeviceshaveoneormoreinputportsandasingleoutputport.Thesimplestanalogy,forexample,istheANDgate.Ithastwoinputsandanoutput.ThesearealsocalledtheANDgate’sinputportsandoutputport.Figure2.2TheoperationstructureofALU

Bothoftheinputportsarebufferedbyatemporaryregister(shownasTemp1andTemp2onthediagram);thatis,eachporthasaregisterthattemporarilystoresonedataword,holdingthewordfortheALU.

The8086microprocessor’sinternalbusisconnectedtotheALU’stwoinputportsthroughthetwotemporaryregisters.Thisallowsittotakedatafromanydeviceontheprocessor’sinternaldatabus.Often,theALUgetsitsdatafromaspecialregistercalledtheaccumulator.

Inthe8086microprocessor,theaccumulatoristheAXregister.TheALU’ssingleoutputportallowsittosendadatawordoverthebustoanydeviceconnectedtothebus.Frequently,dataissenttotheaccumulator.WhentheALUaddstwowords,forexample,oneofthetwowordsisplacedintheaccumulator.Aftertheadditionisperformed,theresultingdatawordissenttotheaccumulatorandstoredthere.

TheALUworksoneitheroneortwodatawords,dependingonthekindofoperationperformed.TheALUusesinputportsasnecessary.Sinceadditionrequirestwodatawords,forexample,anadditionoperationusesbothALUinputports.

Complementingadataword,conversely,usesonlyoneinputport.Tocomplementadatawordalloftheword’sbitsthatarelogic1aresettologic0,andalloftheword’sbitsthatarelogic0aresettologic1.Asyoucansee,theALUneedstoworkononlyonewordtoperformacomplementoperation.Thatiswhythecomplementoperationusesonlyoneinputport.

TheALUisusedwheneveritisnecessarytochangeortestadataword.ALUfunctionsarepartofthe8086microprocessor’sarchitecture.TheALU’smainfunctionsarelistedasbelow:

ADD

Complement

Subtract

Shiftright

AND Shiftleft

OR Increment

ExclusiveOR Decrement

TheimportantpointtorememberisthatanyinstructionthatchangesdatamustusetheALU.BecausetheALUprocessesdata,butdoesnotstoreanydata,itmaynotbepartofsomeprogrammingmodels.Figure2.3Workingcycleofmicroprocessor

2.38086CPU

Registers

Registersaremainstorageusedtosavedatainmicroprocessor.The8086microprocessorcontainsfourteen16-bitregistersintotalwhichreferredtoasAX,BX,CX,DX,SP,BP,SI,DI,CS,DS,SS,ES,IP,andFLAGS.Theycanbedividedintothreecategories:generalpurposeregisters,segmentregisters,andmiscellaneousregisters,whicharedistributedinEU,BIUandelsewhere.

2.3.1RegistersinEU

The8086microprocessorcontainsfourdataregistersreferredtoasAX,BX,CX,andDX,areshowninTable2.1.Allare16bitswideandmaybesplitupintotwohalvesof8bitseach.Duringprogramexecution,theyholdtemporaryvalueswhicharefrequentlyusedasintermediateresults.Softwarecanread,load,ormodifytheircontents.AnyofthefourregisterscanbeusedasthesourceordestinationofanoperandduringanarithmeticoperationsuchasADDoralogicoperationsuchasAND.Theadvantageofstoringthesedataininternalregistersinsteadofmemoryduringprocessingisthattheycanbeaccessedmuchfaster.

Fiveother16-bitregistersareavailableforuseaspointerorindexregisters.TheseregistersaretheStackPointer(SP),BasePointer(BP),SourceIndex(SI),DestinationIndex(DI),andInstructionPointer(IP)(latewewilltalkaboutIPlatter).Noneofthefivemaybedividedupinamannersimilartothedataregisters.

TheSP,BP,SI,andDIregistersarepointerandindexregisters,respectively,asshowninTable2.1.Softwareusesthevalueheldinanindexregistertoreferencedatainmemoryrelativetothedatasegmentorextrasegmentregister,andapointerregistertoaccessmemorylocationsrelativetothestacksegmentregister.Justasforthedataregisters,thevaluesheldintheseregisterscanberead,loaded,ormodifiedthroughsoftware.Thisisdonepriortoexecutingtheinstructionthatreferencestheregisterforaddressoffset.Unlikethegeneral-purposedataregister,thepointerandindexregistersareonlyaccessedaswords.

Inordertousetheoffsetaddressinaregister,theinstructionsimplyspecifiestheregisterthatcontainsthevalue.ThevaluesinSPandBPareusedasoffsetsfromthecurrentvalueofSSduringtheexecutionofinstructionsthatinvolvethestacksegmentofmemoryandpermiteasyaccesstostoragelocationsinthestackpartofmemory.ThevalueinSPalwaysrepresentstheoffsetofthenextstacklocationthatistobeaddressed.Thatis,combiningSPwiththevalueinSS(SS:SP)resultsinanphysicaladdressthatpointstothetopofthestack(TOS).

TheBPregister(BasePointer)issimilartotheBXregister.You’llgenerallyusethisregistertoaccessparametersandlocalvariablesinaprocedure.BPmayrepresentanoffsetrelativetotheSS;however,itisusedtoaccessdatawithinthestacksegmentofmemory.Todothis,itisemployedastheoffsetinanaddressingmodecalledthebasedaddressingmode.OneuseofBPistoreferenceparametersthatarepassedtoasubroutinebywayofthestack.Inthiscase,instructionsareincludedinthesubroutinethatusebasedaddressingtoaccessthevaluesofparametersfromthestack.

TheSIandDIregisters(SourceIndexandDestinationIndex)arecalledasindexregisters.Theyhavesomespecialpurposesaswell.Youmayusetheseregistersaspointers(muchliketheBXregister)toindirectlyaccessmemory.Youwillalsousetheseregisterswiththe8086stringinstructionswhenprocessingcharacterstrings.

Normally,theindexregistersareusedtoholdoffsetaddressesforinstructionsthataccessdatastoredinthedatasegmentofmemoryandareautomaticallycombinedwiththevalueintheDSorESregisterduringaddresscalculation.Ininstructionthatinvolvetheindexedaddressing,thesourceindex(SI)registerholdsanoffsetaddressthatidentifiesthelocationofasourceoperand,andthedestinationindex(DI)registerholdsanoffsetforadestinationoperand.BasicallyweuseDS:SIandES:DIcombination.

[ReadingMaterial]TheAXregister(Accumulator)iswheremostarithmeticandlogicalcomputationstakeplace.Althoughyoucandomostarithmeticandlogicaloperationsinotherregisters,itisoftenmoreefficienttousetheAXregisterforsuchcomputations.Also,theaccumulator(AX)isusedautomaticallyinmultiplyanddivideoperationsandininstructionsthataccessI/Oports.TheBXregister(Base)iscommonlyusedtoholdindirectaddresses.

TheCXregister(Count)asitsnameimplies,countsthings.Itisoftenusedtocountoffthenumberofiterationsinalooporspecifythenumberofcharactersinastring.Itcanbeusedasacounterincertainloopinstructions,providingupto65,536(216)passesthroughaloopbeforetermination.ThelowerhalfofCX,the8-bitCLregister,isalsousedasacounterinshift/rotateoperations.TheDXregister(Data)hastwospecialpurposes:itholdstheoverflowfromcertainarithmeticoperations,anditholdsI/Oaddressesasapointerwhenaccessingdataonthe8086I/Obus.Itisalsousedinmultiplyanddividesoperations.

Eachofthesedataregisterscanbeaccessedeitherasawhole(16bits)forworddataoperationsorastwo8-bitregistersforbyte-widedataoperations.AnXaftertheregisterletteridentifiesthereferenceofaregisterasaword;forinstance,the16-bitaccumulatorisreferencedasAX.Similarly,theotherthreewordregistersarereferredtoasBX,CX,andDX.Onotherhand,whenreferencingoneoftheseregistersonabyte-widebasis,followingtheregisternamewiththeletterHorL,respectively,identifiesthehighbyteandlowbyte.

FortheAregister,themostsignificantbyteisreferredtoasAHandtheleastsignificantbyteasAL;theotherbyte-wideregisterpairsareBHandBL,CHandCL,andDHandDL.Whensoftwareplacesanewvalueinonebyteofaregister,forinstanceAL,thevalueintheotherbyte(AH)doesnotchange.Thisabilitytoprocessinformationineitherbytelocationpermitsmoreefficientuseofthelimitedregisterresourcesofthe8086microprocessor.Actually,someofthedataregistersmayalsostoreaddressinformationsuchasabaseaddressoraninput/outputaddress;forexample,BXcouldholda16-bitbaseaddress.

EarlierwepointedoutthatanyofthedataregisterscanbeusedasthesourceordestinationofanoperandduringanarithmeticoperationsuchasADD,oralogicoperationsuchasAND.However,forsomeoperations,anoperandthatistobeprocessedmaybelocatedinmemoryinsteadoftheinternalregister.Inthiscase,anindexaddressisusedtoidentifythelocationoftheoperandinmemory;forexample,stringinstructionsusetheindexregisterstoaccessoperandsinmemory.SIandDI,respectively,arethepointerstothesourceanddestinationlocationsinthememory.Theindexregisterscanalsobesourceordestinationregistersinarithmeticandlogicaloperations.Forexample,aninstructionmayadd2totheoffsetvalueinSItoincrementitsvaluetopointtothenextword-widestoragelocationinmemory.

2.3.2RegistersinBIU

Anothergroupofregistersisthesegmentregisters.The8086microprocessorusesfoursegmentregisterstocontrolallaccessestomemoryorI/O.Thecodesegment(CS)isusedduringinstructionfetches,thedatasegment(DS)ismostoftenusedbydefaultwhenreadingorwritingdata,thestacksegment(SS)isusedduringstackoperationsuchassubroutinecallsandreturns,andtheextrasegment(ES)isusedforanythingtheprogrammerwishes.Allsegmentregistersare16bitslong,andalsoareusedtoconstructa20-bitphysicaladdress.

Asegmentisa64Kbyteblockofmemorystartingonany16-byteboundary.Thus,00000,00010,00020,20000,8CE90,andE0840areallexamplesofvalidsegmentaddresses.Theinformationcontainedinasegmentregisteriscombinedwiththeaddresscontainedinanother16-bitregistertoformtherequired20-bitphysicaladdress.

InFigure2.4,whichshowshowtogenerateamemoryphysicaladdress,thecodesegmentregistercontainsA000Handtheinstructionpointercontains5F00H.Theprocessorformsthe20-bitaddressA5F00Hinthefollowingways:first,thedatainthecodesegmentregisterisshifted4bitstotheleft,whichhastheeffectofturningA000HintoA0000H.Thenthecontentsoftheinstructionpointerareadded,finallygivingA5F00H.Figure2.4Generatinga20-bitaddressinrealmode

Therearetwospecialpurposeregistersonthe8086microprocessor:theinstructionpointer(IP)andtheflagsregister(FR).Youdonotaccesstheseregistersthesamewayyouaccesstheother8086registers.Instead,themicroprocessorgenerallymanipulatestheseregistersdirectly.

TheIPregistercontainstheaddressofthecurrentexecutioninstruction.Inotherwords,itidentifiesthelocationofthenextwordofinstructioncodetobefetchedfromthecurrentcodesegmentofmemory.

Thisisa16-bitregisterwhichprovidesapointerintothecurrentcodesegment(16bitsletstheprogrammerselectanyoneof65,536differentmemorylocations),anditissimilartoaprogramcounter;however,itcontainstheoffsetofthenextwordofinstructioncodeinsteadofitsactualaddress.ThisisbecauseIPandCSareboth16bitsinlength,buta20-bitaddressisneededtoaccessmemory.Internaltothe8086,theoffsetinIPiscombinedwiththecurrentvalueintheCSregistertogeneratetheactualaddressoftheinstructioncode.Therefore,thevalueoftheaddressforthenextcodeaccessisoftendenotedasCS:IP.

[ReadingMaterial]IthasbeendiscussedthathowtheCSregisterandIPregistergeneratetheinstructionaddress,butheregivessomefurtheroperationexplanations.

Duringnormaloperations,the8086fetchesinstructionsfromthecodesegmentofmemory,storestheminitsinstructionqueue,andexecutesthemoneaftertheother.Everytimeawordofcodeisfetchedfrommemory,the8086updatesthevalueinIPsuchthatitpointstothefirstbyteofthenextsequentialwordofcode—thatis,IPisincrementedby2.Actually,the8086prefetchesuptosixbytesofinstructioncodeintoitsinternalcodequeueandholdthemtherewaitingforexecution.

Afteraninstructionisreadfromtheoutputoftheinstructionqueue,itisdecoded;ifnecessary,operandsarereadfromeitherthedatasegmentofmemoryorinternalregisters.Next,theoperationspecifiedintheinstructionisperformedontheoperandsandtheresultiswrittenbacktoeitheraninternalregisterorastoragelocationinmemory.The8086isnowreadytoexecutethenextinstructioninthecodequeue.

ExecutinganinstructionthatloadsanewvalueintotheCSregisterchangestheactivecodesegment;thus,any64Kbytesegmentofmemorycanbeusedtostoretheinstructioncode.

2.3.3FlagsRegister

Thestatusregister,alsocalledtheflagsregister,isanother16-bitregisterwithinthe8086.Unliketheotherregistersholdingeightorsixteen-bitvaluesonthe8086,theflagsregisterissimplyacollectionofonebitvaluewhichhelpdeterminethecurrentstateoftheprocessor.Althoughtheflagsregisteris16bitswide,the8086usesonlynineofthosebits.Figure2.5showstheorganizationofthisregister.Bits1,3,5,and12~15areundefined.Figure2.5TheorganizationofFlagRegister

Theflagsaredividedintotwogroups:statusflagsandcontrolflags.Sixofthesebitsrepresentstatusflags:theCarryFlag(CF),ParityFlag(PF),AuxiliaryFlag(AF),ZeroFlag(ZF),SignFlag(SF),andOverflowFlag(OF),whichwecall“CAPSZO”.Thelogicstatesofthesestatusflagsindicateconditionsthatareproducedastheresultofexecutinganinstruction—thatis,afterexecutionaninstruction,suchasADD,specificflagbitsarereset(logic0)orset(logic1)basedontheresultthatisproduced.

Letussummarizetheoperationoftheseflags:

(1)?Thecarryflag(CF—Bit0):CFissetifthereisacarry-outoraborrow-inforthemostsignificantbitoftheresultduringtheexecutionofaninstruction.Otherwise,CFisreset.

(2)?Theparityflag(PF—Bit2):PFissetiftheresultproducedbytheinstructionhasevenparity—thatis,ifitcontainsanevennumberofbitsatthe1logiclevel.Ifparityisodd,PFisreset.

(3)?Theauxiliarycarryflag(AF—Bit4):AFissetifthereisacarry-outfromthelownibbleintothehighnibbleoraborrow-infromthehighnibbleintothelownibbleofthelowbyteina16-bitword.Otherwise.AFisreset.

(4)?Thezeroflag(ZF—Bit6):ZFissetiftheresultproducedbyaninstructioniszero.Otherwise,ZFisreset.

(5)?Thesignflag(SF—Bit7):TheMSBoftheresultiscopiedintoSF.Thus,SFissetiftheresultisanegativenumberorresetifitispositive.

(6)?Theoverflowflag(OF—Bit11):WhenOFisset,itindicatesthatthesignedresultisoutofrange.Iftheresultisnotoutofrange,OFremainsreset.

[ReadingMaterial]Forexample,atthecompletionofexecutionofabyte-additioninstruction,thecarryflag(CF)couldbesettoindicatethatthesumoftheoperandscausedacarry-outcondition.Theauxiliarycarryflag(AF)couldalsosetduetotheexecutionoftheinstruction.Thisdependsonwhetherornotacarry-outoccurredfromtheleastsignificantnibbletothemostsignificantnibblewhenthebyteoperandsareadded.Thesignflag(SF)isalsoaffected,anditreflectsthelogicleveloftheMSBoftheresult.Theoverflowflag(OF)issetifthereisacarry-outofthesignbit,butnocarryintothesignbit(anindicationofoverflow).

Oftheseflags,zero,carry,sign,andoverflowareusedbytheprogrammersallthetime.The8086providesinstructionswithinitsinstructionsetthatareabletousetheseflagstoalterthesequenceinwhichtheprogramisexecuted;forinstance,ajumptoanotherpartoftheprogramcouldbeconditionallyinitiatedbytestingforZFequaltologic.Thisoperationiscalledjumponzero.

Theotherthreeimplementedflagbits—theDirectionFlag(DF),theInterruptenableFlag(IF),andTrapFlag(TF),whichwecall“IDT”

—arecontrolflags.Thesethreeflagsprovidecontrolfunctionsofthe8086asfollows:

(7)?Thetrapflag(TF—Bit8):IfTFisset,the8086goesintothesingle-stepmodeofoperation.Wheninthesingle-stepmode,itexecutesaninstructionandthenjumpstoaspecialserviceroutinethatmaydeterminetheeffectofexecutingtheinstruction.Thistypeofoperationisveryusefulfordebuggingprogram.

(8)?Theinterruptflag(IF—Bit9):Forthe8086torecognizemaskableinterruptrequestsatitsinterrupt(INT)INPUT,theIFflagmustbeset.WhenIFisreset,requestsatINTareignoredandthemaskableinterruptinterfaceisdisabled.

(9)?Thedirectionflag(DF—Bit10):ThelogiclevelofDFdeterminesthedirectioninwhichstringoperationswilloccur.Whenset,thestringinstructionautomaticallydecrementstheaddress;therefore,thestringdatatransfersproceedfromhighaddresstolowaddress.Ontheotherhand,resettingDFcausethestringaddresstobeincremented–thatis,datatransfersproceedfromlowaddresstohighaddress.

Theinstructionsetofthe8086includesinstructionsforsaving,loading,ormanipulatingtheflags;forinstance,specialinstructionsareprovidedtopermitusersoftwaretosetorresetTF,DF,andIFatanypointintheprogram(e.g.,justpriortothebeginningofastringoperation,DFisresetsothatthestringaddressautomaticallyincrements).

[ReadingMaterial]Inthestatusregister,theoverflowflagiseasytousemistakenly.Itwillbediscussedasanemphasishere.First,itisveryimportanttoknowwhatisoverflow.Inthelastchapter,ithasbeenintroducedthathowtoindicateavalueasacomplementcode.Therangefor8-bitvalueis+127~-128,andtherangefor16-bitvalueis+32767~-32768.Ifthevaluegoesbeyondthisrange,overflowwillhappen.Asamatteroffact,itpresentstheresultiswrong.Seetheexamplebelow:

3AH+7H=B6H,thatis58+124=182indecimalsystem.Theresultof182isoutof-128~+127,soOF=1;B6His-74asacomplementcode.Obviously,theresultiswrong.

Infact,thereisashortcuttojudgewhethertheresultisoverflowornot.Whentwovalueswiththesamesignaddedandtheresulthasthecontrarysigntotheoriginalvalue,overflowhappens.Inthiscase,theresultisobviouslywrong.Inothercases,overflowwouldneverhappen