數(shù)字電路第六章課件

Chapter6

CombinationalLogicDesignPractices組合邏輯電路ChapterOutlineDocumentationStandardsDigitalCircuitTimingandPropagationdelayCombinationalLogicDesignStructures

:

-Decoders

-Encoders

-Three-StateBuffers

-Multiplexers

-EXCLUSIVEORGatesandParityCircuits

-Comparators

-Adders/Subtractors

-ArithmeticLogicUnits(ALUs)6.1DocumentationStandard

(文檔標(biāo)準(zhǔn))Documentationofadigitalsystemshouldprovidethenecessaryinformationforbuilding,testing,operating,andmaintainingthesystem.Specification:DescriptionofInterfaceandFunction

(說明書：接口及功能描述)BlockDiagram:System’sMajorFunctionModuleandtheirBasicInterconnections

(方框圖：主要功能模塊及其互聯(lián)P345圖6-1)SchematicDiagram:showingallthecomponents,theirtypes,andallinterconnections

(原理圖（P360圖6-17）)BlockDiagramSchematicDiagramHierarchichalschematicstructureDocumentationStandard

(文檔標(biāo)準(zhǔn))TimingDiagram:showingthelogicsignalsasafunctionoftime

(定時(shí)圖（P363圖6-19）)StructureLogicDeviceDescription:showingtheoperationofthestructures

(結(jié)構(gòu)化邏輯器件描述)CircuitDescription:Explainshowthecircuitworksinternally.

(電路描述：解釋電路內(nèi)部如何工作)“HierarchicalDesign”GateSymbols(門的符號(hào))&≥11DeMorganequivalentsymbols

(等效門符號(hào)（摩根定理）)Inverter(反相器)Buffer(緩沖器)Whichsymboltouse?－dependsonsignalnamesandactivelevels.SignalNamesandActiveLevels

(信號(hào)名和有效電平)Signalname:adescriptivealphanumericlabelforeachinput/outputsignal.Inrealsystem,well-chosennamesconveyinformationtoreadersEachsignalnameshouldhaveanactive-levelassociatedwithit.

(有效電平)ActiveHigh

（高電平有效）ActiveLow

（低電平有效）READYREQUESTGOREADY_LREQUEST_LGO_LSignalNameandActiveLevels

(信號(hào)名和有效電平)Thesignalisasserted

whenitisinitsactivelevelandnegated(ordeasserted)whenitsnotinitsactivelevel.AnInversionBubbletoIndicateanActive-LowPin(有反相圈的引腳表示低電平有效)Activelowsignalhasasuffixof_L

aspartofthevariablename.SignalNameandActiveLevels

(信號(hào)名和有效電平)ENABLEDOMYTHING……………ENABLEDOMYTHING……………

AND,OR,andalarge-scalelogicelementhaveactive-highinputsandoutputsThesameelementswithactive-lowinputsandoutputsGivenLogicFunctionasOccurringinsidethatsymbolicoutline.(給定邏輯功能只在符號(hào)框的內(nèi)部發(fā)生)Bubble-to-BubbleLogicDesign

(“圈到圈”的邏輯設(shè)計(jì))Purpose:TomakeiteasytounderstandthefunctionoftheLogiccircuitbychoosingappropriatelogicsymbolsandsignalnamesincludingactive-leveldesignators.

ERRORFAIL_LOVERFLOW_L

ERRORFAIL_LOVERFLOW_LBubble-to-BubbleLogicDesign

(“圈到圈”的邏輯設(shè)計(jì))AASELBDATAAASELBADATA_LBDATA_LDATA6.2CircuitTiming(電路定時(shí))PropagationDelay(傳播延遲)--ASignalPathastheTimethatittakesforaChangeattheInputtoProduceaChangeattheOutputofthePath(信號(hào)通路輸入端的變化引起輸出端變化所需的時(shí)間)tpHLandtpLHMaybeDifferentPropagationDelayTimingAnalysis:Worst-CaseDelay(定時(shí)分析：取最壞情況延遲)MaximumDelay(最大延遲)TypicalDelay(典型延遲)MinimumDelay(最小延遲)’08’08’04’32’32’32P366表6-2152022226.2CircuitTiming(電路定時(shí))TimingDiagram定時(shí)圖（時(shí)序圖）GOREADYDAT6.2CircuitTiming(電路定時(shí))CausalityandPropagationDelay(因果性和傳播延遲）GOREADYDATtDATtDATtRDYtRDYGOREADYDAT6.2CircuitTiming(電路定時(shí))TimingDiagram定時(shí)圖（時(shí)序圖）MinimumandMaximumDelay(最小和最大延遲）GOREADYDATtRDYmintRDYmax6.2CircuitTiming(電路定時(shí))CertainandUncertainTransitions

(確切的和不確切的轉(zhuǎn)換）WRITE_LDATAOUTDATAINtOUTmaxtsetuptOUTminCommonlyUsedMSICombinationalLogicDeviceDecoders(譯碼器)Encoders(編碼器)Multiplexers(多路復(fù)用器)ParityCircuits(奇偶校驗(yàn))Comparators(比較器)Adders(加法器)DecoderandEncoder

(譯碼器和編碼器)Multiple-Input,Multiple-OutputLogicCircuit(多輸入、多輸出電路)EnableInputs(使能輸入)(輸入編碼)(輸出編碼)Map映射EnableInputsmustbeAssertedtoperformNormalMappingFunction(使能輸入有效才能實(shí)現(xiàn)正常映射功能)InputCodeWordOutputCodeWordDecoder（譯碼器）

NormallyOutputCodehasMorebitsthanitsInputCode

(一般來說，輸出編碼比輸入編碼位數(shù)多)Encoder（編碼器）

OutputCodehasFewerbitsthanitsInputCodecalledanEncoder(輸出編碼比輸入編碼位數(shù)少，則常稱為編碼器)DecoderandEncoder

(譯碼器和編碼器)MostCommonlyUsedCase使能輸入編碼輸出編碼Map映射Decoder（譯碼器）Encoder（編碼器）N-BitBinaryCode(n位二進(jìn)制碼)2n

中取1碼使能輸入編碼輸出編碼Map映射2n中取1碼n位二進(jìn)制碼(1-out-of2n)6.4Decoder（譯碼器）BinaryDecoder

(二進(jìn)制譯碼器)1.

2-to-4Decoder2-to-4DecoderY0Y1Y2Y3I0I1EN

0XX00001000001101001011001001111000InputsENI1I2OutputsY3Y2Y1Y0(2-4二進(jìn)制譯碼器真值表)TruthTablefora2-to-4BinaryDecoderY0=EN·(I1’·I2’)Y1=EN·(I1’·I2)Y2=EN·(I1·I2’)Y3=EN·(I1·I2)Yi=EN·miDecoder（譯碼器）

0XX00001000001101001011001001111000InputsENI1I2OutputsY3Y2Y1Y0(2-4二進(jìn)制譯碼器真值表)TruthTablefora2-to-4BinaryDecoder2-to-4DecoderThe74x139Dual2-to-4Decoder

(雙2-4譯碼器74x139)1XX1111

00011100011101

0101011

0110111InputsGBAOutputs

Y3_LY2_LY1_LY0_LTruthTableforOne-halfofa74x139Dual2-to-4Decoder74x1391Y01Y11Y21Y31G1A1B2Y02Y12Y22Y32G2A2B12315141345671211109LogicSymbolsforLarge-ScaleElementY0Y1Y2Y3GAB1/274x139Y0Y1Y2Y3GAB1/274x139Y0Y1Y2Y3GAB1/274x139G_LABY0_LY1_LY2_LY3_L00000001000000100000010000001000000100000010000001000000100000003-to-8DecoderI2I1I0Y0Y1Y7Yi=EN·mi1111111011111101111110111111011111101111110111111011111101111111Decoder（譯碼器）000001010011100101110111I2I1I0Y7Y1Y0Y2Y3Y4Y5Y6(3-8二進(jìn)制譯碼器真值表)TruthTablefora3-to-8BinaryDecoder2.

3-to-8DecoderThe74x1383-to-8Decoder

(3-8譯碼器74x138)低位高位Y0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_LENG1G2A_LG2B_LENEN=G1·G2A·G2B=G1·G2A_L’·G2B_L’Yi=EN·miYi_L=Yi’=(EN·mi

)’ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EnableY6_L=(C·B·A’)’=m6’Logicdiagramforthe74x138用74x138設(shè)計(jì)4-16譯碼器CascadingBinaryDecoders

N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_L思路：16個(gè)輸出需要

片74x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2任何時(shí)刻只有一片在工作。4個(gè)輸入中，哪些位控制片選哪些位控制輸入Consider:Howtomakea5-to-32Decoderwith3-to-8Decoder?32個(gè)輸出需要多少片74x138？控制任何時(shí)刻只有一片工作 ——利用使能端5個(gè)輸入的低3位控制輸入5個(gè)輸入的高2位控制片選 ——利用2-4譯碼器P391圖6-37UsedecoderandGatestorealizelogicfunctionF=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5)Binarydecoder：Yi=EN·mi

Enableinputsareasserted:

Yi=mi

Yi_L=Yi’=mi’=MiABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138UsedecoderandGatestorealizelogicfunctionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)當(dāng)使能端有效時(shí)Yi=miUsedecoderandGatestorealizelogicfunctionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(X,Y,Z)(0,3,6,7)=M1·

M2·M4·M5=m1’

·

m2’

·m4’

·m5’F=(X,Y,Z)(1,2,4,5)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFBCDDecoder(二－十進(jìn)制譯碼器)Inputs:4-bitBCDcodeOutputs:1-out-of10CodeY0Y9I0I1I2I3多余的6個(gè)狀態(tài)如何處理？輸出均無效：拒絕“翻譯”作為任意項(xiàng)處理——電路內(nèi)部結(jié)構(gòu)簡單二-十進(jìn)制譯碼器00000001001000110100010101100111100010011010101111001101111011110111111111101111111111011111111110111111111101111111111011111111110111111111101111111111011111111110111111111111111111111111111111111111111111111111111111111111I3

I2

I1

I00123456789Y0_L

Y9_L偽碼Don’tcareSeven-SegmentDecoders

(七段顯示譯碼器)abcdefgdpNormallyuse

：Light-EmittingDiodes（LED,半導(dǎo)體數(shù)碼管）Liquid-CrystalDisplay（LCD,液晶數(shù)碼管）LED顯示器件LCD顯示器件LEDabcdefgdp公共陰極abcdefgdp公共陽極點(diǎn)陣型顯示器筆劃段型顯示器Inputcode:4-bitBCD輸入信號(hào)：BCD碼（用A3A2A1A0表示）OutputCode:Seven-SegmentCode輸出：七段碼（的驅(qū)動(dòng)信號(hào)）a~g1---On，0---Offabcdefg111111011011010011111Seven-SegmentDecoders74LS48顯示字型與輸入的對(duì)應(yīng)關(guān)系00000001001000110100010101100111100010011010101111001101111011111111110011000011011011111001011001110110110011111111000011111111110011000110100110010100011100101100011110000000A3

A2

A1

A0abcdefg0123456789101112131415A3A2A1A000

01

11

10000111101001100011000111a七段顯示譯碼器的真值表Ya=A3A2A1A0+A3A1+A2A0Yb=A3A1+A2A1A0+A2A1A0KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段顯示譯碼器的卡諾圖)Yc=A3A2+A2A1A0Yd=A2A1A0+A2A1A0+A2A1A0KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段顯示譯碼器的卡諾圖)KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段顯示譯碼器的卡諾圖)Ye=A2A1+A0Yf=A3A2A0+A1A0+A2A1KarnaughMapsforBCD-Seven-SegmentDecoder

(BCD-

七段顯示譯碼器的卡諾圖)Yg=A3A2A1+A2A1A0DesignBCD-Seven-SegmentDecoder邏輯抽象，得到真值表輸入信號(hào)：BCD碼（A3A2A1A0）輸出：七段碼（的驅(qū)動(dòng)信號(hào)）a~g1表示亮，0表示滅選擇器件類型采用基本門電路實(shí)現(xiàn)，利用卡諾圖化簡采用二進(jìn)制譯碼器實(shí)現(xiàn)，變換為標(biāo)準(zhǔn)和形式電路處理，得到電路圖abcdefg6.5Encoder（編碼器）BinaryEncoderA0A1A2I0I1I710000000000010000000010010000001000010000011000010001000000010010100000010110000000011112nInputsnOutputsI0I1I2I3I4I5I6I7A2A1A0(3位二進(jìn)制編碼器的真值表)TruthTablefora8-to-3EncoderGuarantee:

---oneandonlyoneinputwillbeassertedatatime(任何時(shí)刻只有一個(gè)輸入端有效。)1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二進(jìn)制編碼器的真值表)Encoder（編碼器）TruthTablefora8-to-3EncoderthisistheexactoppositeofadecoderA0=I1+I3+I5+I7A1=I2+I3+I6+I7A2=I4+I5+I6+I7Howtodealwithmultiplerequests?---morethanOneInputsareassertedPriority（優(yōu)先級(jí)）1000000000001000000001001000000100001000001100001000100000001001010000001011000000001111I0I1I2I3I4I5I6I7A2A1A0(3位二進(jìn)制編碼器的真值表)Encoder（編碼器）TruthTablefora8-to-3EncoderA2A1A0IDLEI7I6I5I4I3I2I1I0Inordertowritelogicequationsforthepriorityencoder’soutputswefirstdefineeightintermediatevariablesH0-H7Highest-Priority(數(shù)大優(yōu)先)PriorityEncoder(優(yōu)先編碼器)H7=I7H6=I6·I7’H5=I5·I6’·I7’…H0=I0·I1’·I2’·…·I6’·I7’A2A1A0IDLEI7I6I5I4I3I2I1I0Inordertowritelogicequationsforthepriorityencoder’soutputswefirstdefineeightintermediatevariablesH0-H7Highest-Priority(數(shù)大優(yōu)先)PriorityEncoder(優(yōu)先編碼器)A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7TheIDLEOutputisassertedifNoInputsareasserted.

IDLE=I0’·I1’·…·I6’·I7’輸入輸出EI_L有效沒有輸入請求EO_L有效EnableInput有輸入請求EI_L有效GS_L有效A2A1A0EI74x148I7I6I5I4I3I2I1I0GSEO54321131211106791415使能輸出，用于級(jí)聯(lián)

EO選通輸出GSThe74x148PriorityEncoderA2A1A0GSEOEII7I0A2A1A0GSEOEII7I0Q15_LQ8_LQ7_LQ0_LY0Y1Y2Y3GS2個(gè)74x148級(jí)聯(lián)為16-4優(yōu)先編碼器輸入：由864，需8片74x148每片優(yōu)先級(jí)不同（怎樣實(shí)現(xiàn)？）保證高位無輸入時(shí)，次高位才工作——高位芯片的EO端接次高位芯片的EI端用8-3優(yōu)先編碼器74x148級(jí)聯(lián)為64-6優(yōu)先編碼器A2A1A0GSEOEII7I0片間優(yōu)先級(jí)的編碼——利用第9片74x148

每片的GS端接到第9片的輸入端

第9片的輸出作為高3位（RA5～RA3）片內(nèi)優(yōu)先級(jí)片間優(yōu)先級(jí)輸出：6位低3位高3位8片輸出A2～A0通過或門作為最終輸出的低3位RA2～RA0分析判定優(yōu)先級(jí)電路：（利用74x148）

8個(gè)___電平有效輸入I0_L～I(xiàn)7_L，_____的優(yōu)先級(jí)最高地址輸出A2～A0，____電平有效若輸出AVALID高電平有效，則表示_______________A2A1A0GSEOEI74x148I7I0I0_LI7_LA2A1A0AVALID低I0_L至少有一個(gè)輸入有效高P514題6.53設(shè)計(jì)優(yōu)先級(jí)電路：（利用74x148）8個(gè)輸入I0～I(xiàn)7高電平有效，I7優(yōu)先級(jí)最高地址輸出A2～A0，高電平有效如果沒有輸入有效，輸出IDLE有效I7I0A2A1A0IDLEA2A1A0GSEOEII7I074x148P514題6.526.6Three-StateDevices

(三態(tài)器件)Three-StateBuffer(Three-StateDriver)三態(tài)緩沖器（三態(tài)驅(qū)動(dòng)器）ThreeStates: ActiveHigh(1)，ActiveLow(0),Hi-Z

Variousthree-statebuffersThree-StateDevices

Three-StateDeviceallowMultipleSourcestoShareaSingle“PartyLine”AslongasOnlyOnedevice“talk”ontheLineatatime

（三態(tài)器件允許多個(gè)信號(hào)源共享單個(gè)“同線”，條件是每次只有一個(gè)器件工作）

(Figure6-52)TypicalThree-StateDevicesareDesignedSothattheygointotheHi-ZstateFasterthantheycomeoutoftheHi-Zstate.（對(duì)典型的三態(tài)器件，進(jìn)入高阻態(tài)比離開高阻態(tài)的時(shí)間快）ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138EN1EN2_LEN3_LSSRC0SSRC1SSRC2fighting（沖突）利用使能端進(jìn)行時(shí)序控制三態(tài)器件允許信號(hào)共享單個(gè)“同線”（partyline）典型的三態(tài)器件，進(jìn)入高阻態(tài)比離開高阻態(tài)快P0P1P7SDATAEN1EN2_L,EN3_Lmax(tpLZmax,tpHZmax)min(tpZLmin,tpZHmin)SSRC[2:0]01237SDATAP0P1P2P3P7DeadTime(截止時(shí)間)StandardSSIandMSIThree-StateBuffer

(標(biāo)準(zhǔn)SSI和MSI三態(tài)緩沖器)The74x541Octalthree-statebufferA1A2A3A4A5A6A7A8G1G2Y1Y2Y3Y4Y5Y6Y7Y874x541A1A8G1G2Y1Y874x541DB[0:7]A1A8G1G2Y1Y874x541NotationofDataBus（數(shù)據(jù)總線的表示法）A1B1DIRTransferDatainEitherDirectionsByUsingThree-StateTransceiver(利用三態(tài)緩沖器實(shí)現(xiàn)數(shù)據(jù)雙向傳送)BusTransceiver(總線收發(fā))DIRG_L6.7Multiplexer（多路復(fù)用器）DigitalSwitch,Multi-Switch,DataSelector(又稱數(shù)據(jù)開關(guān)、多路開關(guān)、數(shù)據(jù)選擇器)（縮寫：MUX）UnderSelectControllingSignals,SelectOneoftheMulti-InputstotheOutput

(在選擇控制信號(hào)的作用下，從多個(gè)輸入數(shù)據(jù)中選擇其中一個(gè)作為輸出。)MultiplexerENSELD0Dn-1YEnable使能Select選擇n個(gè)1位數(shù)據(jù)源數(shù)據(jù)輸出（1位）ENSELD0Dn-1YEnable(使能)Select(選擇)NDataSources(n個(gè)b位數(shù)據(jù)源)DataOutput(數(shù)據(jù)輸出)（b位）EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8輸入1位多路復(fù)用器)TruthTablefora74x1518-Input,1-bitMultiplexerENABCD0D1D2D3D4D5D6D7YY74x15143211514131211109756EN_LCBAYY_L1XXX0000000100100011010001010110011101D0D0’D1D1’D2D2’D3D3’D4D4’D5D5’D6D6’D7D7’(8輸入1位多路復(fù)用器)TruthTablefora74x1518-Input,1-bitMultiplexerHowtogetalogicequationforaMUXoutput?輸入G_LS1X000100001A2A3A4A1B2B3B4B(2輸入4位多路復(fù)用器)TruthTablefora74x157輸出1Y2Y3Y4Y2-Input,4-bitMultiplexerGS1A1B2A2B3A3B4A4B1Y2Y3Y4Y74x157235611101413115479121G_L2G_LBA1Y2Y11XX000000010010001101000101011001111000100110101011

001C02C01C12C11C22C21C32C31C001C101C201C30

02C002C102C202C3(4輸入2位多路復(fù)用器74x153真值表)4-Input,2-bitMultiplexerTruthTablefora74x153AB1C01C11C21C31Y7417101112132C02C12C22C32G152Y9雙4選1ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingBit(擴(kuò)展位)HowtoRealize8-Input,16-bitMultiplexer?From8-Input,1-bitto8-Input,16-bit

(由8輸入1位8輸入16位)Need1674x151,EachChipProcess1-bit

(需要16片74x151，每片處理輸入輸出中的1位)ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingBit(擴(kuò)展位)Select-InputsConnecttoC,B,AofEachChip(選擇端連接到每片的C,B,A)Note:TheFanoutAbilityofSelectfield

(注意：選擇端的扇出能力)（驅(qū)動(dòng)16個(gè)負(fù)載）ENYYABCD0D7ExpandingInputs(擴(kuò)展數(shù)據(jù)輸入端的數(shù)目)Howtorealize32-Input,1-bitMultiplexer

(如何實(shí)現(xiàn)32輸入，1位多路復(fù)用器？)Inputsfrom8to32,Need4chips

(數(shù)據(jù)輸入由832，需4片)HowtocontrolSelectInputs-----ByHighbitplusLowbit.

(如何控制選擇輸入端？——分為：高位＋低位)ENYYABCD0D7ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)ExpandingInputs(擴(kuò)展數(shù)據(jù)輸入端的數(shù)目)如何實(shí)現(xiàn)32輸入，1位多路復(fù)用器？HighBitsplusDecoderasSelect

(高位＋譯碼器進(jìn)行片選)LowBitsConnecttoC,B,AofeachChip

(低位接到每片的C,B,A)OutputUsingORGate(4片輸出用或門得最終輸出)ENYYABCD0D7ExpandingMultiplexers

(擴(kuò)展多路復(fù)用器)Dual4-to-1Multiplexerto8-to-1MultiplexerD0D1D2D3D4D5D6D7A0A1A2YAB1C01C11C21C31Y7417101112132C02C12C22C32G152Y9UseMUXtodesigncombinationalcircuitWhenenableinputisasserted，CanonicsumENABCD0D1D2D3D4D5D6D7YY74x151CBAVCCF實(shí)現(xiàn)邏輯函數(shù)F=(A,B,C)(0,1,3,7)對(duì)比Ex：Use4-to-1MUXtorealize:解：觀察邏輯邏輯函數(shù)表達(dá)式，每個(gè)與項(xiàng)都包含了變量A和C，因此用A、C作數(shù)據(jù)選擇器的選擇輸入端，變換邏輯函數(shù)表達(dá)式如下MUXD0D1D2D3A0A1ENY對(duì)比：四選一MUX表達(dá)式令A(yù)1=A，A0=CEN’=0，D0=0，D1=D，D2=B，D3=B’YZWX00

01

11

10000111101111111YWX000111100110ZZZZZ’0Use74x151torealizethefunction:F=(W,X,Y,Z)(0,1,3,7,9,13,14)降維：由4維3維ENABCD0D1D2D3D4D5D6D7YY74x151VCCYXWFZ利用74x151實(shí)現(xiàn)F=(W,X,Y,Z)(0,1,3,7,9,13,14)0

2

6

41

3

7

5YWX000111100110ZZZZZ’0說明：用具有n位地址輸入端的多路復(fù)用器，可以產(chǎn)生任何形式的輸入變量數(shù)不大于n+1的組合邏輯函數(shù)。UseMUXtorealizelogicfunction

——Karnughmaps1、將卡諾圖畫成與數(shù)據(jù)選擇器相適應(yīng)的形式。也就是說，所使用的數(shù)據(jù)選擇器有幾個(gè)地址選擇輸入端，邏輯函數(shù)卡諾圖的某一邊就應(yīng)有幾個(gè)變量，且就將這幾個(gè)變量作為數(shù)據(jù)選擇器的地址選擇碼

2、將要實(shí)現(xiàn)的邏輯函數(shù)填入卡諾圖并在卡諾圖上畫圈。順著地址選擇碼的方向畫圈

3、求輸入數(shù)據(jù)端的邏輯函數(shù)表達(dá)式。4、根據(jù)選擇端和輸入數(shù)據(jù)端的邏輯函數(shù)表達(dá)式，畫出用數(shù)據(jù)選擇器實(shí)現(xiàn)的電路。Ex.Use4-to-1MUX74x153

and8-to-1MUX74x151torealizethefunctionrespectively.F(A,B,C,D)=∑m(0,1,5,6,7,9,10,13,15)+∑φ(4,8,11,12)

Solution1:4-to-1MUX74x153AB00011110000111100111101Φ11011CDΦ

ΦΦD0=C’

D1=1D2=1D3=DEN

0

1

2

3

Y1

EN

0

1

2

3

Y2

C_L

1

1

D

MUXB

A

0

FA1A0Solution2:8-to-1MUX74x151EN0123Y456711A0MUXDC0B01A_L1FA0A1A2110111101100111011ABCD010000010110101100Φ11ΦΦΦDemultiplexer（多路分配器）Routethebusdatatooneofmdestinations

(把輸入數(shù)據(jù)送到m個(gè)目的地之一)多路復(fù)用器SRCASRCBSRCZ多路分配器BUSDSTADSTBDSTZSRCSELDSTSELDST:destinationSRC:sourceSEL:selectAbinarydecoderwithanenableinputcanbeusedasademultiplexer(利用帶使能端的二進(jìn)制譯碼器作為多路分配器)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138DST0_LDST7_LEN_LDSTSEL0DSTSEL1DSTSEL2地址選擇——Enableinputisconnectedtothedataline

(利用使能端作為數(shù)據(jù)輸入端)數(shù)據(jù)輸入SRCEN_LCanyoutellthecircuitfunction？6.8ParityCircuit

(奇偶校驗(yàn)電路)Odd-ParityCircuit（奇校驗(yàn)電路）Outputis1ifanoddnumberofitsinputsare1.

(如果輸入有奇數(shù)個(gè)1，則輸出為1。)Even-ParityCircuit（偶校驗(yàn)電路）Outputis1ifanevennumberofitsinputsare1.

(如果輸入有偶數(shù)個(gè)1，則輸出為1。)回顧：用什么可以判斷1的個(gè)數(shù)？？？ParityCircuitA0A1…An=

1變量為1的個(gè)數(shù)是奇數(shù)0變量為1的個(gè)數(shù)是偶數(shù)Outputofodd-paritycircuitisinverted,wegetaneven-paritycircuit.(奇校驗(yàn)電路的輸出反相就得到偶校驗(yàn)電路)NXORgatesmaybecascadedtoformacircuitwithn+1inputsandasingleoutput.(n個(gè)異或門級(jí)聯(lián)，形成具有n+1個(gè)輸入和單一輸出的電路)

ReviewofXORANDXNORAB=(A⊙B)’AB’=A⊙BAB=A⊙B’Anytwosignals(inputsoroutput)ofanXORorXNORgatemaybecomplementedwithoutchangingtheresultinglogicfunction.(Figure6-69)(對(duì)于異或門、同或門的任何2個(gè)信號(hào)（輸入或輸出）都可以取反，而不改變結(jié)果的邏輯功能)F=ABABFABFABABFFF=A’B’F=(A’B)’F=(AB’)’I1I2I3I4INODDDaisy-ChainConnection

(菊花鏈?zhǔn)竭B接)I1I2I3I4IMINODDTreeStructure

(樹狀連接)CascadingXORGates(Figure6-70）9-bitOdd/EvenParityGenerator74x280

(9位奇偶校驗(yàn)發(fā)生器74x280)ABCDEFGHIEVENODD74x280Figure6-71Parity-CheckingApplications用于檢測代碼在傳輸和存儲(chǔ)過程中是否出現(xiàn)差錯(cuò)AEVENODD74x280HIAEVENODD74x280HI發(fā)端收端DB[0:7]DB[0:7]ERROR發(fā)端保證有偶數(shù)個(gè)1收端ODD有效表示出錯(cuò)奇數(shù)EVEN6.9Comparator（比較器）ComparetwoBinarywordsandindicatewhethertheyareequalComparator:CheckiftwoBinarywordsareequal

(等值比較器：檢驗(yàn)數(shù)值是否相等)MagnitudeComparator:Comparetheirmagnitude(Greaterthan,Equal,Lessthan)

(數(shù)值比較器：比較數(shù)值的大?。?gt;,=,<）)ComparatorHowtobuilda1-bitComparator?

(如何構(gòu)造1位等值比較器？？)——UseXOR(XNOR)ABDIFFABEQDIFF:differentEQ:equalDIFFA0B0A1B1A2B2A3B3給出足夠的異或門和寬度足夠的或門，可以搭建任意輸入位數(shù)的等值比較器。HowtoBuildaN-bitComparator?必須每位都相等——并行比較——串行比較4位等值比較器Iterativecircuit（迭代電路）Iterative：重復(fù)的,反復(fù)的,[數(shù)]迭代的PICICOPOPICICOPOPICICOPOC0C1C2CnPO0PO1POn-1Primaryoutputs主輸出PI0PI1PIn-1Primaryinputs主輸入Boundaryinputs邊界輸入Boundaryoutputs邊界輸出Cascadingoutput級(jí)聯(lián)輸出AnIterativeComparatorXYCMPEQIEQOX0Y0X1Y1XN-1YN-1EQ1EQ2EQNEQN-11XYCMPEQIEQOXYCMPEQIEQO——每位串行比較ABEQ迭代的方法可能節(jié)省費(fèi)用，但速度慢用于級(jí)聯(lián)的輸入Figure6-77EQOEQIEQ_LABLT_LGT_L1-BitMagnitudeComparator

(一位數(shù)值比較器)①A>B（A=1,B=0）則A·B’=1可作為輸出信號(hào)②A<B（A=0,B=1）則A’·B=1可作為輸出信號(hào)③A=B，則A⊙B=1，可作為輸出信號(hào)輸出低電平有效EQ_L=A·B’+A’·B=AB=(A⊙B)’LT:LessThanEQ:EqualGT:GreaterThan(A’·B)’(A·B’)’n-BitMagnitudeComparator

(多位數(shù)值比較器)A(A3A2A1A0)

和

B(B3B2B1B0)自高而低逐位比較EQ=(A3⊙B3)·(A2⊙B2)·(A1⊙B1)·(A0⊙B0)GT=(A3>B3)LT=EQ’·GT’=(EQ+GT)’或(A3=

B3)·(A2=

B2)·

(A1>B1)或(A3=

B3)·(A2=

B2)·(A1=

B1)·

(A0>B0)或(A3=

B3)·

(A2>B2)A3·

B3’A2·

B2’A1·

B1’A0·

B0’⊙⊙⊙⊙⊙⊙+++74x854-BitComparator74x85

(4位比較器74x85)A0A1A2A3ALTBINAEQBINAGTBIN級(jí)聯(lián)輸入，用于擴(kuò)展ALTBOUT=(A<B)+(A=B)·ALTBIN通常低位的輸出接高位的輸入A=B：低位和高位都相等A高位>B高位A高位=B高位&A低位>B低位A>BAEQBOUT=(A=B)·AEQBINAGTBOUT=(A>B)+(A=B)·AGTBINSerialExpandingComparators

(比較器的串行擴(kuò)展)XD[11:0]YD[11:0][3:0][7:4][11:8]X<YX=YX>Y+5VA<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x85A<BIA=BIA>BIA<BOA=BOA>BOA0~A3B0~B374x853片74x85構(gòu)成12位比較器低位高位P0P1P2P3P4P5P6P78-bitcomparator74x682問題1：怎樣表示以下輸出？

active-high：PDIFFQ

active-high：PEQQactive-high：PGEQ

active-high：PLTQ（P463圖6-81）GELT問題2：能否擴(kuò)展？？注意：沒有級(jí)聯(lián)輸入端P464Figure6-823片74x682構(gòu)成24位比較器P0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>QP0~P7P=QQ0~Q7P>Q[7:0][15:8][23:16]