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先進(jìn)芯片封裝知識(shí)介紹OutlinePackageDevelopmentTrend3DPackageWLCSP&FlipChipPackage22020/11/30PackageDevelopmentTrend32020/11/30SOFamilyQFPFamilyBGAFamilyPackageDevelopmentTrend42020/11/30CSPFamilyMemoryCardSiPModulePackageDevelopmentTrend52020/11/303DPackage3DPackage62020/11/303DPackageIntroductionetCSPStackFunctionalIntegrationHighLowTape-SCSP(orLGA)S-CSP(orLGA)S-PBGAS-M2CSPStacked-SiP2ChipStackWirebond2ChipStackFlipChip&WirebondMultiChipStackPackageonPackage(PoP)StackingSS-SCSP(film)FS-BGA3S-PBGAS-SBGAS-TSOP/S-QFP

3S-CSPS-etCSPetCSP+S-CSP

PS-fcCSP+SCSP

PoPwithinterposerFS-CSP2FS-CSP1PaperThinPS-vfBGA+SCSPPiP

5SCSPSS-SCSP(paste)UltrathinStackD2D3D4D2D2D3D4D2

PoPQFN4SS-SCSP72020/11/30StackedDieTopdieBottomdieFOWmaterilWire82020/11/30TSVTSV(ThroughSiliconVia) Athrough-siliconvia(TSV)isaverticalelectricalconnection(via)passingcompletelythroughasiliconwaferordie.TSVtechnologyisimportantincreating3Dpackagesand3Dintegratedcircuits.

A3Dpackage(SysteminPackage,ChipStackMCM,etc.)containstwoormorechips(integratedcircuits)stackedverticallysothattheyoccupylessspace. Inmost3Dpackages,thestackedchipsarewiredtogetheralongtheiredges.Thisedgewiringslightlyincreasesthelengthandwidthofthepackageandusuallyrequiresanextra“interposer”layerbetweenthechips. Insomenew3Dpackages,through-siliconviareplaceedgewiringbycreatingverticalconnectionsthroughthebodyofthechips.Theresultingpackagehasnoaddedlengthorthickness.WireBondingStackedDieTSV92020/11/30What’sPoP?PoPisPackageonPackageTopandbottompackagesaretestedseparatelybydevicemanufacturerorsubcon.

PoP102020/11/30PoPPS-vfBGAPS-etCSPLowLoopWirePinGateMoldPackageStackingWaferThinningPoPCoreTechnology112020/11/30PoPAllowsforwarpagereductionbyutilizingfully-moldedstructureMorecompatiblewithsubstratethicknessreductionProvidesfinepitchtoppackageinterfacewiththrumoldviaImprovedboardlevelreliabilityLargerdiesize/packagesizeratioCompatiblewithflipchip,wirebond,orstackeddieconfigurationsCosteffectivecomparedtoalternativenextgenerationsolutionsAmkor’sTMV?PoPTopviewBottomviewThroughMoldVia122020/11/30PoP

BallPlacementontopsurfaceBallPlacementonbottomDieBondMold(UnderFulloptional)LaserdrillingSingulationFinalVisualInspectionBaseM’tlThermaleffectProcessFlowofTMVPoP132020/11/30Digital(Btmdie)+Analog(Middledie)+Memory(Toppkg)PotableDigitalGadgetCellularPhone,DigitalStillCamera,PotableGameUnitMemorydieAnalogdieDigitaldiespacerEpoxyPiP142020/11/30EasysystemintegrationFlexiblememoryconfiguration100%memoryKGDThinnerpackagethanPOPHighIOinterconnectionthanPOPSmallfootprintinCSPformatIthasstandardballsizeandpitchConstructedwith:FilmAdhesivedieattachEpoxypasteforTopPKGAuwirebondingforinterconnectionMoldencapsulationWhyPiP?

PiP152020/11/30MaterialforHighReliabilityBasedonLowWarpageWaferThinningFineProcessControlTopPackageAttachDieAttachetcOptimizedPackageDesignFlipChipUnder-fillTopepoxyISMPiPCoreTechnology

PiP162020/11/30MemoryPKGSubstrateFlipchipMemoryPKGFlipchipInnerPKGAnalogAnalogSpacerDigitalInnerPKGWBPIPFCPIPPiPPiP–W/BPiPandFCPiP

172020/11/30WLCSP&FlipChipPackage182020/11/30WLCSPWhatisWLCSP? WLCSP(WaferLevelChipScalePackaging),isnotsameastraditionalpackagingmethod(dicingpackagingtesting,packagesizeisatleast20%increasedcomparedtodiesize). WLCSPispackagingandtestingonwaferbase,anddicinglater.Sothepackagesizeisexactlysameasbarediesize.

WLCSPcanmakeultrasmallpackagesize,andhighelectricalperformancebecauseoftheshortinterconnection.192020/11/30WLCSPWhyWLCSP?Smallestpackagesize:WLCSPhavethesmallestpackagesizeagainstdiesize.Soithaswidelyuseinmobiledevices.Highelectricalperformance:becauseoftheshortandthicktraceroutinginRDL,itgiveshighSIandreducedIRdrop.Highthermalperformance:sincethereisnoplasticorceramicmoldingcap,heatfromdiecaneasilyspreadout.Lowcost:noneedsubstrate,onlyonetimetesting.WLCSP’sdisadvantageBecauseofthediesizeandpinpitchlimitation,IOquantityislimited(usuallylessthan50pins).BecauseoftheRDL,staggerIOisnotallowedforWLCSP.202020/11/30RDLRDL:RedistributionLayerAredistributionlayer(RDL)isasetoftracesbuiltuponawafer’sactivesurfacetore-routethebondpads.

Thisisdonetoincreasethespacingbetweeneachinterconnection(bump).212020/11/30WLCSPProcessFlowofWLCSP222020/11/30WLCSPProcessFlowofWLCSP232020/11/30FlipChipPackageFCBGA(PassiveIntegratedFlipChipBGA)(PI)-EHS-FCBGA(PassiveIntegratedExposedHeatSinkFlipChipBGA)(PI)-EHS2-FCBGA(PassiveIntegratedExposed2piecesofHeatSinkFlipChipBGA)MCM-FCBGA(Multi-Chip-ModuleFCBGA)PI-EHS-MP-FCBGA(PassiveIntegratedExposedHeatSinkMultiPackageFlipChip)242020/11/30Bump252020/11/30BumpDevelopment262020/11/30BumpDevelopment272020/11/30BumpDevelopment282020/11/30C4FlipChipWhat’sC4FlipChip?C4is:ControlledCollapsedChipConnectionChipisconnectedtosubstratebyRDLandBumpBumpmaterialtype:solder,gold292020/11/30C4FlipChipBGAMainFeaturesBallPitch:0.4mm-Packagesize:upto55mmx55mmSubstratelayer:4-16LayersBallCount:upto2912

TargetMarket:

CPU、F

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