單周期實(shí)驗(yàn)報(bào)告電子信息與電器工程學(xué)院

年 月 F /201965I/OI/OI/O（1）實(shí)驗(yàn)儀器：3.實(shí)驗(yàn)任務(wù)VerilogHDLquartus20MIPSCPU的一部分，實(shí)現(xiàn)CPU與外部設(shè)備的輸入輸出端口設(shè)計(jì)。實(shí)驗(yàn)中可采用高端I/OlwDE2信息。即將外部設(shè)備狀態(tài)，讀到CPU內(nèi)部寄存器。I/OswDE2LED設(shè)備的控制信號(hào)（或數(shù)據(jù)信息）。即將對(duì)外部設(shè)備的控制數(shù)據(jù)，從CPU內(nèi)部按鍵的狀態(tài)輸入，并將判別或處理結(jié)果，利用板載LED燈或7LED數(shù)碼2個(gè)LED數(shù)碼管以10LED上指令集的測(cè)試應(yīng)用功能的程序設(shè)計(jì)代碼，流程圖。 //SchoolofSoftwareof //inputresetn,clock,mem_clk;inputresetn,mem_clk;wireinput[3:0]in_port0,//output[31:0]wire[31:0] wireimem_clk,dmem_clk;output[31:0]out_port0,out_port1,out_port2;wire[31:0]out_port0,out_port1,out_port2;wire[31:0]data;wirewmem;//allthese"wire"sareusedtoconnectorinterfacethecpu,dmem,imemandsoon.outputwire[6:0]clock_divsc_cpucpu(clock,resetn,inst,memout,pc,wmem,aluout,data); sc_instmemimem(pc,inst,clock,mem_clk,imem_clk); instructionmemory.sc_datamemdmemt0,out_port1,out_port2);//datamemory.sevensegss0(out_port0[3:0],HEX0);sevensegss1(out_port0[7:4],HEX1);sevensegss2(out_port1[3:0],HEX2);sevensegss3(out_port1[7:4],HEX3);sevensegss4(out_port2[3:0],HEX4);sevensegss5(out_port2[7:4],HEX5);module//NOTE:lw,iotoinput[31:0]input[3:0]in_port0,in_port1;inputio_clk;outputwire[31:0]io_read_data;reg[31:0]in_reg0,in_reg1;in_reg0=in_reg1=always@(posedgeio_clk)in_reg0<={28'b0,in_port0};in_reg1<=//NOTE:input[31:0]addr,inputwrite_io_enable,io_clk,outputreg[31:0]out_port0,out_port1,always@(posedgeio_clkornegedgeclrn)out_port0<=out_port1<=out_port2<=6'b100000:out_port0<=datain;6'b100001:out_port1<=datain;6'b100010:out_port2<=datain;moduleio_input_mux(in_reg0,in_reg1,addr,io_read_data);input[31:0]in_reg0,in_reg1;input[5:0]outputreg[31:0]io_read_data;io_read_data=always6'b110000:io_read_data=in_reg0;6'b110001:io_read_data=in_reg1;modulealu(a,b,aluc,s,z);input[31:0]a,b;input[3:0]output[31:0]s; reg[31:0]s; always@(aorbor //casex4'bx000:s=a+ //x0004'bx100:s=a- //x1004'bx001:s=a& //x0014'bx101:s=a| //x1014'bx010:s=a^ //x0104'bx110:s={b,16'b0}; //x110LUI:imm<<16bit4'b0011:s=b<<<a; //0011SLL:rd<-(rt<<sa)4'b0111:s=b>>>a; //0111SRL:rd<-(rt>>sa)(logical)4'b1111:s=$signed(b)>>>a; //1111SRA:rd<-(rt>>sa)default:s=

if(s==0)z=1;elsez=0;modulesc_cu(op,func,z,wmem,wreg,regrt,m2reg,aluc,shift,aluimm,pcsource,jal,sext);input[5:0]op,func; output[3:0]aluc;output[1:0]pcsource;wirer_type=~|op;wirei_add=r_type&func[5]&~func[4]&~func[3]~func[2]&~func[1]&~func[0]; wirei_sub=r_type&func[5]&~func[4]&~func[3]&~func[2]&func[1]& //pleasecompletethedeletedwirei_and=r_type&func[5]&~func[4]&~func[3]&func[2]~func[1]&~func[0];wirei_or=r_type&func[5]&~func[4]&~func[3]&func[2]~func[1]&func[0];wirei_xor=r_type&func[5]&~func[4]&~func[3]&func[2]&func[1]&~func[0];//100110wirei_sll=r_type&~func[5]&~func[4]&~func[3]&~func[2]~func[1]&~func[0];wirei_srl=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]&~func[0];//000010wirei_sra=r_type&~func[5]&~func[4]&~func[3]&~func[2]&func[1]&func[0];//000011wirei_jr=r_type&~func[5]&~func[4]&func[3]&~func[2]~func[1]&~func[0];//Note:here,op[i]insteadofwirei_addi=~op[5]&~op[4]&op[3]&~op[2]&~op[1]&~op[0];//001000wirei_andi=~op[5]&~op[4]&op[3]&op[2]&~op[1]&~op[0];wirei_ori=~op[5]&~op[4]&op[3]&op[2]&~op[1]&op[0];//001101wirei_xori=~op[5]&~op[4]&op[3]&op[2]&op[1]&~op[0];//001110wirei_lw=op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0];//100011wirewirewirei_beqwirei_bnewirei_luiwirei_jwire=op[5]&~op[4]=~op[5]&~op[4]=~op[5]&~op[4]=~op[5]&~op[4]=~op[5]&~op[4]op[3]&~op[2]&op[1]&op[0];~op[3]&op[2]&~op[1]&~op[0];~op[3]&op[2]&~op[1]&op[0];op[3]&op[2]&op[1]&op[0];~op[3]&~op[2]&op[1]&~op[0];=~op[5]&~op[4]&~op[3]&~op[2]&op[1]&op[0];assignpcsource[1]=i_jr|i_j|assignpcsource[0]=(i_beq&z)|(i_bne&~z)|i_j|i_jalassignwreg=i_add|i_sub|i_and| |i_xori_sll|i_srl|i_sra|i_addi|i_andii_ori|i_xori|i_lw|i_lui|//aluc+:0000,-:x100and:x001or:x101xor:x010lui:x110sll:0011//Note:bne,beq==xorassignaluc[3]=assignaluc[2]=i_or|i_ori|i_lui|i_srl|i_sra|assignaluc[1]=i_beq|i_bne|i_xor|i_xori|i_lui|i_sll|i_srl|assignaluc[0]=i_and|i_andi|i_or|i_ori|i_sll|i_srl|i_sra;assignshift =i_sll|i_srl|i_sra;assignaluimm=i_addi|i_andi|i_ori|i_xori|i_lw|i_sw;//I-type(exceptLUI?).J-typeisprocessedassign =i_addi|i_lw|i_sw|i_beq|i_bne;//arithmeticI-logicalassignassign//rd=assign===i_addi|i_andi|i_ori|i_xori|i_lw|=的二進(jìn)制代碼，接著，為調(diào)用IO，完成io_input_mux,io_input_reg,io_output_reg三個(gè)DEPTH=64;%Memorydepthandwidtharerequired%WIDTH=32;%EnteradecimalnumberADDRESS_RA