講義課件教程

5?CPU設(shè)實(shí)驗(yàn)理解計(jì)算機(jī)指令流?線的協(xié)調(diào)?作原理，初步掌握流?線的設(shè)計(jì)原理2.深刻理解流?線寄存器在流?線實(shí)現(xiàn)3理解和掌握流?段的劃分、設(shè)計(jì)原理及其實(shí)現(xiàn)4.掌握運(yùn)算器、寄存器堆、器、控制器在流??作?式下，有別于實(shí)驗(yàn)?的設(shè)計(jì)?法5掌握流??式下，通過I/O端?與外部設(shè)備進(jìn)實(shí)驗(yàn)采?VerilogHDL在quartusⅡ中實(shí)現(xiàn)基本的具有20條MIPS指令的單周期CPU設(shè)計(jì)利?實(shí)驗(yàn)提供的標(biāo)準(zhǔn)測(cè)試程序代碼，完成仿真測(cè)試?yán)???編寫的程序代碼，在??設(shè)計(jì)的CPU上，實(shí)現(xiàn)對(duì)板載輸?開關(guān)或按鍵的狀態(tài)輸?處理結(jié)果，利?板載LED燈或7段LED數(shù)碼管顯?出來實(shí)驗(yàn)DE1SOC實(shí)驗(yàn)板套件1套萬?表1臺(tái)?波器1頂層實(shí)驗(yàn)設(shè)計(jì)采?了如下圖所?的結(jié)inputresetn,clock,mem_clock;output[31:0]input[3:0]in_port0,in_port1;output[6:0]hex0,hex1,hex2,hex3,hex4,hex5;wire[31:0]out_port0,out_port1,wire[31:0] wire[31:0]wire[31:0]wire[31:0]wire[31:0]//registerwire[4:0]wire[3:0]wire[1:0]//freezePCandIF/IDwirewpcir;wirewirewirewire//IF/ID/MEMreadatnegedgeofclock. pipeifif_stage(pcsource,pc,bpc,da,jpc, pipeirinst_reg(pc4,ins,wpcir,clock,resetn,dpc4,inst);pipeididstage(mwreg,mrn,ern,ewreg,em2reg,mm2reg,dpc4,inst,pipederegdepipeemregem_reg(ewreg,em2reg,ewmem,ealu,eb,ern,clock,resetn,mwreg,pipememmemstage(mwmem,malu,mb,wmo,wm2reg,inport0,inport1,pipemwregmw_reg(mwreg,mm2reg,mmo,malu,mrn,clock,resetn,wwreg,muxx32wbreg[3:0]low0,high0,low1,high1,low2,high2;always@(*)high0=out_port0/low0=out_port0-high0*10; outport1/10;low1=out_port1-high1*10;high2=out_port2/10;low2=out_port2-high2*sevensegtrans0(low0,hex4);sevensegtrans1(high0,hex5);sevensegtrans2(low1,hex2);sevensegtrans3(high1,hex3);sevensegtrans4(low2,hex0);sevensegtrans5(high2,hex1);具體pipepc決定了當(dāng)前應(yīng)該賦給pc的值，這是?個(gè)D鎖存器，當(dāng)wpcir=1且resetn!=0的時(shí)候才?種，rom通過輸?的pc獲取輸出的IF級(jí)和ID級(jí)之間的流?線寄存器模塊，當(dāng)wpcir1且resetn!0的時(shí)候，D鎖存器將pc4賦值給dpc4，將ins賦reg?le和單周期的?致，cu中除去解決數(shù)據(jù)和控制的forwardA&B，以及控制停頓的wpcir，其余均與單周期流?線?致。值得注意的是，fwda,fwdb?來判斷是否有可以?轉(zhuǎn)發(fā)來解決的數(shù)據(jù)，通過?個(gè)四modulemodulepipeid(mwreg,mrn,ern,ewreg,em2reg,mm2reg,dpc4,inst,inputwireinputwiremwreg,ewreg,em2reg,mm2reg,wwreg;inputwire[4:0]mrn,ern,wrn;inputwire[31:0]outputwiredwreg,dm2reg,dwmem,daluimm,dshift,djal,wpcir;outputwire[3:0]daluc;outputwire[31:0]da,db,dimm,bpc,jpc;outputwire[4:0]drn;outputwire[1:0]pcsource;wiredregrt,sext;//fromCU.wire[3:0]daluc_tmp;wire[4:0]drn_tmp;wirez=~|(da^db);wire[5:0]op=inst[31:26];wire[5:0]func=inst[5:0];wire[4:0]rs=inst[25:21];wire[4:0]rt=inst[20:16];wire[4:0]rd=inst[15:11];wire[31:0]sa={27'b0,inst[10:6]};//extendto32bitsfromsaforshiftwire[31:0]rf_outa,pipecucu(op,func,z,dwmem_tmp,dwreg_tmp,dregrt,dm2reg_tmp,daluc_tmp,dshifttmp,daluimm_tmp,pcsource,djal_tmp,regfilerf(rs,rt,wdi,wrn,wwreg,clock,resetn,rf_outa,rf_outb);assigndwreg=wpcir?dwreg_tmp:1'b0;assigndm2reg=wpcir?dm2reg_tmp:1'b0;assigndwmem=wpcir?dwmem_tmp:1'b0;assigndaluimm wpcir?daluimmtmp:1'b0;assigndshift=wpcir?dshift_tmp:1'b0;assigndjal=wpcir?djal_tmp:1'b0;assigndaluc=wpcir?daluc_tmp:4'b0;assigndrn assignjpc={dpc4[31:28],inst[25:0],1'b0,1'b0};wiree=sext&inst[15];wire[15:0]imm={16{e}};assigndimm {imm,inst[15:0]};wire[31:0]offset={imm[13:0],inst[15:0],1'b0,1'b0};assignbpc=dpc4+offset;//data//forwarding:1instructionbefore,R-type=>ealu(readybeforenegedgeofsystem//forwarding:2instructionsbefore,R-type=>malu(readybeforenegedgeofsystemwire[1:0]fwda,assignfwda[0]=(ewreg&~em2reg&ern==rs&ern!=0)|assignfwda[1]=(mwreg&~mm2reg&mrn==rs&ern!=rs&mrn!=0)|(mm2reg&mrn==rs&mrn!=0);assignfwdb[0] (ewreg&~em2reg&ernrt&ern!0)|(mm2reg&mrnrt&mrn!0);assignfwdb[1]=(mwreg&~mm2reg&mrn==rt&ern!=rt&mrn!=0)|wire[31:0]assignda dshift?sa:rfmux4x32forwarding_da(da_tmp,ealu,malu,mmo,fwda,da);mux4x32//neednottostop:2instruction//havetostop:1instructionbefore,assignwpcir=~(em2reg&((ern==rs)|(ern==rt))&//controlhazards:flushwhenj/jal/beq/bne. atnextEXE，ALU與單周期 致，增 MEM/WB線寄存器，當(dāng)resetn!=0時(shí)，將MEM段的輸出賦給WB段的輸?，否則輸?變成0流?線流?線cpu可能會(huì)發(fā)?結(jié)構(gòu)，數(shù)據(jù)和控制。本實(shí)驗(yàn)要解決的是數(shù)據(jù)和控制數(shù)據(jù)及解決辦法。數(shù)據(jù)是指令之間會(huì)有數(shù)據(jù)相關(guān)的問題，?條指令沒有執(zhí)?完，下?條指令就 頓會(huì)??降低流?線cpu的效率，所以本實(shí)驗(yàn)采?了內(nèi)部前推的?法應(yīng)對(duì)數(shù)據(jù)。內(nèi)部前推有三種情況，alu的計(jì)算結(jié)果從EXE段推到ID段，alu的計(jì)算結(jié)果從MEM段推到ID段，lw指令從數(shù)據(jù)器讀出的 器的寫信號(hào)與wpcir做與運(yùn)算。這?部分在ID段controlunit控制及解決辦法。MIPS指令集中有jr，beq，bne，j，jal會(huì)引起pc的轉(zhuǎn)移或跳轉(zhuǎn)，但是在跳轉(zhuǎn)過指令這次我實(shí)現(xiàn)的是減法器的功能匯編指令采?的寄存器地址需要與輸?端??致并將操作數(shù)與結(jié)果通過sw指令到輸出端?上。DEPTHDEPTH=64;%Memorydepthandwidtharerequired%WIDTH=32;%Enteradecimalnumber%ADDRESSRADIX HEX;%Addressandvalueradixesareoptional%DATA_RADIX=HEX;%EnterBIN,DEC,HEX,orOCT;unless%%otherwisespecified,radixes=HEX%0 ;%addi$2,$0,801 ;%addi$3,$0,842:200400c0;%addi$4,$0,c03:200500c4;%addi$5,$0,c44:8c8a0000;%lw$10,0($4)5:8cab0000;%lw$11,0($5)6 ;%addi$8,$10,07 ;