第3章-VHDL設(shè)計(jì)初步-習(xí)題

習(xí)題3-2圖3-16所示的是4選1多路選擇器，試分別用IF_THEN語(yǔ)句、WHEN_ELSE和CASE語(yǔ)句的表達(dá)方式寫出此電路的VHDL程序，要求選擇控制信號(hào)s1和s0的數(shù)據(jù)類型為STD_LOGIC；當(dāng)s1='0'，s0='0'；s1='0'，s0='1'；s1='1'，s0='0'和s1='1'，s0='1'時(shí)，分別執(zhí)行y<=a、y<=b、y<=c、y<=d。

習(xí)題3-2WHEN_ELSE條件信號(hào)賦值語(yǔ)句

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux41ISPORT(s0,s1:instd_logic;a,b,c,d:instd_logic;y:outstd_logic);ENDENTITYmux41;ARCHITECTUREbehave1OFmux41ISSIGNALs:std_logic_vector(1downto0);BEGINS<=s1&s0;y<=aWHENs="00"ELSE bWHENs="01"ELSE cWHENs="10"ELSE dWHENs="11"ELSE '0';ENDbehave1;多選擇控制的IF語(yǔ)句

IF條件1THEN<順序語(yǔ)句l>;ELSIF條件2THEN<順序語(yǔ)句2>;…..ELSIF條件nTHEN<順序語(yǔ)句n>;ELSE<順序語(yǔ)句n+1>;ENDIF;…ARCHITECTUREbehave2OFmux41ISSIGNALs:std_logic_vector(1downto0);BEGINs<=s1&s0;PROCESS(s,a,b,c,d)BEGINIFs="00"THENy<=a;ELSIFs="01"THENy<=b;ELSIFs="10"THENy<=c;ELSEy<=d;ENDIF;ENDPROCESS;ENDbehave2;CASE語(yǔ)句…ARCHITECTUREbehave3OFmux41ISSIGNALs:std_logic_vector(1downto0);BEGINs<=s1&s0;PROCESS(s,a,b,c,d)BEGINCASEsISWHEN"00"=>y<=a;WHEN"01"=>y<=b;WHEN"10"=>y<=c;WHEN"11"=>y<=d;WHENOTHERS=>y<='0';ENDCASE;ENDPROCESS;ENDbehave3;習(xí)題3-3圖3-17所示的是雙2選1多路選擇器構(gòu)成的電路MUXK，對(duì)于其中MUX21A，當(dāng)s='0'和s='1'時(shí)，分別有y<='a'和y<='b'。試在一個(gè)結(jié)構(gòu)體中用兩個(gè)進(jìn)程來表達(dá)此電路，每個(gè)進(jìn)程中用CASE語(yǔ)句描述一個(gè)2選1多路選擇器MUX21A。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmuxkISPORT(a1,a2,a3:instd_logic;s0,s1:instd_logic;outy:outstd_logic);ENDENTITYmuxk;ARCHITECTUREbehaveOFmuxkISSIGNALtmp:std_logic;SIGNALoutx:std_logic;BEGINPr1:PROCESS(a2,a3,s0)BEGINCASEs0ISWHEN'0'=>tmp<=a2;WHEN'1'=>tmp<=a3;WHENOTHERS=>tmp<='0';ENDCASE;ENDPROCESS;Pr2:PROCESS(a1,tmp,s1)BEGINCASEs1ISWHEN'0'=>outx<=a1;WHEN'1'=>outx<=tmp;WHENOTHERS=>outx<='0';ENDCASE;ENDPROCESS;outy<=outx;ENDbehave;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux21aISPORT(a,b:instd_logic;s:instd_logic;y:outstd_logic);ENDENTITYmux21a;ARCHITECTUREbehaveOFmux21aISBEGINy<=aWHENs='0'ELSEb;ENDbehave;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmuxkISPORT(a1,a2,a3:instd_logic;s0,s1:instd_logic;outy:outstd_logic);ENDENTITYmuxk;ARCHITECTUREbehaveOFmuxkISSIGNALtmp:std_logic;COMPONENTmux21aPORT(a,b,s:instd_logic;y:outstd_logic);ENDCOMPONENT;BEGINu1:mux21aPORTMAP(a2,a3,s0,tmp);u2:mux21aPORTMAP(a1,tmp,s1,outy);ENDbehave;必須先編譯、調(diào)試子模塊，才能使用元件例化語(yǔ)句。

習(xí)題3-6圖3-18是一個(gè)含有上升沿觸發(fā)的D觸發(fā)器的時(shí)序電路，試寫出此電路的VHDL設(shè)計(jì)文件。

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmux_dISPORT(CL,CLK0:instd_logic;OUT1:outstd_logic);END;ARCHITECTUREbehaveOFmux_dISSIGNALx,y:std_logic;BEGINx<=NOT(CLORy);--或x<=CLNORyOUT1<=NOTy;PROCESS(CLK0)BEGINIFCLK0'EVENTANDCLK0='1'THENy<=x;ENDIF;ENDPROCESS;ENDbehave;4-5.給出1位全減器的VHDL描述。要求：(1)首先設(shè)計(jì)1位半減器，然后用例化語(yǔ)句將它們連接起來，圖4-20中h_suber是半減器，diff是輸出差，s_out是借位輸出，sub_in是借位輸入。(2)以1位全減器為基本硬件，構(gòu)成串行借位的8位減法器，要求用例化語(yǔ)句來完成此項(xiàng)設(shè)計(jì)(減法運(yùn)算是x–y-sun_in=diffr)。圖4-19時(shí)序電路圖

t0t1t2(1)先設(shè)計(jì)一個(gè)半減器Libraryieee;useieee.std_logic_1164.alll;Entityh_suberisPort(x,y:instd_logic;diff,s_out:outstd_logic);endh_suber;Architecturebehavofh_suberisBeginprocess(x,y)begindiff<=xxory;s_out<=(notx)andy;Endprocess;Endbehav;x、y00011011diff0110S_out0100一位全減器的VHDL描述suber.vhdLibraryieee;useieee.std_logic_1164.alll;EntitysuberisPort(x,y,sub_in:instd_logic;diffr,sub_out:outstd_logic);Endsuber;ArchitecturebehavofsuberisComponenth_suberPort(x,y:instd_logic;diff,s_out:outstd_logic);Endcomponent;Signalt0,t1,t2:std_logic;Beginu1:h_suberportmap(x=>x,y=>y,diff=>t0,s_out=>t1);u2:h_suberportmap(x=>t0,y=>sub_in,diff=>diffr,s_out=>t2);Sub_out<=t1ort2;Endbehav;(2)8位全減器(生成語(yǔ)句第九章)Libraryieee;useieee.std_logic_1164.alll;Entitysuber8isPort(a,b:instd_logic_vector(7downto0);Sin:instd_logic;sout:outstd_logic;C:outstd_logic_vector(7doento0);Endsub8;Architecturebehavofsuber8isComponentsuberPort(x,y,sub_in:instd_logic;diffr,sub_out:outstd_logic);Endcomponent;Signalstmp:std_logic_vector(8downto0);Beginstmp(0<=sin;Sout<=stmp(8);Gensub:foriin0to7generateu1:subportmap(x=>a(i),y=>b(i),diffr=>c(i),sub_out=>stmp(i+1));Endgenerate;end;習(xí)題3-4將3-20程序的計(jì)數(shù)器改為12進(jìn)制計(jì)數(shù)器，程序用例3-21的方式表述，并且將復(fù)位RST改為同步清0控制，加載信號(hào)LOAD改為異步控制方式。討論例3-20與例3-21的異同點(diǎn)。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT12ISPORT(CLK,RST,EN,LOAD:INSTD_LOGIC;DATA:INSTD_LOGIC_VECTOR(3DOWNTO0);DOUT:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);END;ARCHITECTUREbehavOFCNT12ISSIGNALQ:STD_LOGIC_VECTOR(3DOWNTO0);BEGINREG:PROCESS(CLK,LOAD)BEGIN

IFLOAD='0'THENQ:=DATA; ELSIFCLK'EVENTANDCLK='1'THEN IFEN='1'THEN

IF(RST='0')THENQ:=(OTHERS=>'0');

ELSEIFQ<11THENQ:=Q+1;ELSEQ:=(OTHERS=>'0');ENDIF;ENDIF; ENDIF; ENDIF;ENDPROCESS;COM:PROCESS(Q) IFQ="1011"THENCOUT<='1'; ELSECOUT<='0'; ENDIF;ENDPROCESS;DOUT<=Q;ENDbehav;習(xí)題準(zhǔn)備：設(shè)計(jì)含有異步清零和計(jì)數(shù)使能的16位二進(jìn)制加法可控計(jì)數(shù)器。LIBRARYieee;USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;USEieee.std_logic_arith.all;ENTITYex3_4_aISport(clk:instd_logic;clr,en:instd_logic;cnt:outstd_logic_vector(15downto0));END;ARCHITECTUREbhvOFex3_4_aIS signalcnt_tmp:std_logic_vector(15downto0); BEGIN process(clk,clr)begin

ifclr='1'thencnt_tmp<=(others=>'0');

elsif(rising_edge(clk))thenifen='1'thencnt_tmp<=cnt_tmp+1;endif;

endif;endprocess;cnt<=cnt_tmp;END;習(xí)題3-5設(shè)計(jì)含有異步清零和計(jì)數(shù)使能的16位二進(jìn)制加減法可控計(jì)數(shù)器。LIB