第7章單片機a-d轉(zhuǎn)換模塊實驗

CollegeofCommunicationEngineering,JilinUniversity第7章單片機A-D轉(zhuǎn)換模塊2CollegeofCommunicationEngineering,JilinUniversity7A-D轉(zhuǎn)換模塊7.1A-D轉(zhuǎn)換概述7.2A-D模塊寄存器7.3A-D模塊編程范例3CollegeofCommunicationEngineering,JilinUniversity7.1A-D轉(zhuǎn)換概述-轉(zhuǎn)換原理微控制器處理的是離散量(數(shù)字量)，而現(xiàn)實中往往是連續(xù)量(模擬量)。物理量如：溫度，壓力，濕度以及速度等等。傳感器將物理量轉(zhuǎn)換為電信號(電壓，電流)需要模擬-數(shù)字轉(zhuǎn)換器將電信號轉(zhuǎn)換為數(shù)字量以供微控制器處理4CollegeofCommunicationEngineering,JilinUniversity逐次逼近式A/D轉(zhuǎn)換器工作原理（4位為例）＋－Uin逐次逼近寄存器D/A轉(zhuǎn)換器結(jié)果UrefSA-ADC完成一次轉(zhuǎn)換至少需要n個時鐘周期7.1A-D轉(zhuǎn)換概述-轉(zhuǎn)換原理5CollegeofCommunicationEngineering,JilinUniversity采樣保持電路可以避免輸入電壓在轉(zhuǎn)換期間發(fā)生變化而引起的差錯。＋－Uin7.1A-D轉(zhuǎn)換概述-轉(zhuǎn)換原理6CollegeofCommunicationEngineering,JilinUniversityA-D參數(shù)轉(zhuǎn)換位數(shù)（Bits）:分辨率=2-n(8bits=1/256=0.39%)轉(zhuǎn)換速度（Speed）:由工作時鐘頻率和轉(zhuǎn)換位數(shù)確定轉(zhuǎn)換范圍（Range）:0~5V,0~10V,-5V~+5V.Etc..轉(zhuǎn)換通道數(shù)（Channels）:8、167.1A-D轉(zhuǎn)換概述-基本知識7CollegeofCommunicationEngineering,JilinUniversityS12單片機ADC特性如下：

8/10/12位可選

轉(zhuǎn)換速度較高，8位、8MHz、單次轉(zhuǎn)換時間為2us

采樣時間可編程設(shè)置多種轉(zhuǎn)換模式：數(shù)據(jù)對齊方式、單次/連續(xù)轉(zhuǎn)換、轉(zhuǎn)換結(jié)果比較外觸發(fā)控制轉(zhuǎn)換序列結(jié)束可產(chǎn)生中斷，能夠使能比較中斷模擬輸入引腳與通用I/O口復(fù)用多通道掃描，1~16轉(zhuǎn)換序列長度。7.1A-D轉(zhuǎn)換概述-模塊簡介8CollegeofCommunicationEngineering,JilinUniversityS12單片機ADC轉(zhuǎn)換時間：轉(zhuǎn)換時間計算舉例:(假設(shè)A/D時鐘為2MHz，10位精度

)轉(zhuǎn)換時間=InitialSampleTime+ProgrammedSampleTime+ResolutionPeriod=2+4+10=16A/DClocks=8us4~24ClocksAlways2Clocks7.1A-D轉(zhuǎn)換概述-模塊簡介9CollegeofCommunicationEngineering,JilinUniversityS12單片機ADC模塊框圖ADC引腳可用于數(shù)字輸入ADC結(jié)果寄存器模擬輸入通道參考電壓VDDAVSSAVRLVRH模擬信號7.1A-D轉(zhuǎn)換概述-模塊簡介10CollegeofCommunicationEngineering,JilinUniversity7.2A-D模塊寄存器S12單片機A-D模塊共27個寄存器控制寄存器（ATDCTL0~ATDCTL5，6個）狀態(tài)寄存器（ATDSTAT0~ATDSTAT1，2個）比較使能寄存器（ATDCMPE，1個）比較方式寄存器（ATDCMPHT，1個）轉(zhuǎn)換輸入使能寄存器（ATDDIEN，1個）轉(zhuǎn)換結(jié)果寄存器（ATDDR0~ATDDR15，16個）其中:8位寄存器：ATDCTL0~ATDCTL5,ATDSTAT016位寄存器：其余11CollegeofCommunicationEngineering,JilinUniversity1、ATDControlRegister0(ATDCTL0)$02C07.2A-D模塊寄存器WRAP[3-0]-WrapAroundChannelSelect0=ReservedX=多通道轉(zhuǎn)換模式從ANx回繞到AN0

1≤x≤15

僅在ATDCTL5的MULT=1時有效12CollegeofCommunicationEngineering,JilinUniversity2、ATDControlRegister1(ATDCTL1)$02C17.2A-D模塊寄存器SRES[1:0]-A/DResolutionSelectETRIGSEL-ExternalTriggerSourceSelect

S12XS此位無效ETRIGCH[3:0]-ExternalTriggerChannelSelectSMP_DIS-DischargeBeforeSamplingBit0=Nodischarge1=discharge

注：寫ATDCTL1會終止當前轉(zhuǎn)換序列13CollegeofCommunicationEngineering,JilinUniversity3、ATDControlRegister2(ATDCTL2)$02C27.2A-D模塊寄存器注：寫ATDCTL2會終止當前轉(zhuǎn)換序列AFFC-ATDFastFlagClearAll0=向CCF[n]標志位寫1則清零1=讀ATD轉(zhuǎn)換結(jié)果寄存器則CCF[n]標志位清零（當比較功能被禁止）寫ATD轉(zhuǎn)換結(jié)果寄存器則CCF[n]標志位清零（當比較功能被使能）ETRIGE-ExternalTriggerModeEnable0=禁止外部觸發(fā)信號1=使能外部觸發(fā)信號ASCIE-ATDSequenceCompleteInterruptEnable0=禁止ATD轉(zhuǎn)換序列結(jié)束中斷1=使能ATD轉(zhuǎn)換序列結(jié)束中斷ACMPIE-ATDCompareInterruptEnable0=禁止比較中斷1=使能比較中斷ICLKSTP-InternalClockinStopModeBit0=停止模式下，停止當前轉(zhuǎn)換，退出停止模式后

ATD轉(zhuǎn)換自動重新開始1=停止模式下，可繼續(xù)使用內(nèi)部時鐘進行ATD轉(zhuǎn)換ETRIGLE-外部信號觸發(fā)條件選擇位ETRIGP-外部信號極性14CollegeofCommunicationEngineering,JilinUniversity4、ATDControlRegister3(ATDCTL3)$02C37.2A-D模塊寄存器注：寫ATDCTL3會終止當前轉(zhuǎn)換序列DJM-ResultRegisterDataJustification0=Leftjustifieddataintheresultregisters1=RightjustifieddataintheresultregistersS8C,S4C,S2C,S1C-ConversionSequenceLengthFIFO-ResultRegisterFIFOMode0=Conversionresultsareplacedinthecorrespondingresultregisteruptotheselectedsequencelength.1=Conversionresultsareplacedinconsecutiveresultregisters(wraparoundatend).FRZ[1:0]-BackgroundDebugFreezeEnable15CollegeofCommunicationEngineering,JilinUniversity5、ATDControlRegister4(ATDCTL4)$02C47.2A-D模塊寄存器注：寫ATDCTL4會終止當前轉(zhuǎn)換序列設(shè)置預(yù)分頻因子時，0.25MHz≤ATDCLK≤8.3MHzSMP[2:0]-SampleTimeSelect，采樣時間包含的ATD時鐘周期PRS[4:0]-ATDClockPrescalerDivideBy25-BitModulusCounterPrescalerPRS0-PRS4SYSTEMCLOCKA/DClock采樣時間長，采樣點電平更準確的逼近外部信號電平16CollegeofCommunicationEngineering,JilinUniversity6、ATDControlRegister5(ATDCTL5)$02C57.2A-D模塊寄存器A-D啟動：寫ATDCTL5會終止當前轉(zhuǎn)換序列，并開始新一次轉(zhuǎn)換此后，若外部觸發(fā)信號每次滿足觸發(fā)條件都會開始一次ATD轉(zhuǎn)換

SC-SpecialChannelConversion0=Specialchannelconversionsdisabled1=SpecialchannelconversionsenabledSCAN-ContinuousConversionSequenceMode0=Singleconversionsequence1=Continuousconversionsequences(scanmode)MULT-Multi-ChannelSample0=Sampleonlyonechannel1=SampleacrossseveralchannelsCD,CC,CB,CA-AnalogInputChannelSelectCode17CollegeofCommunicationEngineering,JilinUniversity7.2A-D模塊寄存器單通道，單次轉(zhuǎn)換多通道，單次轉(zhuǎn)換單通道，序列轉(zhuǎn)換模式多通道，序列轉(zhuǎn)換模式特殊通道測試模式A-D模塊工作方式18CollegeofCommunicationEngineering,JilinUniversity7、ATDStatusRegister0(ATDSTAT0)$02C67.2A-D模塊寄存器SCF-SequenceCompleteFlag0=一次轉(zhuǎn)換序列未完成1=一次轉(zhuǎn)換序列完成ETORF-ExternalTriggerOverrunFlag0=NoExternaltriggeroverrunerrorhasoccurred1=ExternaltriggeroverrunerrorhasoccurredFIFOR-ResultRegisterOverrunFlag0=Nooverrunhasoccurred1=Overrunconditionexists(resultregisterhasbeenwrittenwhileassociatedCCFxflagwasstillset)CC[3:0]-ConversionCounter當前轉(zhuǎn)換結(jié)果將寫入的結(jié)果寄存器編號

例如：CC[3:0]=0110，轉(zhuǎn)換結(jié)果寫入第6個結(jié)果寄存器先入先出模式下，不被初始化，當計數(shù)到最大值回最小值非先入先出模式下，轉(zhuǎn)換開始和結(jié)束時被初始化為0兩種模式下終止ATD轉(zhuǎn)換或開始新ATD轉(zhuǎn)換均被清零19CollegeofCommunicationEngineering,JilinUniversity8、ATDCompareEnableRegister(ATDCMPE)$02C87.2A-D模塊寄存器CMPE[15:0]-CompareEnableforConversionNumbern(n=15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0)ofaSequence0=Noautomaticcompare1=Automaticcompareofresultsforconversionnofasequenceisenabled對一個序列中第n次ATD轉(zhuǎn)換結(jié)果進行比較，除CMPE[n]=1，還要完成如下設(shè)置：將比較閾值寫入ATDDRn寫ATDCPMHT的CMPHT[n]位選擇比較方法注：寫ATDCMPE會終止當前轉(zhuǎn)換序列20CollegeofCommunicationEngineering,JilinUniversity9、ATDStatusRegister2(ATDSTAT2)$02CA7.2A-D模塊寄存器CCF[15:0]-ConversionCompleteFlagn(n=15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0)0=Conversionnumbernnotcompletedorsuccessfullycompared1=If(CMPE[n]=0):Conversionnumbernhascompleted.ResultisreadyinATDDRn.If(CMPE[n]=1):CompareforconversionresultnumbernwithcomparevalueinATDDRn,usingcompareoperatorCMPGT[n]istrue.(NoresultavailableinATDDRn)出現(xiàn)以下任一情況，CCF[n]被清零：寫ATDCTL5當AFFC=0，向CCF[n]寫1當AFFC=1，且CMPE[n]=0，讀ATDDRn當AFFC=1，且CMPE[n]=1，寫ATDDRn21CollegeofCommunicationEngineering,JilinUniversity10、ATDInputEnableRegister(ATDDIEN)$02CC7.2A-D模塊寄存器IEN[15:0]-ATDDigitalInputEnableonchannelx(x=15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0)0=DisabledigitalinputbuffertoANxpin1=EnabledigitalinputbufferonANxpin通用I/O口AD口與ATD模塊的模擬輸入引腳復(fù)用將某個模擬輸入引腳作為通用輸入引腳使用時，必須將對應(yīng)IEN位置位22CollegeofCommunicationEngineering,JilinUniversity11、ATDCompareHigherThanRegister(ATDCMPHT)$02CE7.2A-D模塊寄存器CMPHT[15:0]-CompareOperationHigherThanEnableforconversionnumbern(n=15,14,…,2,1,0)ofaSequence0=IfresultofconversionnislowerorsamethancomparevalueinATDDRn,thisisflaggedinATDSTAT21=IfresultofconversionnishigherthancomparevalueinATDDRn,thisisflaggedinATDSTAT2注：寫ATDCMPHT會終止當前轉(zhuǎn)換序列23CollegeofCommunicationEngineering,JilinUniversity12~27、ATDConversionResultRegisters(ATDDRn)7.2A-D模塊寄存器ATDDR0~ATDDR15$02D0~$02EE關(guān)閉比較操作時，ATD轉(zhuǎn)換結(jié)果寫入ATDDRn

要寫入的ATDDRn的編號由ATDSTAT0的CC3~CC0轉(zhuǎn)換計數(shù)給出

轉(zhuǎn)換結(jié)果在ATDDRn中的放置位置與轉(zhuǎn)換精度和結(jié)果對齊方式有關(guān)使能比較功能時，ATD轉(zhuǎn)換結(jié)果和比較閾值都總是12位，與SRES[1:0](ATDCTL1)無關(guān)DJM=0比較閾值左對齊DJM=1比較閾值右對齊轉(zhuǎn)換結(jié)果不放入結(jié)果寄存器，比較完成后丟失24CollegeofCommunicationEngineering,JilinUniversity7.3A-D模塊編程范例ATD模塊編程需要考慮的問題：啟動轉(zhuǎn)換：寫ATD0CTL5將啟動轉(zhuǎn)換；若使用外部觸發(fā)，則需設(shè)定觸發(fā)通道，觸發(fā)條件，使能外部觸發(fā)轉(zhuǎn)換進行：設(shè)定AD時鐘，采樣時間，轉(zhuǎn)換位數(shù)，8/10/12位可選轉(zhuǎn)換通道是否為特殊通道；轉(zhuǎn)換序列是否為單通道；是否為連續(xù)轉(zhuǎn)換是否為比較功能，如是，則需要使能比較通道，寫比較閾值，選擇比較方式轉(zhuǎn)換結(jié)束：讀SCF判斷轉(zhuǎn)換序列是否完成；或查CCF[15:0]逐個通道判斷；或采用中斷方式設(shè)置AFFC，CCF是否快速清零結(jié)果數(shù)據(jù)存儲的寄存器設(shè)置FIFO讀結(jié)果數(shù)據(jù)寄存器比較方式下，比較結(jié)果存于CCF[15:0]，也可以使能比較中斷25CollegeofCommunicationEngineering,JilinUniversity7.3A-D模塊編程范例A-D模塊應(yīng)用注意事項ATD初始化：先寫除ATD0CTL5外的控制寄存器寫ATD0CTL5完成初始化，并啟動轉(zhuǎn)換；ATD結(jié)果讀?。?/p>

通過查詢ATD0STAT0中的SCF位（某通道的CCF位）或采用中斷方式，確定轉(zhuǎn)換完成，讀取相關(guān)結(jié)果寄存器取得ATD轉(zhuǎn)換結(jié)果。

8/10/12位可選26CollegeofCommunicationEngineering,JilinUniversity7.3A-D模塊編程范例（1）AD初始化

voidATD_init(void){ATD0CTL1=0x0F;//選擇8位轉(zhuǎn)換精度ATD0CTL2=0x40;//打開CCF快速清零，關(guān)閉外部觸發(fā)輸入，關(guān)閉中斷ATD0CTL3=0x08;//數(shù)據(jù)左對齊，non-fifo，轉(zhuǎn)換序列長度為1ATD0CTL4=0xE3;//采樣時間為24個ATD時鐘周期，ATDClk=8MB/8=1MHz}27CollegeofCommunicationEngineering,JilinUniversity7.3A-D模塊編程范例（2）單次、單通道for(;;){ATD0CTL5=0x0F;//單次轉(zhuǎn)換，單通道，選擇通道15//ATD0CTL5=0x46;//單次轉(zhuǎn)換，單通道，選擇特殊通道(VRL+VRH)/2while(!(ATD0STAT0&0x80));//查詢ATD是否完成

ADresult=ATD0DR0H;showdata[0]=ADresult&0x0F;showdata[1]=(ADresult&0xF0)>>4;

Show(); //顯示

}28CollegeofCommunicationEngineering,JilinUniversity7.3A-D模塊編程范例（3）連續(xù)、單通道for(;;){/*ATD0CTL5=0x0F;*///單次轉(zhuǎn)換，單通道，選擇通道15while(!(ATD0STAT0&0x80));//查詢ATD是否完成

ADresult=ATD0DR0H;showdata[0]=ADresult&0x0F;ATD0CTL5=0x2F;//連續(xù)轉(zhuǎn)換，單通道，選擇通道15showdata[1]=(ADresult&0xF0)>>4;ADresult=*(&ATD0DR0H+2);showdata[2]=ADresult&0x0F;showdata[3]=(ADresult&0xF0)>>4;Show(); //顯示

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