集成電路的基本制造工藝教材

集成電路的基本制造工藝教材上節(jié)課內容要點雙極集成電路的基本工藝雙極集成電路中元件結構2023/6/4pn+n-epin+P-Sin+-BLCBESP+P+雙極集成電路的基本工藝2023/6/4P-SiTepiCBEpn+n-epin+P-SiP+P+Sn+-BLTepiAA’TBL-uptepi-oxxmcxjc四層三結結構的雙極晶體管雙極集成電路中元件結構2023/6/4ECB相關知識點隱埋層的作用、電隔離的概念、寄生晶體管本節(jié)課內容

MOS集成電路的工藝

P阱CMOS工藝

BiCMOS集成電路的工藝

N阱CMOS工藝雙阱CMOS工藝2023/6/4MOS晶體管的動作

MOS晶體管實質上是一種使電流時而流過，時而切斷的開關n+n+P型硅基板柵極（金屬）絕緣層（SiO2）半導體基板漏極源極N溝MOS晶體管的基本結構源極(S)漏極(D)柵極(G)MOSFET的基本結構2023/6/4siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxideMOS晶體管的立體結構2023/6/4在硅襯底上制作MOS晶體管siliconsubstrate2023/6/4siliconsubstrateoxidefieldoxide2023/6/4siliconsubstrateoxidephotoresist2023/6/4ShadowonphotoresistphotoresistExposedareaofphotoresistChromeplatedglassmaskUltravioletLightsiliconsubstrateoxide2023/6/4非感光區(qū)域siliconsubstrate感光區(qū)域oxidephotoresist2023/6/4Shadowonphotoresistsiliconsubstrateoxidephotoresistphotoresist顯影2023/6/4siliconsubstrateoxideoxidesiliconsubstratephotoresist腐蝕2023/6/4siliconsubstrateoxideoxidesiliconsubstratefieldoxide去膠2023/6/4siliconsubstrateoxideoxidegateoxidethinoxidelayer2023/6/4siliconsubstrateoxideoxidepolysilicongateoxide2023/6/4siliconsubstrateoxideoxidegategateultra-thingateoxidepolysilicongate2023/6/4siliconsubstrateoxideoxidegategatephotoresistScanningdirectionofionbeamimplantedionsinactiveregionoftransistorsImplantedionsinphotoresisttoberemovedduringresiststrip.sourcedrainionbeam2023/6/4siliconsubstrateoxideoxidegategatesourcedraindopedsilicon2023/6/4自對準工藝在有源區(qū)上覆蓋一層薄氧化層淀積多晶硅，用多晶硅柵極版圖刻蝕多晶硅以多晶硅柵極圖形為掩膜板，刻蝕氧化膜離子注入2023/6/4siliconsubstratesourcedraingate2023/6/4siliconsubstrategatecontactholesdrainsource2023/6/4siliconsubstrategatecontactholesdrainsource2023/6/4完整的簡單MOS晶體管結構siliconsubstratesourcedraingateoxideoxidetopnitridemetalconnectiontosourcemetalconnectiontogatemetalconnectiontodrainpolysilicongatedopedsiliconfieldoxidegateoxide2023/6/4CMOSFETP型sisubn+gateoxiden+gateoxideoxidep+p+2023/6/4主要的CMOS工藝VDDP阱工藝N阱工藝雙阱工藝P-P+P+N+N+P+N+VSSVOUTVINVDDN-P+P+N+N+P+N+VSSVOUTVINVDDP-P+P+N+N+P+N+VSSVOUTVINN-SiP-SiN-I-SiN+-Si2023/6/4掩膜1：P阱光刻P-wellP-well

N+

N+

P+

P+

N+

P+N-SiP2023/6/4具體步驟如下：1．生長二氧化硅（濕法氧化）：Si(固體)+2H2OSiO2（固體）+2H22023/6/4氧化2023/6/42．P阱光刻：涂膠腌膜對準曝光光源顯影2023/6/42023/6/4硼摻雜（離子注入）刻蝕（等離子體刻蝕）去膠P+去除氧化膜P-well3．P阱摻雜：2023/6/42023/6/4離子源高壓電源電流積分器離子束2023/6/4掩膜2：光刻有源區(qū)有源區(qū)：nMOS、PMOS

晶體管形成的區(qū)域P+N+N+P+N-SiP-wellP-wellP-well淀積氮化硅光刻有源區(qū)場區(qū)氧化去除有源區(qū)氮化硅及二氧化硅SiO2隔離島2023/6/4有源區(qū)depositednitridelayer有源區(qū)光刻板N型p型MOS制作區(qū)域(漏-柵-源)2023/6/4P-well1.淀積氮化硅：氧化膜生長（濕法氧化）P-well氮化膜生長P-well涂膠P-well對版曝光有源區(qū)光刻板2.光刻有源區(qū)：2023/6/4P-well顯影P-well氮化硅刻蝕去膠3.場區(qū)氧化：P-well場區(qū)氧化（濕法氧化）P-well去除氮化硅薄膜及有源區(qū)SiO22023/6/4掩膜3：光刻多晶硅P-well去除氮化硅薄膜及有源區(qū)SiO2P-wellP+N+N+P+N-SiP-well柵極氧化膜多晶硅柵極生長柵極氧化膜淀積多晶硅光刻多晶硅2023/6/4P-well生長柵極氧化膜P-well淀積多晶硅P-well涂膠光刻多晶硅光刻板P-well多晶硅刻蝕2023/6/4掩膜4

：P+區(qū)光刻

1、P+區(qū)光刻

2、離子注入B+，柵區(qū)有多晶硅做掩蔽，稱為硅柵自對準工藝。

3、去膠P-wellP+N+N+P+N-SiP-wellP-wellP+P+2023/6/4P-wellP+P-wellP+P+硼離子注入去膠2023/6/4掩膜5

：N+區(qū)光刻

1、N+區(qū)光刻

2、離子注入P+，柵區(qū)有多晶硅做掩蔽，稱為硅柵自對準工藝。

3、去膠P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+2023/6/4P-wellN+P-wellP+P+磷離子注入去膠P+P+N+N+2023/6/4掩膜6

：光刻接觸孔1、淀積PSG.2、光刻接觸孔3、刻蝕接觸孔P-wellP+N+N+P+N-SiP-wellP-wellP+P+N+N+磷硅玻璃（PSG)2023/6/4掩膜6

：光刻接觸孔P-wellP+P+N+N+淀積PSGP-wellP+P+N+N+光刻接觸孔P-wellP+P+N+N+刻蝕接觸孔P-wellP+P+N+N+去膠2023/6/42023/6/4掩膜7

：光刻鋁線1、淀積鋁.2、光刻鋁3、去膠P-wellP-wellP+P+N+N+2023/6/4P-wellP+P+N+N+鋁線PSG場氧柵極氧化膜P+區(qū)P-wellN-型硅極板多晶硅N+區(qū)2023/6/4Example:Intel0.25micronProcess5metallayersTi/Al-Cu/Ti/TiNPolysilicondielectric2023/6/4InterconnectImpactonChip2023/6/4掩膜8

：刻鈍化孔CircuitPADCHIP雙阱標準CMOS工藝P+p-epipwellnwellp+n+gateoxideAl(Cu)tungstenSiO2SiO2TiSi2fieldoxide增加器件密度防止寄生晶體管效應（閂鎖效應）p-epiP阱n+STITiSi2STI深亞微米CMOS晶體管結構STISTISTIN阱n-n+n-p+p-p+p-源/漏擴展區(qū)淺槽隔離側墻多晶硅硅化物2023/6/4功耗驅動能力CMOS雙極型Bi-CMOSBiCMOS集成電路工藝2023/6/4BiCMOS工藝分類以CMOS工藝為基礎的BiCMOS工藝以雙極工藝為基礎的BiCMOS工藝。2023/6/4以P阱CMOS工藝為基礎的BiCMOS工藝NPN晶體管電流增益??；集電極的串聯(lián)電阻很大;NPN管C極只能接固定電位，從而限制了NPN管的使用2023/6/4以N阱CMOS工藝為基礎的BiCMOS工藝NPN具有較薄的基區(qū)，提高了其性能；N阱使得NPN管C極與襯底隔開，可根據(jù)電路需要接電位集電極串聯(lián)電阻還是太大，影響雙極器件的驅動能力在現(xiàn)有N阱CMOS工藝上增加一塊掩膜板2023/6/4

以N阱CMOS工藝為基礎的改進BiCMOS工藝使NPN管的集電極串聯(lián)電阻減小56倍；使CMOS器件的抗閂鎖性能大大提高2023/6/4三、后部封裝（在另外廠房）（1）背面減?。?）切片（3）粘片（4）壓焊：金