EDA課程設(shè)計(jì)多功能電子鬧鐘

摘要：本文講述一種基于EDA技術(shù)和數(shù)字電路的基礎(chǔ)知識(shí)設(shè)計(jì)一個(gè)具有時(shí)鐘功能和鬧鈴功能的數(shù)字時(shí)鐘?？赏瓿赡辍⒃?、日、時(shí)、分、秒的正常切換顯示，并具有校時(shí)功能和鬧鐘功能。該系統(tǒng)以QuartusⅡ?yàn)槠脚_(tái)，采用自頂向下、模塊化的編程設(shè)計(jì)方法。整個(gè)系統(tǒng)主要包括計(jì)時(shí)校時(shí)模塊、鬧鐘模塊、日歷模塊，各個(gè)模塊的源程序代碼采用HDL硬件描述語(yǔ)言設(shè)計(jì)，然后進(jìn)行仿真。關(guān)鍵字：QuartusⅡ軟件；數(shù)字鐘；模塊化；HDL硬件語(yǔ)言。Summary:ThispaperisbasedontheEDAtechnologyandthebasicknowledgeofdigitalcircuittodesignadigitalclock,thathasclockfunctionandalarmfunction.Itcanbefinishedtimeanddateswitchdisplay.ThesystemusesQuartusⅡasplatform,usingtop-downdesignmethodandmodularprogrammingdesignideas.Thewholesystemincludestimingcalibrationmodule,alarmmoduleandacalendarmodule.eachmoduleofthesourcecodeusesHDLhardwaredescriptionlanguagetodesignandsimulate.Keyword:QuartusIISoftware;DigitalClock;Modular;HDLHardwareLanguage.

目錄TOC\o"1-3"\h\u2882前言 II系列為平臺(tái)，用VerilogHDL語(yǔ)言編寫源程序，然后用QuartueⅡ軟件仿真。經(jīng)過(guò)為期2周的不懈努力，目前基本達(dá)到了預(yù)期的要求，能夠?qū)崿F(xiàn)電子鬧鐘的功能。4.2設(shè)計(jì)收獲與體會(huì)本次課程設(shè)計(jì)由于沒(méi)有硬件平臺(tái)用于測(cè)試，故只用QuartueⅡ軟件進(jìn)行了功能仿真。通過(guò)仿真驗(yàn)證，本次設(shè)計(jì)的電子鬧鐘基本能完成設(shè)計(jì)之初的任務(wù)要求，但在一些細(xì)節(jié)方面沒(méi)有達(dá)到預(yù)期效果。同時(shí)因?yàn)檎莆罩R(shí)有限，有要求的部分功能未能實(shí)現(xiàn)，在此只能寄希望于以后的學(xué)習(xí)中，能更好的掌握應(yīng)有知識(shí)。通過(guò)本次兩周的課程設(shè)計(jì)，對(duì)課堂上所講的EDA技術(shù)知識(shí)進(jìn)行了實(shí)踐應(yīng)用，更進(jìn)一步了解到EDA技術(shù)的實(shí)用性，同時(shí)也熟悉了QuartueⅡ軟件的使用方法，以及如何使用VerilogHDL語(yǔ)言編程，通過(guò)教材的程序認(rèn)知，很好的把握了硬件語(yǔ)言編程程序的方式方法，為日后的學(xué)習(xí)、應(yīng)用打下了良好的基礎(chǔ)。另一方面也發(fā)現(xiàn)自己有所不足，對(duì)于硬件語(yǔ)言的語(yǔ)句熟悉度還有待提高。本次課程設(shè)計(jì)，通過(guò)查閱資料，了解到很多教材上沒(méi)有學(xué)習(xí)到的知識(shí)，這點(diǎn)很好的說(shuō)明了學(xué)習(xí)一門課程，應(yīng)該通過(guò)多方面的參考，才能更好的全面的掌握該門課程的知識(shí)。由于個(gè)人能力有限，設(shè)計(jì)過(guò)程中難免遇到困難，但都在老師和同學(xué)的幫助下得到了解決，使得設(shè)計(jì)能順利完成，將理論變成了現(xiàn)實(shí)。同時(shí)也理解到團(tuán)隊(duì)的力量是強(qiáng)大的，對(duì)今后的學(xué)習(xí)工作有很深的意義。最后，在此對(duì)在設(shè)計(jì)過(guò)程中給予我?guī)椭睦蠋熀屯瑢W(xué)表示衷心的感謝！參考文獻(xiàn)[1]王金明.數(shù)字系統(tǒng)設(shè)計(jì)與VerilogHDL（第四版）.北京：電子工業(yè)出版社，2011[2]王金明，周順.數(shù)字系統(tǒng)設(shè)計(jì)與VHDL.北京：電子工業(yè)出版社，2010[3]夏宇聞.verilog數(shù)字系統(tǒng)設(shè)計(jì)教程.北京：航空航天大學(xué)出版社，2008[4]吳繼華,王誠(chéng).AlteraFPGA/CPLD設(shè)計(jì).北京：人民郵電出版社，2005[5]潘松，黃繼業(yè).EDA技術(shù)實(shí)用教程（第三版）.北京：科學(xué)出版社，2006附錄各模塊源程序代碼1.分頻模塊源程序如下：/*fenpin.v:時(shí)鐘分頻到1HZ。clk50m為輸入的50MHZ時(shí)鐘；Clk_1hz為分頻得到的1HZ時(shí)鐘*/modulefenpin(clk50m,clk_1hz);inputclk50m;outputclk_1hz;regclk_1hz;reg[25:0]counter_1hz;always@(posedgeclk50m)beginif(counter_1hz==500000000)begincounter_1hz<=0;clk_1hz=~clk_1hz;endelsecounter_1hz<=counter_1hz+1'b1;endendmodule2.鬧鈴模塊源程序如下：/*alarm.v:鬧鈴模塊；alarmon:鬧鈴是否打開(kāi)，2'b00:不打開(kāi)；2'b01:鬧鐘；alarmout:鬧鈴聲音輸出*/modulealarm(clk50m,alarmon,alarmout,reset);input[1:0]alarmon;inputclk50m,reset;outputregalarmout;reg[15:0]counter_1k;wireclk_1k;assignclk_1k=counter_1k[15];always@(posedgeclk50m)beginif(counter_1k==50000)counter_1k<=0;elsecounter_1k<=counter_1k+1'b1;endwireddd_du_out,ddd_out;sound_ddd_duddd_du(clk_1k,alarmon[1],ddd_du_out);sound_dddddd(clk_1k,alarmon[0],ddd_out);alwaysbeginif(!reset)beginif(alarmon[0]==1'b1)alarmout=ddd_out;elseif(alarmon==2'b10)alarmout=ddd_du_out;elsealarmout=0;endelsealarmout=0;endendmodule鬧鐘時(shí)間設(shè)定模塊源程序如下：/*alarm_time.v:鬧鐘時(shí)間設(shè)定模塊；enable:使能信號(hào)；inc：對(duì)選中的信號(hào)自增；sel:在時(shí)分間切換選擇10：時(shí)；01分*/modulealarm_time(clk_1hz,enable,sel,inc,basetime,alarmouttime,alarm_on,reset);inputclk_1hz,enable,inc,reset;input[1:0]sel;input[4*5-1:0]basetime;outputregalarm_on;output[4*4-1:0]alarmouttime;reg[3:0]hour1,hour0,minu1,minu0;always@(posedgeincorposedgereset)beginif(reset)begin{hour1,hour0,minu1,minu0}<=16'h0;endelsebeginif(enable)beginif(sel==2'b10)beginif({hour1,hour0}==8'h23){hour1,hour0}<=8'h00;elseif(hour0==9)beginhour0<=0;hour1<=hour1+1'b1;endelsehour0<=hour0+1'b1;endelseif(sel==2'b01)beginif({minu1,minu0}==8'h59){minu1,minu0}<=8'h00;elseif(minu0==4'h9)beginminu0<=4'h0;minu1<=minu1+4'h1;endelseminu0<=minu0+4'h1;endelse{hour1,hour0,minu1,minu0}<=16'h0;endendendalwaysbeginif(({hour1,hour0,minu1,minu0}==basetime[(4*5-1):4])&&(basetime[3:0<2]))alarm_on=1'b1;elsealarm_on=1'b0;endassignalarmouttime={hour1,hour0,minu1,minu0};endmodule4.譯碼顯示模塊源程序如下：/*led.v：led譯碼顯示模塊*/moduleled(datain,dotin,ledout);parameterINWIDTH=4;parameterOUTWIDTH=8;input[INWIDTH-1:0]datain;inputdotin;output[OUTWIDTH-1:0]ledout;reg[OUTWIDTH-2:0]dataout;wiredotout;assignledout[OUTWIDTH-1:1]=dataout;assignledout[0]=dotout;assigndotout=dotin;alwaysbegincase(datain)0:dataout<=7'b1000000;1:dataout<=7'b1111001;2:dataout<=7'b0100100;3:dataout<=7'b0110000;4:dataout<=7'b0011001;5:dataout<=7'b0010010;6:dataout<=7'b0000010;7:dataout<=7'b1111000;8:dataout<=7'b0000000;9:dataout<=7'b0010000;10:dataout<=7'b0001000;11:dataout<=7'b0000011;12:dataout<=7'b1000110;13:dataout<=7'b0100001;14:dataout<=7'b0000110;15:dataout<=7'b0001110;default:dataout<=7'b1000000;endcaseendendmodule5.輸出解碼模塊源代碼如下：/*bitsel.v:將輸出解碼成對(duì)時(shí)、分、秒的選擇；alarmmode:是否是在鬧鐘設(shè)置模式；checkmode:是否是在時(shí)間調(diào)整模塊*/modulebitsel(alarmmode,checkmode,sel,selcode,reset);inputalarmmode,checkmode,sel,reset;outputreg[2:0]selcode;reg[2:0]check_code;reg[1:0]alarm_code;always@(negedgeselorposedgereset)beginif(reset)check_code<=3'b000;elsebegincase(check_code)3'b000:check_code<=3'b001;3'b001:check_code<=3'b010;3'b010:check_code<=3'b100;3'b100:check_code<=3'b001;default:check_code<=3'b000;endcaseendendalways@(negedgeselorposedgereset)beginif(reset)alarm_code<=2'b00;elsebegincase(alarm_code)2'b00:alarm_code<=2'b01;2'b01:alarm_code<=2'b10;2'b10:alarm_code<=2'b01;default:alarm_code<=2'b00;endcaseendendalwaysbeginif(alarmmode^checkmode)beginif(checkmode)selcode=checkmode;elseselcode={alarm_code,1'b0};endelseselcode=3'b000;endendmodule6.計(jì)時(shí)模塊源程序如下：/*counter_time.v：計(jì)時(shí)模塊，并留有調(diào)整接口；check：調(diào)整信號(hào)，3位，分別調(diào)整時(shí)分秒；hour1，hour0，minu1，minu0，sec1，sec0：輸出的計(jì)時(shí)時(shí)鐘；alarmout：整點(diǎn)報(bào)時(shí)輸出*/modulecounter_time(clk_1hz,check,inc,hour1,hour0,minu1,minu0,sec1,sec0,alarmout,reset);inputclk_1hz,inc,reset;input[2:0]check;output[3:0]hour1,hour0,minu1,minu0,sec1,sec0;outputregalarmout;regclk_1hz_md;wire[6:0]carryclk;reg[5:0]incplus;ire[5:0]carrybit;wire[3:0]adderout0,adderout1,adderout2,adderout3,adderout4,adderout5;wire[3:0]timerout0,timerout1,timerout2,timerout3,timerout4,timerout5;hexcountercounter_sel0(carryclk[0],reset,4'd9,4'b0,timerout0,carrybit[0]);hexcountercounter_sel1(carryclk[1],reset,4'd5,4'b0,timerout1,carrybit[1]);hexcountercounter_minu0(carryclk[2],reset,4'd9,4'b0,timerout2,carrybit[2]);hexcountercounter_minu1(carryclk[3],reset,4'd5,4'b0,timerout3,carrybit[3]);wire[3:0]hour0max;assignhour0max=(timerout5==4'h2)?(4'h3):(4'h9);hexcountercounter_hour0(carryclk[4],reset,hour0max,4'b0,timerout4,carrybit[4]);hexcountercounter_hour1(carryclk[5],reset,4'd2,4'b0,timerout5,carrybit[5]);assigncarryclk[0]=clk_1hz_md|incplus[0];assigncarryclk[1]=carrybit[0]|incplus[1];assigncarryclk[2]=carrybit[1]|incplus[2];assigncarryclk[3]=carrybit[2]|incplus[3];assigncarryclk[4]=carrybit[3]|incplus[4];assigncarryclk[5]=carrybit[4]|incplus[5];alwaysbegincase(check)3'b001:beginclk_1hz_md=0;incplus={5'b00000,inc};end3'b010:beginclk_1hz_md=0;incplus={3'b000,inc,2'b00};end3'b100:beginclk_1hz_md=0;incplus={1'b0,inc,4'b000};enddefault:beginincplus=6'b000000;clk_1hz_md=clk_1hz;endendcaseendalwaysbeginif((timerout3==0)&&(timerout2==0)&&(timerout1<2))alarmout=1;elsealarmout=0;endassignhour1=timerout5;assignhour0=timerout4;assignminu1=timerout3;assignminu0=timerout2;assignsec1=timerout1;assignsec0=timerout0;endmodule/*hexcounter.v十六進(jìn)制計(jì)數(shù)器*/modulehexcounter(clk,set,max,setdata,dataout,carryout);inputclk,set;input[3:0]max,setdata;outputcarryout;output[3:0]dataout;reg[3:0]counter;regcarrybit;assigncarryout=carrybit;assigndataout=counter;always@(posedgeclkorposedgeset)beginif(set)begincounter<=setdata;carrybit<=0;endelsebeginif((counter==max)||(counter>max))begincounter<=0;carrybit<=1;endelsebeginounter<=counter+1'b1;carrybit<=0;endendendendmodule7.鬧鈴聲發(fā)生模塊源程序如下：/*sound_beep.vSHORTSTOP:兩聲嘀聲間的間隔；LONGSTOP:連續(xù)三生嘀后的時(shí)間間隔。*/modulesound_beep(clk_1k,on,out);parameterSOUNDSPACE=300;parameterSHORTSTOP=200;parameterLONGSTOP=500;inputclk_1k,on;outputregout;regsound;always@(posedgeclk_1k)beginsound=~sound;endreg[10:0]mscount;always@(posedgeclk_1k)beginif(mscount==(SOUNDSPACE*3+SHORTSTOP*2+LONGSTOP)-1)mscount<=0;elsemscount<=mscount+1'b1;endalways@(negedgeclk_1k)beginif(on)beginif((mscount>=0)&&(mscount<SOUNDSPACE))out<=sound;elseif((mscount>=SOUNDSPACE)&&(mscount<(SOUNDSPACE+SHORTSTOP)))out<=0;elseif((mscount>=(SOUNDSPACE+SHORTSTOP))&&(mscount<(SOUNDSPACE+SHORTSTOP)+SOUNDSPACE))out<=sound;elseif((mscount>=(SOUNDSPACE+SHORTSTOP)+SOUNDSPACE)&&(mscount<(SOUNDSPACE+SHORTSTOP)*2))out<=0;elseif((mscount>=(SOUNDSPACE+SHORTSTOP)*2)&&(mscount<((SOUNDSPACE+SHORTSTOP)*2)+SOUNDSPACE))out<=sound;elseout<=0;endelseout<=0;endendmodule8.頂層模塊源程序如下：/*clock.vmode:模式選擇0：計(jì)時(shí)模式1：設(shè)置鬧鐘模式；mcheck:手動(dòng)調(diào)整時(shí)間；turn:時(shí)、分選擇；change:對(duì)選擇的數(shù)據(jù)調(diào)整；alert：鬧鐘輸出；ld_alert:是否設(shè)置了鬧鐘*/moduleclock(clk50m,mode,turn,change,mreset,led_hour1,led_hour0,led_minu1,led_minu0,led_sec1,led_sec0,alert,ld_alert,ld_check,ld_hour,ld_min,le_sec);inputclk50m,mode,turn,change,mreset;outputalert,ld_alert,ld_check,ld_hour,ld_min,le_sec;output[7:0]led_hour1,led_hour0,led_minu1,led_minu0,led_sec1,led_sec0;reg[1:0]modestate;wirenowmoud,ischecking;assign{nowmode,ischecking}=modestate;always@(negedgemode)begincase(modestate)2'b00:modestate<=2'b10;2'b10:modestate<=2'b01;2'b01:modestate<=2'b00;default:modestate<=2'b00;endcaseendwirereset,clk_1hz;switch#(8)rmjitter(clk50m,mreset,reset);clk50mtolgen1hz(clk50m,clk_1hz);wire[2:0]selcode;bitselseldecoder(mowstate,ischecking,turn,selcode,reset);wire[3:0]clocktime0,clocktime1,clocktime2,clocktime3,clocktime4,clocktime5;wireclockalarmon;wire[2:0]counterselcode;assigncounterselcode=(modestate==2'b01)?selcod