飛思卡爾后備資料 看

HCS12

Overview8

&

16-Bit

MicrocontrollerDivisionMain

Features:16-bit

HCS12

CPU–

Upward

compatible

with

HC11/

12instruction

setInterrupt

stacking

and

programmer’smodel

identical

to

HC11/

1220-bit

ALUInstruction

pipeEnhanced

indexed

addressingSIM

(System

integration

module)MEBI

(Multiplexed

External

BusInterface)MMC

(Module

Mapping

Control)INT

(Interrupt

control)BKP

(Breakpoints)BDM

(Background

Debug

Mode)Clocks

and

Reset

Generator

(CRG)-

low

current

oscillator,

PLL,reset,

clocks,

COP

watchdog,Real

time

interrupt,

clock

monitoringMemorySplit

Gate

Flash

EEPROM

(paged)Split

Gate

EEPROM(word

write,

2

word

erase)zerowaitstate

RAMPeripheralsEnhanced

Serial

Communications

Interface

(SCI)Serial

Peripheral

interface

(SPI)1M

bit

persecond,

CAN

2.0

A,

B

msCANmodule

(with

paged

message

buffers)Universal

Serial

Bus

2.0

(USB)

interfaceByte

Data

Link

Controller(BDLC)Inter-IC

Bus

(IIC)10-bit

Analog-to-Digital

ConverterStandard

8

channel

TimerEnhanced

Capture

Timer

(ECT)PWM

moduleStepper

Motor

controllerLCD

controller

and

more

on

the

way!On-chip

Voltage

Regulator2.25to2.75V

Digital

Supply

Voltage

generatedusing

an

internal

Voltage

Regulator4.75V

to

5.25V

Analog

and

I/O

Supply

VoltageTechnology:

0.25

micron

CMOS50

MHz

CPU

equivalent

to

25MHz

busoperation

(66/33MHz

in

design)MC9S12DP256HCS12

Building

Blocks

Internal

Bus

SCI1P

W

M8C

H

A

NECT8CHAN256

KFLASEEPROM12

KSRAMATD1HCS12

CPUBKP

INT

MMI4

KB

Y

T

E

SE

E

P

R

O

MS

IMmsCAN3msCAN2msCAN1SCI0msCAN0orBDLCmsCAN4orIICSPI

2

SPI

1or

orPWM

PWMCH

CH4

-

7

0

-

3SPI

0ATD0CM

BDM

MEBIPLLPITCRGPIM

VREG

HCS12

CPU

Core&

SystemIntegration

Module

Support

Modules:

Vreg

&

Clocks

andReset

Generator

Memories:

Flash,RAM,

EEPROM

Peripherals:Comms

interfaces,ATD,

Timer,

etc.HCS12

DocumentationDevice

User

Guide

MC

9

S

12

DP

256

DeviceUserGuide

(9

S

12

DP256UG/D)

[1

Mb]HCS

12

V

1

.5

Core

UserGuide

(S

12

CPU

15

UG/D)

[6

Mb]Block

User

Guides

PIM_9

DP

256

Block

User(9

S

12

DP256PIMUG/D)FTS

256

K

Block

User(S

12

FTS

256

KUG/D)EETS

4

KBlock

User(S

12

EETS

4

KUG/D)CRG

Block

User(S

12

CRGUG/D)GuideGuideGuideGuideECT_16

B

8

C

Block

User

GuideGuideGuideGuideGuideGuideVREG

Block

User

Guide(S

12

ECT

16

B

8

CUG/D)ATD_10

B

16

C

Block

User(S

12

ATD

10

B

16

CUG/D)

[6

Mb]SCI

BlockUser(S

12

SCIUG/D)SPI

Block

User(S

12

SPIUG/D)PWM_8

B

8

C

Block

User(S

12

PWM

8

B

8

CUG/D)MSCAN

Block

User(S

12

MSCANUG/D)(S12VREGUG/D)Watch

out

for

the

Rev

Number

of

each

Guide

-

there

is

a

list

in

the

Device

User

Guide

ofwhichrev

was

appropriate

when

the

device

was

created.Click

here

to

learn

how

to

receive

up-to-date

technical

documentationCPU

Core(Programming

Model)Core

Features

(1

of

2)HCS12

has

identical

programmers

model

to

M68HC11/M68HC12???No

new

registersNo

changes

in

interrupt

stacking

orderMuxed

and

non-muxed

external

interfacesPossible

to

reuse

existing

software

source

code---Note:

timing

loops

change

due

to

new

clock

frequency,Byte

counts

and

instruction

cycle

times.Almost

all

peripheral

drivers

will

require

updatingPerformance

improvement

when

using

new

instructionsReduced

interrupt

latencyIncreased

math

speedIncreased

performance??Instruction

Queue

data

to

increase

performance

Instructions

execute

faster

while

remaining

deterministicCore

Features

(2

of

2)HC11

instruction

set

with

extra

instructions

designed

with

compilers

in

mind:New

instructions

and

addressing

modes

to

support

high

levellanguages.*?Added?addressingStack

pointer

and

program

counter

offset

indexed?11

math

instructions?Longbranch

instruction(16

bit

offset)?Move

instruction

(memory

to

memory)?Min

/

max

functions?Bit

manipulations

for

entire

memory

map?Exchange/

transfer?Table

look-up

and

interpolate

function?Looping

construct?Fuzzy

logic

instructions*

MC68HC12

and

HCS12

have

Identical

Instruction

Set.HCS12

Programmers

Model68HC11

=

68HC12

=

HCS12

Programmers

ModelCarry/Borrow

(From

MSB)OverflowZeroNegative

(MSB

=

1)I-Interrupt

MaskHalfCarry

(For

BCD)X-Interrupt

MaskSTOP

Disable15SP0Stack

PointerPC0Program

Counter7SXHI

NZV0CCondition

Codes

Register7A07B08-Bit

Accumulators

A

and

B15D0or

16-Bit

Double

Accumulator

D15X0Index

Register

X15Y0Index

Register

YSource

code

compatibleIdentical

stack

frame◆◆0

155

PPAGE

**

PPAGE

used

by

CALL&Return

To

Call(RTC).HC05

/HC08(/pHaCgSe21ed

HC(S)12oHCn0l8y/)HCS12Condition

Code

RegisterS

-

Disables

STOP

instruction

when

set.-

set

by

unmaskable

XIRQI

-

Masks

interrupt

request

from

allIRQ

level

sources

(

both

external

and

internal

)when

set.-

set

byunmasked

I

level

requestor

unmasked

XIRQMASKING

BITSARITHMETIC

BITSReflect

results

of

instruction

execution.C

-

Carry/Borrow

from

MSBunsigned

arithmeticX

-

Masks

XIRQ

request

when

set.-

set

by

hardware

reset,

cleared

by

software.

V

-

2"s

complement

overflow

indicationsigned

arithmeticZ

-

Zero

resultN

-

Negative

(

follows

MS

Bit

of

result

)H

-

Half

Carryfrom

bit

3to

bit

4ADD

operations

onlyS

X

H

I

N

Z

V

CHCS12

Serial

Interface

Features2

SCI

InterfacesUp

to

3

SPI

interfacesSCI

is

Asynchronous

Communication

Port13-bit

break

supportSPI

is

a

Synchronous

High

SpeedCommunication

PortModular

Architecture

allows

future

expansionSCI

&

SPI

are

similar

to

MC68HC11

withenhancementspins

may

be

configured

as

general

purpose

I/OLoop

mode

operationfor

debuggingSCI

&

SPI

have

single-wire

functionRxD0SCI0TxD0RxD

TxD

RxD

TxDMISO

MOSISCKSS

MISO

MOSISCKSSMISO

MOSISCKSSD

D

R

SPORTSMISOSPI1

MOSISCK

SSMISOSPI0

MOSISCK

SSMISOSPI2

MOSISCK

SSSCI1RxD0TxD0PinLogicDelayCounterCOMPARATORCAP./COM.

RegisterPulse

Accumulator16-Bit

Free-runningMain

TimerHold

RegisterHold

RegisterPrescalerBusClockCH116-Bit

Modulo

Down-CounterPrescaler016-bit

main

timer

with

7-bit

Prescaler8

IC/OC

channels,

4

IC

channelsbuffered16-Bit

modulus

Down-Counter

with

4-bit

prescaler

for:periodicinterrupt

time

basecontrol

IC/PA

register

latch4

8-Bit

or

2

16-bit

pulse

accumulators

with

4

8-bit

buffer

registersindependent

Interrupt

sources:

8

IC/OC,

Timer

OF,

3

PA,

MC4

inputs

withselectable

Delay

Counters

to

filter

out

spurious

signalsControlBitsResetload

RegisterMC9S12

Enhanced

Capture

TimerStandardized

interface

between

peripheralmodules

and

I/O

pads

for

all

ports

exceptA,B,E,K.Port

control

function

within

standard

peripheralmodules

has

been

removedPIMStandard

Port

features:User

Defined

"electrical"characteristics

on

a

pin

by

pinbasis:reduced

drivewired-or

modepull-ups

/downs*(*

Here

certain

precautions

are

taken such

as

ifis

enabled

pull-

up

is

allowed

but

pull-

down

is

bl->

High

FlexibilityPort

registers

relocatableinmemory

map

->

High

FlexibilityPT

0

PT

1IOC

0IOC

1IOC

4PWMPortPPW

0

PW

1

PW

2

PW

3

PW

4

PW

5

PW

6

PW

7PortSPP

0

PP

1

PP

2

PP

3

PP

4

PP

5

PP

6

PP

7PS

0

PS

1

PS

2

PS

3

PS

4

PS

5

PS

6

PS

7SCI0

Rx

DTx

DTx

DSDI/

MISOSDO/

MOSISCKSSSCI1

Rx

DSPIPH

0

PH

1PH

2PH

3

PortHPH

4Interrupt

TimerIOC

2

PortTIOC

3LogicPT

2PT

3

PT

4PH

5IOC

5PT

5PH

6IOC

6PT

6PH

7IOC

7PT

7Inter.L.PortJPJ

0

PJ

1

PJ

6PJ

7IICoSDA

SDL

Rx

CAN

CAN4Tx

CANPortMPM

0

PM

1

PM

2PM

3

PM

4

PM

5

PM

6

PM

7Tx

CANRx

CANTx

CAN

Tx

CAN

Tx

CANRx

CAN

CAN

3Rx

CAN

CAN

2BDLCCAN

0CAN

1Rx

B

Tx

B

Rx

CANNew:

PortIntegration

Module

PIMIIC

FeaturesCompatible

with

I2C

Bus

standardMulti-master

operationSoftware

programmable

for

one

of

256

different

serial

clockfrequenciesSoftware

selectable

acknowledge

bitInterrupt

driven

byte-by-byte

data

transferArbitration

lost

interrupt

with

automatic

mode

switching

frommaster

to

slaveCalling

address

identification

interruptStart

and

stop

signalgeneration/detectionRepeated

start

signal

generationAcknowledge

bit

generation/detectionBus

busy

detectionLow

power

modes

supportShared

with

msCAN

4msCAN

BusUp

to

5

ms

CAN

Modules

(ms

CAN)

3

Tx

message

buffers

each

AutomaticallyMapped5

Background

Rx

BuffersProgrammable

I/O

modesMaskable

interrupts

Programmable

loop-back

for

self

testoperation

Independent

of

the

transmission

medium(external

transceiver

is

assumed)Open

network

architectureMultimaster

conceptHigh

immunity

to

EMIShort

latency

time

for

high-priority

messa

Low

powersleepmode,

with

programmablewake

up

on

bus

activityggeessNote:

ms

CAN

0

is

multiplexed

with

BDLCms

CAN

4

is

multiplexed

with

IIC.BDLC

CONTROLLER

(J1850)SAEJ1850

Compatible10.4Kbps

VPW

bit

formatDigital

noise

filterCollision

detectionHardware

CRC

generation

&checkingReceive

and

Transmit

Block

mode

supportedSupports

4X

receive

mode

(41.6

Kbps)Digital

loopback

modeIn-frame

Response

(IFR)

Types

0,

1,

2,

and3

supported

Power-Saving

Stop

and

Wait

modes

with

AutomaticWakeup

on

Network

ActivityInterrupt

Generation

with

Vector

Lookup

TableAnalog

to

Digital

Converter8/10

Bit

Resolution.7

usec,

10-Bit

Single

Conversion

Time.Sample

Buffer

Amplifier.Programmable

Sample

Time.Left/Right

Justified,

Signed/Unsigned

Result

Data.External

Trigger

Control.Conversion

Completion

Interrupt

Generation.Analog

Input

Multiplexer

for

8

Analog

Input

Channels.Analog/Digital

Input

Pin

Multiplexing.1

to

8

Conversion

Sequence

Lengths.Continuous

Conversion

Mode.Multiple

Channel

Scans.PWM

FEATURES8

INDEPENDENT

PWM

CHANNELS

WITHPROGRAMMABLE

PERIOD

AND

DUTY

CYCLE.8-BIT

8-CHANNELS

OR

16-BIT

4-CHANNELS.DEDICATED

COUNTER

FOR

EACH

CHANNEL.FLEXIBLE

CLOCK

GENERATION(

A,

B,

SA

AND

SB

)

THAT

COVERS

WIDE

RANGE

OF

FREQUENCIES.PERIOD

AND

DUTY

CYCLE

ARE

DOUBLEBUFFERED.ALLOWS

FOR

IMMEDIATE

PWM

UPDATE.POLARITY

IS

SOFTWARE

SELECTABLE.PROGRAMMABLE

CENTER

OR

LEFT-ALIGNEDPWM

OUTPUT.EMERGENCY

SHUT

DOWNHCS12

Device

IdentificationThe

part

ID

is

located

in

two

8-bit

registers

PARTIDH

and

PARTIDL.The

read-onlyvalue

is

a

unique

part

ID

for

each

revision

of

the

die.The

codingis

as

follows:Bit

15-12:

Major

family

identifierBit

11-8:Bit

7-4:Bit

3-0:Minor

family

identifierMajor

mask

set

revision

number

including

FAB

transfersMinor

-

non

full

-

mask

set

revisionThe

device

memory

sizes

are

located

in

two

8-bit

registers

MEMSIZ0

andMEMSIZ1.Crystal

oscillator

(OSC)Colpitts

with

translated

GND

(as

per

HC12D-

Family)or

traditional

Pierce

configurationsCrystal

Monitor

(CM)same

as

on

HC12D-FamilyClock

Quality

Checker(CQC)ensures

valid

clock

for

operationPhase

Locked

Loop

(PLL)same

as

on

HC12D-FamilySelf

Clock

Mode

with

internal

oscillatorSystem

Clocks

Generator

(CGEN)simplified

clock chain:Core

clock

=

PLLCLK

or

OSCCLKPeripherals

clock

=

PLLCLK/2

or

OSCCLK/2(25%

duty)ECLK

=

PLLCLK/2

or

OSCCLK/2

(50%

duty)no

Slow

Mode

ClockSystem

Reset

Generator

(RGEN)same

Reset

functionality

as

on

HC12D-Family:Reset

by

POR,COP,ext.

Reset,

Clock

MonitorReal

Time

Interrupt

(RTI)

-

slightly

different

divider

chaiWatchdog

(COP)

-

slightly

different

divider

chainLOW

POWER

OSCILLATORSUPPORTS

OPERATION

UP

TO

33

MHzCRGOSCPLLCMRTICOPCGENPORRGENRegisters&ControlEXTALXTALVDDPLLXFCVSSPLLRESETInternalBusInterfaceMC9S12

Clocks

&

Reset

Gen

(CRG)CQCPower

Saving

Design

Features:Low

power

Oscillator

design

(Engineered

to

avoid

power-wasting

harmonics)User

Configurable

Low

Power

Peripheral

modesRUN

Mode

(full

operation):65

mA

max

-

However

peripherals

automatically

shut

down

if

not

in

useWAIT

Mode

(CPU

sleeping):Peripheral

modules

can

be

configured

in

power

conservation

mode40

mA

max

with

all

modules

enabled5

mA

max

with

only

Real

Time

interrupt

enabledSTOP

Mode

(All

modules

stopped

-Oscetc):30uA

*

TypicalPseudo

STOP

Mode

(All

modules

stopped):350uA

*

Typ

-

However

Osc

runs

in

low

power

mode

enabling

wake-up

as

fast

as

in

WAIT

mode*At

27oC.MC9S12

Low

Power

Modes:HCS12

ResetsPOR

(power-on

reset)Special

delayed

reset

to

allow

oscillator

tostabilize.

Does

not

replace

LVI

function.Thresholds:

Releases

when

Vdd2.5

goes

above2.07V,

Active

when

Vdd2.5

goesbelow

0.97V.Clock

quality

check

window

is

50K

self-clockcyclesIf

oscillator

amplitude

and

freq.

are

sufficient

fo4096

cycles

to

be

detected

during

a

quality

check

window

resetis

exited

using

the

XTALclock.Up

to

50

quality

check

windows

can

occur

ifoscillator

is

slow

to

start.

After

50

unsuccessful

cycles

SelfClock

Mode

is

entered.??POR

bit

can

be

checked

for

cause

of

last

reset.POR

bit

can

only

be

cleared

by

software.Crystal

Monitor

Function:Detects

crystal

failure

and

takes

user-specified

action

-

bad

clock

detect.Clock

Quality

Checker:Performs

a

window

check

on

the

oscillator

to

ensure

that

the

MCU

only

executesfrom

a

stable

clock

-

good

clock

detect.Self

Clock

Mode:Limited

operation

still

possible

even

with

temporary

crystal

problemallows

controlled

shut-down

in

event

of

oscillator

failureallows

for

slow

start-up

of

crystal

oscillatorsFlexible

Watchdog:Can

be

used

as

“windowed

w/dog”

-

(eg

refresh

only

between

75-100%

of

period)-

further

reduces

possibility

of

code

run-awayIndependent

from

PLL

(clocked

directly

from

crystal)

-

secure

even

if

PLL

failsFurther

Reading:AN2201/D:

“

Low

Battery

Cranking

Pulse

in

Automotive

Applications”(This

app

note

shows

how

the

HCS12

and

SBC

devices

can

be

used

together

in

a

cost

efficient

manner

for

Automotive

conditions).MC9S12

-

System

Integrity...BDM

on

MC9S12:Low

cost

serial

real-timeemulation

and

debugSingle

step,

Run,

or

Trace

the

application

codeOn-chip

hardware

for

multiple

breakpointsReplaces

expensive

emulator

or

bus

analyzerWorks

at

full

operating

voltage

and

frequency

rangeNon-intrusive

-

no

cumbersome

emulator

cablesIn-circuit

FLASH

programmingBDM

Development

ToolsHighly

Flexible

Flash:5

volt

FLASH

-

no

externalchargepump

requiredMarket-leading

Flash

Granularity

-

512B

Flash

Erase

/

2B

ProgramVirtual

EEPROM

implementation

possible

for

EE

extension4

independently

programmable

Flash

SegmentsCan

erase

one

block

whilst

readinganotherHigh

Speed

Programming:Fast

Flash

Page

Erase

-

20ms

(512bytes)Can

program

16

bits

in

20usTotal

Program

Time

for

128K

Code

down

to:

<5seconds!(App

note

AN2204

"Fast

NVM

Programming

for

the

MC9S12DP256"

is

now

published)Efficient

End

Of