EDA試驗(yàn)-數(shù)字時(shí)鐘實(shí)驗(yàn)報(bào)告

EDA試驗(yàn)——數(shù)字時(shí)鐘實(shí)驗(yàn)?zāi)康氖煜ぴ贓DA平臺(tái)上進(jìn)行數(shù)字電路集成設(shè)計(jì)的整個(gè)流程。掌握MaxPlus軟件下的簡(jiǎn)單的圖形、VHDL文本等輸入的設(shè)計(jì)方法。學(xué)習(xí)使用JTAG借口下載邏輯電路到可編程芯片，并能調(diào)試到芯片正常工作。實(shí)驗(yàn)原理本實(shí)驗(yàn)是實(shí)現(xiàn)數(shù)字電子鐘，直接用數(shù)字顯示時(shí)間的計(jì)時(shí)裝置。分別設(shè)計(jì)出時(shí)間設(shè)置電路，走時(shí)電路，打鈴控制電路，顯示電路。三．實(shí)驗(yàn)設(shè)計(jì)（1）在這個(gè)設(shè)計(jì)中我使用VHDL設(shè)計(jì)時(shí)間設(shè)置電路：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYcontrolISPORT(reset:INSTD_LOGIC;begend:INSTD_LOGIC;keyup:INSTD_LOGIC;enter:INSTD_LOGIC;settime:OUTSTD_LOGIC;hourhset:OUThourlset:OUTminhset:OUTminlset:OUTsechset:OUTseclset:OUTENDcontrol;ARCHITECTUREarchiOFcontrolISTYPESTATEIS(sethh,sethl,setmh,setml,setsh,setsl,ini);SIGNALadjsta:STATE;SIGNALsetmark:STD_LOGIC;SIGNALseclow,minlow,hourlow:INTEGERSIGNALsechigh,minhigh:INTEGERSIGNALhourhigh:INTEGERBEGINseclset<=seclow;sechset<=sechigh;minlset<=minlow;minhset<=minhigh;hourlset<=hourlow;hourhset<=hourhigh;settime<=setmark;mark:PROCESS(begend)beginifreset='1'thensetmark<='0';elsifbegend'eventandbegend='1'thenifsetmark='1'then setmark<='0'; else setmark<='1'; endif;endif;ENDPROCESS;normal_run:PROCESS(enter,reset)BEGINIFreset='1'THENadjsta<=ini;ELSIFenter='1'ANDenter'eventTHENcaseadjstaISWHENini=>adjsta<=sethh;WHENsethh=>adjsta<=sethl;WHENsethl=>adjsta<=setmh;WHENsetmh=>adjsta<=setml;WHENsetml=>adjsta<=setsh;WHENsetsh=>adjsta<=setsl;WHENsetsl=>adjsta<=sethh;endcase;ENDIF;ENDPROCESS;time_adjust:PROCESS(keyup)BEGINifreset='1'then hourhigh<=0; hourlow<=0; minhigh<=0; minlow<=0; sechigh<=0; seclow<=0; elsifkeyup='1'ANDkeyup'eventTHEN caseadjstaIS WHENsethh=> hourhigh<=hourhigh+1; WHENsethl=> hourlow<=hourlow+1; WHENsetmh=> minhigh<=minhigh+1; WHENsetml=> minlow<=minlow+1; WHENsetsh=> sechigh<=sechigh+1; WHENsetsl=> seclow<=seclow+1; WHENini=>NULL; endcase; endif;ENDPROCESS;ENDarchi;走時(shí)電路：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityclockisport(clk:instd_logic; settime:instd_logic; hourhset:inintegerrange0to2; hourlset:inintegerrange0to9; minhset:inintegerrange0to5; minlset:inintegerrange0to9; sechset:inintegerrange0to5; seclset:inintegerrange0to9; hourhdis:outintegerrange0to2; hourldis:outintegerrange0to9; minhdis:outintegerrange0to5; minldis:outintegerrange0to9; sechdis:outintegerrange0to5; secldis:outintegerrange0to9);endclock;architecturearchiofclockis signalseclow,minlow,hourlow:integerrange0to9; signalsechigh,minhigh:integerrange0to5; signalhourhigh:integerrange0to2;begin secldis<=seclow; sechdis<=sechigh; minldis<=minlow; minhdis<=minhigh; hourldis<=hourlow; hourhdis<=hourhigh;normal_run: process(clk,settime) begin ifsettime='1'then seclow<=seclset; sechigh<=sechset; minlow<=minlset; minhigh<=minhset; hourlow<=hourlset; hourhigh<=hourhset; else ifclk='1'andclk'eventthen ifseclow=9thenseclow<=0; ifsechigh=5thensechigh<=0; ifminlow=9thenminlow<=0; ifminhigh=5thenminhigh<=0; ifhourlow=9then hourlow<=0; hourhigh<=hourhigh+1; elsifhourlow=3andhourhigh=2then hourhigh<=0; hourlow<=0; elsehourlow<=hourlow+1; endif; elseminhigh<=minhigh+1; endif; elseminlow<=minlow+1; endif; elsesechigh<=sechigh+1; endif; elseseclow<=seclow+1; endif; endif; endif; endprocess;endarchi;打鈴控制電路：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityringisport(reset:instd_logic; alarm:outstd_logic; hourhdis:inintegerrange0to2; hourldis:inintegerrange0to9; minhdis:inintegerrange0to5; minldis:inintegerrange0to9; sechdis:inintegerrange0to5; secldis:inintegerrange0to9);endring;architecturearchiofringis constantre:integer:=2; constantstop:integer:=50;signalcnt:integerrange0to60;begin process(secldis) begin cnt<=sechdis*10+secldis; ifreset='1'thenalarm<='0'; elsif(minhdis=5andminldis=9)then ifcnt>stopandcnt<re+stopthenalarm<='0'; elsifcnt>re+stopandcnt<re*2+stopthenalarm<='1'; elsifcnt>2*re+stopandcnt<4*re+stopthenalarm<='0'; elsealarm<='1'; endif; elsealarm<='0'; endif; endprocess;endarchi;顯示電路：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityringisport(reset:instd_logic; alarm:outstd_logic; hourhdis:inintegerrange0to2; hourldis:inintegerrange0to9; minhdis:inintegerrange0to5; minldis:inintegerrange0to9; sechdis:inintegerrange0to5; secldis:inintegerrange0to9);endring;architecturearchiofringis constantre:integer:=2; constantstop:integer:=50;signalcnt:integerrange0to60;begin process(secldis) begin cnt<=sechdis*10+secldis; ifreset='1'thenalarm<='0'; elsif(minhdis=5andminldis=9)then ifcnt>stopandcnt<re+stopthenalarm<='0'; elsifcnt>re+stopandcnt<re*2+stopthenalarm<='1'; elsifcnt>2*re+stopandcnt<4*re+stopthenalarm<='0'; elsealarm<='1'; endif; elsealarm<='0'; endif; endprocess;endarchi;