微波爐控制器設(shè)計(jì)

定時(shí)器集成電路的設(shè)計(jì)根本功能復(fù)位開關(guān)：reset啟動(dòng)開關(guān)：start_cook烹調(diào)時(shí)間設(shè)置：set_time烹調(diào)時(shí)間顯示：min;sec七段碼測(cè)試：test啟動(dòng)輸出：cook信號(hào)描述CLK：外部時(shí)鐘。std_logic;RESET：復(fù)位信號(hào)，“1〞有效。std_logic;TEST：測(cè)試信號(hào)“1〞有效。std_logic;SET—TIME：時(shí)間設(shè)置“1〞有效。std_logic;DATA[15..0]：4*4BCD數(shù)碼設(shè)置〔59分59秒〕std_logic_vector(15..0);STRT—COOK：烹調(diào)開始“1〞有效。std_logic;1、cook:烹調(diào)進(jìn)行信號(hào)，接繼電器“1〞有效。std_logic;2、min_msb:std_logic_vector(1to7);3、min_lsb:std_logic_vector(1to7);4、sec_msb:std_logic_vector(1to7);5、sec_lsb:std_logic_vector(1to7);設(shè)計(jì)分析控制狀態(tài)機(jī)：工作狀態(tài)狀態(tài)轉(zhuǎn)換。數(shù)據(jù)裝入電路：根據(jù)控制信號(hào)選擇定時(shí)時(shí)間、測(cè)試數(shù)據(jù)或完成信號(hào)的裝入。定時(shí)器電路：負(fù)責(zé)完成烹調(diào)過(guò)程中的時(shí)間遞減計(jì)數(shù)和數(shù)據(jù)譯碼供應(yīng)七段數(shù)碼顯示，同時(shí)還可以提供烹調(diào)完成時(shí)間的狀態(tài)信號(hào)供控制狀態(tài)機(jī)產(chǎn)生完成信號(hào)。四、模塊設(shè)計(jì)控制狀態(tài)機(jī)設(shè)計(jì)輸入輸出信號(hào)ENTITYstate_countrolIS PORT( clk ,done,reset,test,set_time,start_cook :IN std_logic; cook,load_8888,load_clk,load_done :OUT std_logic);END;根據(jù)輸入信號(hào)和自身當(dāng)時(shí)的狀態(tài)完成狀態(tài)轉(zhuǎn)換和輸出相應(yīng)的信號(hào)。Cook：指示烹調(diào)進(jìn)行中，同時(shí)提示計(jì)時(shí)器減數(shù)。load_8888：指示LOADER裝入完成測(cè)試數(shù)據(jù)。load_clk：指示LOADER裝入設(shè)置烹調(diào)時(shí)間數(shù)據(jù)。load_done：指示LOADER裝入完成信息數(shù)據(jù)。狀態(tài)分析idle:復(fù)位狀態(tài)。lamp_test:數(shù)碼管測(cè)試狀態(tài)。set_clock：烹調(diào)時(shí)間設(shè)置狀態(tài)。Timer：減數(shù)定時(shí)狀態(tài)。done_msg：完成信息顯示狀態(tài)。程序設(shè)計(jì)libraryIEEE;useIEEE.std_logic_1164.all;ENTITYstate_countrolIS PORT( clk ,done,reset,test,set_time,start_cook :IN std_logic; cook,load_8888,load_clk,load_done :OUT std_logic);END;ARCHITECTUREaOFstate_countrolIS TYPESTATE_TYPEIS(idle,lamp_test,set_clock,timer,done_msg); SIGNALnext_state,current_state :STATE_TYPE;BEGIN PROCESS(clk,reset) BEGIN IFreset='1'THEN current_state<=idle; ELSIF(clk'EVENTANDclk='1')THENcurrent_state<=next_state;endif;endPROCESS;PROCESS(current_state,set_time,start_cook,test,done)beginnext_state<=idle;load_8888<='0';load_clk<='0';load_done<='0';cook<='0'; CASEcurrent_stateIS WHENlamp_test=>load_8888<='1';next_state<=idle;WHENset_clock=>load_clk<='1';next_state<=idle;WHENdone_msg=>load_done<='1';next_state<=idle;WHENidle=>iftest='1'thennext_state<=lamp_test;load_8888<='1';elsifset_time='1'thennext_state<=set_clock;load_clk<='1';elsifstart_cook='1'anddone='0'thennext_state<=timer;cook<='1';endif;WHENtimer=>ifdone='1'thennext_state<=done_msg;load_done<='1';elsenext_state<=timer;cook<='1';endif; ENDCASE; ENDPROCESS; ENDa;數(shù)據(jù)裝入電路設(shè)計(jì)輸入輸出信號(hào)PORT(load_8888,load_clk,load_done:IN std_logic;data:IN std_logic_vector(15downto0); load :OUT std_logic;load_val:OUT std_logic_vector(15downto0));END;數(shù)據(jù)裝入電路根據(jù)輸入信號(hào)的描述是組合邏輯電路，類似多路選擇器。數(shù)據(jù)裝入和輸出均為BCD編碼。load_8888：“1〞時(shí)，輸出測(cè)試數(shù)據(jù)。load_clk：輸出設(shè)置烹調(diào)時(shí)間數(shù)據(jù)。load_done：“1〞輸出完成信息數(shù)據(jù)。load：指示TIMER處于數(shù)據(jù)裝入狀態(tài)并裝入有效數(shù)據(jù)。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;ENTITYloaderIS PORT( load_8888,load_clk,load_done:IN std_logic;data:IN std_logic_vector(15downto0); load :OUT std_logic;load_val:OUT std_logic_vector(15downto0));END;ARCHITECTUREaOFloaderIS BEGIN PROCESS(data,load_8888,load_clk,load_done)variabletemp:std_logic_vector(2downto0); BEGIN load<=load_8888orload_doneorload_clk;temp:=load_8888&load_done&load_clk; CASEtempIS WHEN"100"=>load_val<=all_8;WHEN"010"=>load_val<=done;WHEN"001"=>load_val<=data;WHENothers=>null; ENDCASE; ENDPROCESS; ENDa;定時(shí)電路設(shè)計(jì)輸入輸出信號(hào)ENTITYtimerIS PORT(clk:IN std_logic; data:IN std_logic_vector(15downto0);down:IN std_logic;load:IN std_logic;done:out std_logic;min_msb:out std_logic_vector(1to7);min_lsb:out std_logic_vector(1to7);sec_msb:out std_logic_vector(1to7);sec_lsb:out std_logic_vector(1to7));END;定時(shí)電路根據(jù)輸入信號(hào)的描述是時(shí)序邏輯電路，主要由計(jì)數(shù)器構(gòu)成。設(shè)計(jì)方法采用例化設(shè)計(jì)法。電路具有裝入功能、逆計(jì)數(shù)功能及數(shù)據(jù)譯碼功能。Load：“1〞時(shí)，完成裝入功能。down：“1〞時(shí)，執(zhí)行逆計(jì)數(shù)功能。Done：表示烹調(diào)完成。min_msbmin_lsbsec_msbsec_lsb：用于驅(qū)動(dòng)七段數(shù)碼管顯示。注意：需要4個(gè)計(jì)數(shù)器〔counter4〕，每個(gè)計(jì)數(shù)器寬度為4。分、秒在個(gè)位“10〞進(jìn)制，在十位上“6〞進(jìn)制。如“59分：59秒〞。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYtimerIS PORT(clk:IN std_logic; data:IN std_logic_vector(15downto0);down:IN std_logic;load:IN std_logic;done:out std_logic;min_msb:out std_logic_vector(1to7);min_lsb:out std_logic_vector(1to7);sec_msb:out std_logic_vector(1to7);sec_lsb:out std_logic_vector(1to7));END;ARCHITECTUREaaOFtimerIScomponentcounter4PORT(clk:IN std_logic; cnt_f_5:IN std_logic;data_in:IN std_logic_vector(3downto0);down:IN std_logic;load:IN std_logic;zero :OUT std_logic; segs :OUT std_logic_vector(1to7));endcomponent;signalzer0,zer1,zer2,zer3:std_logic;signaldown0,down1,down2,down3:std_logic;signaldata0,data1,data2,data3:std_logic_vector(3downto0);signalis_five,is_nine:std_logic;beginis_five<='1';is_nine<='0';data3<=data(15downto12);data2<=data(11downto8);data1<=data(7downto4);data0<=data(3downto0);process(zer0,zer1,zer2,zer3,down)begindone<=zer3andzer2andzer1andzer0;down3<='0';down2<='0';down1<='0';down0<='0';if(down='1')thendown0<='1';endif;if(zer0='1')thendown1<='1';endif;if(zer1='1')thendown2<='1';endif;if(zer2='1')thendown3<='1';endif;endprocess;u3:counter4portmap(clk=>clk,cnt_f_5=>is_five,data_in=>data3,down=>down3,load=>load,zero=>zer3,segs=>min_msb);u2:counter4portmap(clk=>clk,cnt_f_5=>is_nine,data_in=>data2,down=>down2,load=>load,zero=>zer2,segs=>min_lsb);u1:counter4portmap(clk=>clk,cnt_f_5=>is_five,data_in=>data1,down=>down1,load=>load,zero=>zer1,segs=>sec_msb);u0:counter4portmap(clk=>clk,cnt_f_5=>is_nine,data_in=>data0,down=>down0,load=>load,zero=>zer0,segs=>sec_lsb);ENDaa;計(jì)數(shù)電路設(shè)計(jì)輸入輸出信號(hào)ENTITYcounter4IS PORT(clk:IN std_logic; IN std_logic;data_in:IN std_logic_vector(3downto0);down:IN std_logic;load:IN std_logic;zero :OUT std_logic; segs :OUT std_logic_vector(1to7));END;計(jì)數(shù)電路根據(jù)輸入信號(hào)的描述是時(shí)序邏輯電路。電路設(shè)計(jì)采用“例化〞設(shè)計(jì)方法。具體包括4個(gè)需要例化的元件模塊：零指示模塊〔zero_detect〕、譯碼器模塊〔bcd7〕、減法器模塊〔dec4〕、雙端口裝入存放器模塊〔dual_reg4〕。cok：“同步時(shí)鐘信號(hào)。 Load：“1〞時(shí)，且在時(shí)鐘為高電平，數(shù)據(jù)data_in被裝入到計(jì)數(shù)器；否那么，當(dāng)down為高電平，計(jì)數(shù)器開始減數(shù)。cnt_f_5：進(jìn)制設(shè)置?！?〞執(zhí)行六進(jìn)制、“0〞執(zhí)行十進(jìn)制。down：驅(qū)動(dòng)一個(gè)7段數(shù)碼管。計(jì)數(shù)器的4位輸出經(jīng)過(guò)譯碼器得到。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYcounter4IS PORT(clk:IN std_logic; cnt_f_5:IN std_logic;data_in:IN std_logic_vector(3downto0);down:IN std_logic;load:IN std_logic;zero :OUT std_logic; segs :OUT std_logic_vector(1to7));END;ARCHITECTUREaOFcounter4IScomponentzero_detectport(a:IN std_logic_vector(3downto0);zero :OUT std_logic);endcomponent;componentbcd7PORT( q:IN std_logic_vector(3downto0); segments :OUT std_logic_vector(1to7));endcomponent;componentdec4PORT( cnt_f_5:IN std_logic;dec_in:IN std_logic_vector(3downto0); dec_out :OUT std_logic_vector(3downto0));endcomponent;componentdual_reg4PORT( a:IN std_logic_vector(3downto0);b:IN std_logic_vector(3downto0);clk:IN std_logic;lda:IN std_logic;ldb:IN std_logic; q :OUT std_logic_vector(3downto0));endcomponent;signalcount:std_logic_vector(3downto0);signaltemp:std_logic_vector(3downto0); BEGINu0:zero_detectportmap(a=>count,zero=>zero);u1:bcd7portmap(q=>count,segments=>segs);u2:dec4portmap(cnt_f_5=>cnt_f_5,dec_in=>count,dec_out=>temp);u3:dual_reg4portmap(a=>data_in,b=>temp,clk=>clk,lda=>load,ldb=>down,q=>count);ENDa;零指示模塊〔zero_detect〕設(shè)計(jì)輸入輸出信號(hào)ENTITYzero_detectIS PORT(a:IN std_logic_vector(3downto0); zero :OUT std_logic);END;該電路根據(jù)輸入信號(hào)的描述是組合電路。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;ENTITYzero_detectIS PORT( a:IN std_logic_vector(3downto0); zero :OUT std_logic);END;ARCHITECTUREaOFzero_detectIS BEGIN zero<='1'WHENa="0000"else'0';ENDa;譯碼器模塊〔bcd7〕設(shè)計(jì)輸入輸出信號(hào)ENTITYbcd7IS PORT(q:IN std_logic_vector(3downto0); segments :OUT std_logic_vector(1to7));END;該電路根據(jù)輸入信號(hào)的描述是組合電路。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;ENTITYbcd7IS PORT(q:IN std_logic_vector(3downto0); segments :OUT std_logic_vector(1to7));END;ARCHITECTUREaOFbcd7IS BEGINprocess(q)BEGINcaseqisWHEN"0000"=>segments<="1111110";WHEN"0001"=>segments<="1100000";WHEN"0010"=>segments<="1011011";WHEN"0011"=>segments<="1110011";WHEN"0100"=>segments<="1100101";WHEN"0101"=>segments<="0110111";WHEN"0110"=>segments<="0111111";WHEN"0111"=>segments<="1100010";WHEN"1000"=>segments<="1111111";WHEN"1001"=>segments<="1110111";WHEN"1010"=>segments<="1111001";WHEN"1011"=>segments<="0111001";WHEN"1100"=>segments<="0101001";WHEN"1101"=>segments<="0011111";WHENothers=>segments<="0000000";endcase;endprocess;ENDa;減法器模塊〔dec4〕設(shè)計(jì)輸入輸出信號(hào)ENTITYdec4IS PORT( cnt_f_5:IN std_logic;dec_in:IN std_logic_vector(3downto0); dec_out :OUT std_logic_vector(3downto0));END;該電路根據(jù)輸入信號(hào)的描述是組合電路。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYdec4IS PORT( cnt_f_5:IN std_logic;dec_in:IN std_logic_vector(3downto0); dec_out :OUT std_logic_vector(3downto0));END;ARCHITECTUREaOFdec4ISsignalmaxval:std_logic_vector(3downto0); BEGINmaxval<="0101"WHENcnt_f_5='1'else"1001";dec_out<=maxvalWHENdec_in="0000"elsemaxval-1;ENDa;雙端口裝入存放器模塊〔dual_reg4〕設(shè)計(jì)輸入輸出信號(hào)ENTITYdual_reg4IS PORT( a:IN std_logic_vector(3downto0);b:IN std_logic_vector(3downto0);clk:IN std_logic;lda:IN std_logic;ldb:IN std_logic; q :OUT std_logic_vector(3downto0));END;該電路根據(jù)輸入信號(hào)的描述是時(shí)序電路。程序設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYdual_reg4IS PORT( a:IN std_logic_vector(3downto0);b:IN std_logic_vector(3downto0);clk:IN std_logic;lda:IN std_logic;ldb:IN std_logic; q :OUT std_logic_vector(3downto0));END;ARCHITECTUREaOFdual_reg4IS BEGINprocess(clk)beginifclk'eventandclk='1'thenif(lda='1')thenq<=a;elsif(ldb='1')thenq<=b;endif;endif;endprocess;ENDa;主電路microwave_timer設(shè)計(jì)輸入輸出信號(hào)ENTITYmicrowave_timerIS PORT(clk:IN std_logic;reset:IN std_logic; data:IN std_logic_vector(15downto0);test:IN std_logic;set_time:IN std_logic;start_cook:IN std_logic;cook:out std_logic;min_msb:out std_logic_vector(1to7);min_lsb:out std_logic_vector(1to7);sec_msb:out std_logic_vector(1to7);sec_lsb:out std_logic_vector(1to7));END;總體電路根據(jù)輸入信號(hào)的描述是時(shí)序電路。由三大模塊構(gòu)成：控制狀態(tài)機(jī)〔state_countrol〕：工作狀態(tài)狀態(tài)轉(zhuǎn)換。數(shù)據(jù)裝入電路〔loader〕：根據(jù)控制信號(hào)選擇定時(shí)時(shí)間、測(cè)試數(shù)據(jù)或完成信號(hào)的裝入。定時(shí)器電路〔timer〕：負(fù)責(zé)完成烹調(diào)過(guò)程中的時(shí)間遞減計(jì)數(shù)和數(shù)據(jù)譯碼供應(yīng)七段數(shù)碼顯示，同時(shí)還可以提供烹調(diào)完成時(shí)間的狀態(tài)信號(hào)供控制狀態(tài)機(jī)產(chǎn)生完成信號(hào)?？傮w設(shè)計(jì)方法：時(shí)序電路設(shè)計(jì)、組合電路設(shè)計(jì)。狀態(tài)機(jī)電路設(shè)計(jì)、多層例化電路設(shè)計(jì)。主程序microwave_timer設(shè)計(jì)LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;ENTITYmicrowave_timerIS PORT(clk:IN std_logic;reset:IN std_logic; data:IN std_logic_vector(15downto0);test:IN std_logic;set_time:IN std_logic;start_cook:IN std_logic;cook:out std_logic;min_msb:out std_logic_vector(1to7);min_lsb:out std_logic_vector(1to7);sec_msb:out std_logic_vector(1to7);sec_lsb:out std_logic_vector(1to7));END;ARCHITECTUREaaOFmicrowave_timerIScomponentstate_countrolPORT( clk ,done,reset,test,set_time,start_cook :IN std_logic; cook,load_8888,load_clk,load_done :OUT std_logic);endcomponent;componentloaderPORT( load_8888,load_clk,load_done:IN std_logic;data:IN std_logic_vector(15downto0); load :OUT std_logic;