同步時序線路分析和設計-2

Analysis&DesignofSynchronousSequentialLogicCircuitsDigitalLogic2ConceptsofSequentialCircuitsClassificationofSequentialCircuitsSynchronousSequentialCircuits(同步時序電路):Allflip-flopsinsystemarecontrolledbyoneglobalclocksignal.

Thatiswhatwediscussedinthischapter.AsynchronousSequentialCircuits(異步時序電路):Allflip-flopsarenotdrivenbyoneclocksignalorthereisnoclockpulseinput.Thatis,thetransitionfromonestatetoanotherisinitiatedbythechangeintheprimaryinputs;thereisnoexternalsynchronisation(無外部同步機制).DigitalLogic3ConceptsofSequentialCircuitsTwoBasicModelsMealy(米里型):TheoutputisafunctionofPresent-State&PresentInputs;Moore(摩爾型):Theoutputcanchangeonlywhenthestatechangesandhavenothingtodowiththeinputs.Outputonlydependsonpresentstates.DigitalLogic4ConceptsofSequentialCircuitsTwoTypicalApplicationsAnalysis(分析):Withgivencircuit,tellwhatdoesitdo?Design/Synthesis(設計/綜合):Givenspecificationofcircuit,developdesigns.DigitalLogic5SomeImportantConceptsDrivenEquation(ControlEquation,ExcitingEquation)(驅(qū)動方程)TheinputofFFs,suchas:J=….;K=….;CharacteristicEquation(特征方程)BelongstooneFF,suchasQn+1=D;StateEquation(狀態(tài)方程)Equationdescribingtherelationshipofpresentstate(現(xiàn)態(tài))&nextstate(次態(tài))DigitalLogic6SomeImportantConceptsStatetransitiontable(狀態(tài)轉(zhuǎn)移表)Statetransitiondiagram(狀態(tài)轉(zhuǎn)移圖)XPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)0000110110110111110011001100100010011111010/1000110110/10/10/11/01/11/11/0Input/outputDigitalLogic7SomeImportantConceptsStatetransitiontable(狀態(tài)轉(zhuǎn)移表)XPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)000011011011011111001100110010001001111101010001/111/00110/100/01011/101/11100/110/1DigitalLogic8StepsofAnalysisofSynchronousSequentialCircuitsGivenCircuitsDerivetheOutputEquation&DrivenEquationsGivetheState

Transition

Table/

diagramBuildtheStateTransitionEquationTiming

diagramExplainTheLogicFunctionThat’swhatwehaveThis’sourtargetWecaneasilygetweneedittoanalysisDigitalLogic9Example1(Analysis)(Indetail)1,Derivethedriverequation/excitationequation(驅(qū)動方程/激勵方程)accordingtocircuitdiagram所謂驅(qū)動方程,也就是觸發(fā)器輸入端的邏輯表達式.DigitalLogic10Example1(Indetail)1,Derivetheoutputequations(輸出方程)所謂輸出方程,也就是電路輸出函數(shù)的邏輯表達式DigitalLogic11Example1(Indetail)2,Derivethestateequation(狀態(tài)方程)(ornext-stateequation)byconvertingtheseexcitationequationsintoflip-flops’characteristicequations(特征方程)這就是狀態(tài)方程,根據(jù)狀態(tài)方程可以很方便地得到狀態(tài)轉(zhuǎn)移表.DigitalLogic12Example1(Indetail)3,Convertthesenext-stateequationsintostatetransitiontable(狀態(tài)轉(zhuǎn)移表)PresentState(現(xiàn)態(tài))NextState(次態(tài))YQ2nQ1nQ0nQ2n+1Q1n+1Q0n+100000100010110010101001111101000001101010111010001111100DigitalLogic13Example1(Indetail)3,Drawthestatetransitiondiagram(狀態(tài)轉(zhuǎn)移圖)PresentState(現(xiàn)態(tài))NextState(次態(tài))YQ2nQ1nQ0nQ2n+1Q1n+1Q0n+100000100010110010101001111101000001101010111010001111100001/0/0011/0111/0110/0100000/1notinnotin/1010101/0DrawSTDItisaninvalidloop(無效循環(huán))DigitalLogic14Example1(Indetail)/1010101/0思考:該系統(tǒng)是否具有自啟動(SelfStartup)功能？答案:是否定的,一旦系統(tǒng)陷入無效循環(huán),將不能恢復正常狀態(tài).3,Drawthestatetransitiondiagram(狀態(tài)轉(zhuǎn)移圖)DigitalLogic15Example1(Indetail)4,Drawtheconclusionaboutthecircuits001/0/0011/0111/0110/0100/1000有效循環(huán)的6個狀態(tài)分別是0～5這6個十進制數(shù)字的格雷碼,并且在時鐘脈沖CP的作用下,這6個狀態(tài)是按遞增規(guī)律變化的,即:000→001→011→111→110→100→000→…所以這是一個用格雷碼表示的六進制同步加法計數(shù)器.當對第6個脈沖計數(shù)時,計數(shù)器又重新從000開始計數(shù),并產(chǎn)生輸出Y＝1.DigitalLogic16Example1(Indetail)5,Furthermore,wecandrawthetimingdiagram(時序圖).Inthisexample,weassumetheoriginalstateofQ2,Q1,Q0

is000.Q2Q1Q0:000→001→011→111→110→100→000→…negativeedge/fallingedgetriggered(下降沿觸發(fā)).每一個下降沿狀態(tài)改變一次.DigitalLogic17Example1(Indetail)5,ResultDiagram1(效果圖)CPQ0Q1Q2YDigitalLogic18JustForJumpDigitalLogic19ResultDiagram(2)01ReplayDigitalLogic20Example2(Analysis)(Insteps)1,DrivenequationsandoutputequationsareasfollowedDigitalLogic21Example2(Insteps)2,Derivethestateequations1,DrivenequationsandoutputequationsareasfollowedDigitalLogic22Example2(Insteps)3,Statetransitiontable/diagramXPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)000011011011011111001100110010001001111101DigitalLogic23Example2(Insteps)XPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)000011011011011111001100110010001001111101=>PresentStateNextState/OutputX=0X=10001/111/00110/100/01011/101/11100/110/1StateTransitionTable(狀態(tài)轉(zhuǎn)移表)STT(compressedform)3,Statetransitiontable/diagramDigitalLogic24Example2(Insteps)XPresentStateNextStateYQ1(n)Q0(n)Q1(n+1)Q0(n+1)0000110110110111110011001100100010011111010/1000110110/10/10/11/01/11/11/00/1:‘/’前表示輸入X,后表示輸出Y3,Statetransitiontable/diagramDigitalLogic25Example2(Insteps)4,功能分析當X＝0時,在時鐘脈沖CP的作用下,電路的4個狀態(tài)按:00→01→10→11→00→…當X＝1時,在時鐘脈沖CP的作用下,電路的4個狀態(tài)按:00→11→10→01→00→…可見,該電路既具有遞增計數(shù)功能,又具有遞減計數(shù)功能,是一個2位二進制同步可逆計數(shù)器(2-bitup/downbinarysynchronouscounter).DigitalLogic26Example2(Insteps)5,Drawthetimingdiagram0/1000110110/10/10/11/01/11/11/0思考:Y的波形如何？DigitalLogic27Example3(Analysis)(Insteps)1,DrivenequationsandoutputequationsareasfollowedDigitalLogic28Example3(Insteps)2,DerivethestateequationsDigitalLogic29Example3(Insteps)3,Statetransitiontable/diagramPresentState(現(xiàn)態(tài))NextState(次態(tài))YQ3(n)Q2(n)Q1(n)Q3(n+1)Q2(n+1)Q1(n+1)00000100010100010011001110001001010101110011000011110001對于相對復雜的邏輯表達式,我們可通過Excel的函數(shù)工具來進行計算DigitalLogic30Example3(Insteps)3,Statetransitiontable/diagram000001010011100101110111此處,狀態(tài)圖中省略了輸出Y;狀態(tài)“111”不在有效循環(huán)中,但是,當出現(xiàn)異常狀態(tài)“111”時,在下降沿的作用下,觸發(fā)器狀態(tài)會回歸到“000”,所以,可以稱這類系統(tǒng)為“自啟動的(selfstartup)”.DigitalLogic31Example3(Insteps)4,Drawtheconclusionaboutthecircuit同步七進制的加法計數(shù)器(Modulo-7BinarySynchronousUpCounter)000001010011100101110111SomeTerms:Synchronous/Asynchronous;

Up/Down/Up-down/Bi-directional;

DigitalLogic32StepsofDesign/SynthesisofSequentialCircuitsGivenSpecifi-cationOfCircuitsResultCircuitsDerivetheOriginalStateTableOutputEquation&DrivenEquationThat’swhatwehaveThis’sourtargetHowmanystatesshouldbeinmemoryweneedittobuildcircuitsDerivetheReducedStateTable(Optional)EncodeTheStatesCheckSelf-Startup難點所在，有時還須選觸發(fā)器如不符合須重新設計DigitalLogic33Example1(Design)(Indetail)1,Generatetheoriginalstatetable(原始狀態(tài)表)設計一個按自然數(shù)順序變化的7進制Moore型同步加法計數(shù)器,計數(shù)規(guī)則為“逢七進一”,并在進一時產(chǎn)生一個進位輸出.2,Converttothereducedstatetable:本例中已最簡3,Encodestatesandselectproperflip-flops狀態(tài)已經(jīng)對應于編碼,故無須重編(此類題共性)因為有效狀態(tài)數(shù)為7,故需要觸發(fā)器數(shù)目為3.選擇下降沿觸發(fā)的JK觸發(fā)器State:000=>001=>010=>011=>100=>101=>110=>000Y:0000001DigitalLogic34Example1(Indetail)4,Derivetheoutputequation,stateequations&drivenequations001000d00001111001YQn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111dddd/1DigitalLogic35Example1(Indetail)000101d10001111001Q2(n+1)Qn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111d/0ddd/14,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic36Example1(Indetail)0001111001Q2(n+1)000101d14,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic37Example1(Indetail)0001111001Q2(n+1)000101d14,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic38Example1(Indetail)010010d10001111001Q1(n+1)Qn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111d/0d/0dd/14,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic39Example1(Indetail)110100d00001111001Q0(n+1)Qn(2,1,0)Qn+1(2,1,0)Y0000010001010001001100111000100101010111001100001111d/0d/0d/0d/14,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic40Example1(Indetail)110100d00001111001Q0(n+1)上式不滿足JK方程雛形形式,但是其不滿足僅僅表現(xiàn)為缺少對應的項:Q0n,對于這種“缺項”形式,我們可以方便地將其構(gòu)造出來.方式是:+0構(gòu)造.在本例中,如果將d看作1,也可以構(gòu)造出Q0n,但是卻犧牲了電路的簡潔性.4,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic41Example1(Indetail)可見,同步時序邏輯設計的難點即在于此步.要將卡諾圖中的形式表示為“向特征方程靠攏”的形式.同時,可以看出,對于存在無效狀態(tài)的狀態(tài)轉(zhuǎn)換表,其最終的函數(shù)表示方式可能是多種多樣的.答案并不唯一.5,Checkifsystemcanself-startup由最終真值表可知,當電路陷入異常狀態(tài)“111”,那么下一次下降沿觸發(fā)時,將進入有效狀態(tài)“000”.所以,電路具備自啟動功能.4,Derivetheoutputequation,stateequations&drivenequationsDigitalLogic42Example1(Indetail)6,DrawthecircuitdiagramDigitalLogic43Example1(Indetail)7,Sth.Shouldbementioned思考:該電路設計有什么缺陷之處？缺陷之處在于:當系統(tǒng)由異常狀態(tài)“111”跳變到“000”的時候,將同樣產(chǎn)生異常的輸出Y,可以,可以通過更改卡諾圖中的這一方格,來改變輸出電路的實現(xiàn).新的卡諾圖如下:0d=00001000001111001YDigitalLogic44Example1(Indetail)7,Sth.Shouldbementioned思考:在P37頁里,d確定為0抑或為1是否是任意的?須要受到什么因素制約嗎?須考慮系統(tǒng)能夠自啟動.系統(tǒng)是否能夠?qū)崿F(xiàn)自啟動,完全是由無效狀態(tài)下的次態(tài)決定的.DigitalLogic45Example1(Indetail)7,Sth.Shouldbementioned本題結(jié)果分析題例3思考:它們的完全一致是必然的嗎?DigitalLogic46Example2(Design)(Insteps)1,Draworiginalstatediagram(原始狀態(tài)圖)假設一位3位串行奇偶校驗電路,當電路串行地接受了三位2進制數(shù),如果其中1的個數(shù)為偶數(shù),則在收到第三位數(shù)時輸出1;其余情況下輸出0.每三位二進制數(shù)為1組,在接受到第三位數(shù)碼后,電路返回到初始狀態(tài).A0/01/0BCEDFG0/01/00/01/00/11/00/01/10/01/10/11/0DigitalLogic47Example2(Insteps)1,Generateoriginalstatetable(原始狀態(tài)表)如左表可知,狀態(tài)可化簡.因為狀態(tài)D和G等效,狀態(tài)E和F等效;所謂D和G等效的物理意義是:如果電路收到串00(A->B->D)和收到串11(A->C->G),所引發(fā)的效果將是相同的;當然,并非只有完全等效的若干組才可以化簡.(前面已討論過).PresentStateNextState/OutputX=0X=1AB/0C/0BD/0E/0CF/0G/0DA/1A/0EA/0A/1FA/0A/1GA/1A/0DigitalLogic48Example2(Insteps)2,ReducedstatetablePresentStateNextState/OutputX=0X=1AB/0C/0BD/0E/0CE/0D/0DA/1A/0EA/0A/1DigitalLogic49Example2(Insteps)3,Encodestates,

theprinciplesofencodingare:如果狀態(tài)表某些狀態(tài)在相同的輸入作用下次態(tài)相同,那么應給這些狀態(tài)相鄰的代碼;狀態(tài)表中某一狀態(tài)在不同的輸入下產(chǎn)生的不同次態(tài)應盡可能相鄰;如果狀態(tài)表中某些狀態(tài)有相同的輸出,應該盡可能安排成相鄰;狀態(tài)表中出現(xiàn)次數(shù)最多的狀態(tài)應分配為邏輯0.y3y2y10001111001EDCBA在本例中,由于狀態(tài)數(shù)目為5,所以需要3個觸發(fā)器.2^3=8>5,分配結(jié)果如右:對狀態(tài)的編碼分配沒有錯對之分,只有優(yōu)劣之別.會影響所設計電路的復雜度.DigitalLogic50Example2(Insteps)4,StateTransitionDiagram:A0/01/0BCEDFG0/01/00/01/00/11/00/01/10/01/10/11/0A0/01/0BCED0/01/01/00/00/11/00/01/1DigitalLogic51Example2(Insteps)4,StateTransitionTable:y3y2y10001111001EDCBAPS(y3y2y1)NS(y3y2y1)/ZX=0X=1000010/0110/0001ddd/dddd/d010100/0101/0011ddd/dddd/d100000/1000/0101000/0000/1110101/0100/0111ddd/dddd/dA0/01/0BCED0/01/01/00/00/11/00/01/1DigitalLogic52Example2(Insteps)4,FromSTTtoK-Map:PS(y3y2y1)NS(y3y2y1)/ZX=0X=1000010/0110/0001ddd/dddd/d010100/0101/0011ddd/dddd/d100000/1000/0101000/0000/1110101/0100/0111ddd/dddd/dZxy3y2y1

000111