硬件描述語言VHDL及其應(yīng)用講解材料

硬件描述語言VHDL及其應(yīng)用哈工大微電子中心王進祥電話：6415979-8069/27/20241一、目的了解目前電子設(shè)計系統(tǒng)方法及流程了解/掌握綜合與驗證工具能用VHDL設(shè)計復(fù)雜功能電路二、內(nèi)容高層次設(shè)計概述如何寫優(yōu)化的VHDL代碼examplesSoC設(shè)計方法學(xué)設(shè)計工具使用三、如何學(xué)習(xí)本課程帶著實際課題學(xué)習(xí)，多提問題，一起分析、討論9/27/20242一、高層次設(shè)計概述EDA工具發(fā)展設(shè)計方法深亞微米設(shè)計問題測試綜合（可測性設(shè)計）Top-down設(shè)計流程硬件描述語言綜合VHDL設(shè)計小結(jié)9/27/20243年代名稱硬件特征70’sCAD16位小型機圖型編輯，設(shè)計規(guī)則檢查80’sCAE32位工作站LVS工具90’sEDA32位工作站邏輯/行為綜合工具NowSoC?32位工作站物理綜合工具，IP復(fù)用技術(shù)1.1EDA工具發(fā)展9/27/20244自頂向下設(shè)計方法（Top-down）:系統(tǒng)行為設(shè)計結(jié)構(gòu)設(shè)計邏輯設(shè)計電路設(shè)計版圖設(shè)計1.2設(shè)計方法自底向上設(shè)計方法（Bottom-up）:系統(tǒng)功能劃分單元設(shè)計功能模塊設(shè)計子系統(tǒng)設(shè)計系統(tǒng)總成基于平臺設(shè)計方法（Platform-based）:SoC設(shè)計普遍采用的方法，SoC平臺和IP—IntellectualProperty其它設(shè)計:嵌入式設(shè)計方法，層次式設(shè)計方法等9/27/202461.3深亞微米設(shè)計問題連線延時時序模型器件模型信號完整性電磁干擾功耗設(shè)計工具綜合優(yōu)化工具布圖規(guī)劃工具SDFPDEFSDF—標(biāo)準(zhǔn)數(shù)據(jù)格式PDEF—物理設(shè)計交換格式9/27/202471.4測試綜合目的：集成電路的測試簡單化嵌入可測試結(jié)構(gòu)，加速可測性設(shè)計產(chǎn)品制造前就可評價設(shè)計的可測性消除冗余邏輯診斷不可測的邏輯結(jié)構(gòu)內(nèi)容：測試嵌入、設(shè)計規(guī)則檢查、測試碼生成、故障模擬/診斷和輸出測試圖樣測試綜合包括了使測試成功的每一步驟：如加入帶測試因素的電路，對邏輯綜合增加約束條件以滿足測試要求及對高級語言描述的可測結(jié)構(gòu)的綜合等都可歸結(jié)為測試綜合9/27/202481.4測試綜合（Cont.）方法：FullScanPartialScanBISTBoundaryScan標(biāo)準(zhǔn)/規(guī)范：IEEE1149IEEEP1500VSIARelatedSpec.SoC可測試設(shè)計：IP可測試設(shè)計GlueLogic可測試設(shè)計測試存取結(jié)構(gòu)分類：1—Pass2—Pass9/27/202491.5Top-down設(shè)計流程TIMINGLVS/DRCEXTRACTIONRouteSignoff--Gates&PlacementSynthesis&PlaceDesignPlanningCOTSIGNOFFPLANNINGSYNTHESISFLOORPLAN,P&REXTRACTIONLVS/DRCTIMINGLTL9/27/2024101.6硬件描述語言VHDL&VerilogVHDLObjectEntity—I/O界面描述Architecture—功能定義Process—行為模塊Library—VHDLObject的集合Package—數(shù)據(jù)類型、子程序、子單元的集合Configuration—Architecture/Parameter選擇9/27/2024111.6硬件描述語言（Cont.）VHDL中的端口：InOutInoutBufferBlk1Blk3Blk4Blk5Blk2InInoutOutBufferEntity9/27/2024121.7綜合Definition：Synthesis=Translation+Optimization

HDLcode

gtechlogicnetlistmin(SpeedXAreaXPower)Optimization&technologyMapping

BehavioralSynthesis:SchedulingandAllocationAlgorithm9/27/2024131.8VHDL設(shè)計小結(jié)一個完整的設(shè)計由一些子單元相互連接而成每個子單元有一個Entity和至少一個Architecture單元間數(shù)據(jù)傳遞是通過在Entity中描述中所聲明的端口進行，通信端口的信號類型、端口寬度以及端口方向要匹配一個Architecture可包括Behavioral、Dataflow和Structure風(fēng)格語句子單元（Component）在使用之前要聲明9/27/2024141.8VHDL設(shè)計小結(jié)（Cont.）RS(255,223)碼譯碼器Top框圖9/27/2024151.8VHDL設(shè)計小結(jié)（Cont.）RS(255,223)碼譯碼器詳細(xì)模塊圖9/27/2024161.8VHDL設(shè)計小結(jié)（Cont.）entityrsdecoderis

port(reset,clk:instd_logic;decin:inbit8;decout:outbit8);endrsdecoder;architecturestructuralofrsdecoderis

componentsyndrome

port(reset,clk:instd_logic;rec:inbit8;synfb:inbit8;syndout:outbit8);

end

component;1componentbmexpand

port(reset,clk:instd_logic;synin:inbit8;cnt:inrsInt;synout:outbit8;lstsfe:outbit8;bout:outbit8);endcomponent;componentbmfftbuf

port(reset,clk:instd_logic;ctl255:instd_logic;syno,addo:inbit8;bmfo:outrsbit8_vector(0toN2-1));endcomponent;

29/27/2024171.8VHDL設(shè)計小結(jié)（Cont.）componentifftport(reset,clk:instd_logic;ctlN1m1,ctlN1:instd_logic;ctl254:instd_logic;buffin:inrsbit8_vector(0toN2-1);iffto:outbit8);endcomponent;componentfftobufport(reset,clk:instd_logic;ctlobf:instd_logic;din:inbit8;fbo:outbit8);end

component;3componentdecbuf

port(reset,clk:instd_logic;din:inbit8;dout:outbit8);endcomponent;

componentcontrol

port(reset,clk:instd_logic;ctlN1m1,ctlN1:outstd_logic;ctl254,ctl255:outstd_logic;ctlobf:outstd_logic;synfb:outstd_logic;cntout:bufferrsInt);endcomponent;

49/27/2024181.8VHDL設(shè)計小結(jié)（Cont.）componentxor8port(in1,in2:inbit8;xout:outbit8);endcomponent;signalctlN1m1,ctlN1,ctl254,ctl255:std_logic;signalctlobf,synfb:std_logic;signalfbo,dout,synout,lstsfe,bout:bit8;signalcntout:rsInt;signaliffto,syndout:bit8;signalbmfo:rsbit8_vector(0toN2-1);59/27/2024191.8VHDL設(shè)計小結(jié)（Cont.）beginu1:controlportmap(reset,clk,ctlN1m1,ctlN1,ctl254,ctl255,ctlobf,synfb,cntout);u2:syndromeportmap(reset,clk,decin,synfb,syndout);u3:bmexpandportmap(reset,clk,syndout,cntout,synout,lstsfe,bout);u4:bmfftbufportmap(reset,clk,ctl255,synout,lstsfe,bmfo);u5:ifftportmap(reset,clk,ctlN1m1,ctlN1,ctl254,bmfo,iffto);u6:fftobufportmap(reset,clk,ctlobf,iffto,fbo);u7:decbufportmap(reset,clk,decin,dout);u8:xor8portmap(fbo,dout,decout);endstructural;69/27/202420二、如何寫優(yōu)化的VHDL代碼數(shù)據(jù)類型并發(fā)/順序賦值語句小結(jié)Process語句資源共享其它9/27/2024212.1數(shù)據(jù)類型TypesScalarFileAccessCompositeArrayRecordEnumeratedRealIntegerPhysical9/27/2024222.1數(shù)據(jù)類型(Cont.)標(biāo)準(zhǔn)數(shù)據(jù)類型：

bit,bit_vector,std_ulogic,std_logic,

std_logic_vector,boolean,integer,etc.復(fù)合數(shù)據(jù)類型：

array, record,sub_type,newtype9/27/2024232.1.1賦值語句i/ signalt,s:bit;s<=‘1’;--s<=t;ii/signalc:bit_vector(0to3);signald:bit_vector(3downto0);c<=“1011”;d<=c;--ok?c(0to3)<=d(0to3)–ok?d<=c;--ok!c(0to3)<=d(0to3)–No!c(0)c(1)c(2)c(3)d(3)d(2)d(1)d(0)9/27/202424iii/signals,t,w,m:bit;signalc:bit_vector(0to3);c<=“1011”;c<=s&t&w&m;c<=(‘1’,‘0’,‘1’,‘1’);c<=3;

c<=(0->‘1’,1->s,2->‘1’,3->‘1’);Ok?c<=3;--No

c<=(0->‘1’,1->s,2->‘1’,3->‘1’);--Ok2.1.1賦值語句（Cont.）9/27/202425iv/signala_vec:bit_vector(0to11);a_vec<=B”1100_0011_0011_1100”;a_vec<=“1100001100111100”;a_vec<=X”C33C”;a_vec<=X”C3_3C”;a_vec<=“1100_0011_0011_1100”;

a_vec<=“C33C”;Ok?a_vec<=“1100_0011_0011_1100”;

a_vec<=“C33C”;No!2.1.1賦值語句（Cont.）9/27/202426二進制—B（Binary）八進制—O（Octal）十六進制—X（Hexadecimal）位串中的進制表示：十進制—D（Decimal）???十進制—D（Decimal）No!2.1.1賦值語句（Cont.）9/27/202427v/signalA,B,C:bit_vector(3downto0);C<=AandB;C<=notA

Ok?‘0’‘1’‘1’‘0’‘1’‘1’‘0’‘1’‘0’‘1’‘0’‘0’A=B=C=C(3)<=A(3)andB(3);C(2)<=A(2)andB(2);C(1)<=A(1)andB(1);C(0)<=A(0)andB(0);S2.1.1賦值語句（Cont.）C<=notA

OK!‘0’‘1’‘1’‘0’‘1’‘0’‘0’‘1’A=C=9/27/202428vi/sliceofarrayentityVHDLis

port(A:inbit_vector(0to7);outp:outbit);endVHDL;architectureE1ofVHDLisbeginoutp<=A(5);end;signalC:bit_vector(0to7);C(4)<=‘1’;C(0to3)<=“1001”;2.1.1賦值語句（Cont.）9/27/202429vii/Compositedatatype

typedateisrecord

year:

integerrange1980to2030;

month:

integerrange1to12;

day:

integerrange1to30;endrecord;subtypebit8isbit_vector(7downto0);2.1.1賦值語句（Cont.）9/27/202430vii/Compositedatatypesignalweekday,today:date;weekday.year<=2003;weekday.monty<=2;weekday.day<=14;

today<=weekday;2.1.1賦值語句（Cont.）9/27/2024312.1.2數(shù)據(jù)類型轉(zhuǎn)換強類型語言：VHDL具有豐富的數(shù)據(jù)類型，不同類型的對象（信號、變量）不能直接賦值經(jīng)常轉(zhuǎn)換的數(shù)據(jù)類型：std_logic,bit,std_ulogic,boolean,signedunsigned,std_logic_vector,bit_vector數(shù)據(jù)類型轉(zhuǎn)換三種方法：類型標(biāo)記轉(zhuǎn)換法、函數(shù)轉(zhuǎn)換法和常數(shù)轉(zhuǎn)換法9/27/202432類型標(biāo)記轉(zhuǎn)換法 std_logicandstd_ulogic, std_logic_vectorandsigned std_logic_vectorandunsigned integerandreal等signalastd_logic_vector(0to7);signalbunsigned(0to7);b<=unsigned(a);2.1.2數(shù)據(jù)類型轉(zhuǎn)換(Cont.)9/27/202433函數(shù)轉(zhuǎn)換法 std_logicandbit std_ulogicandbit,booleanandbit, std_logic_vectorandbit_vector integerandstd_logic_vector/unsigned等signalastd_logic_vector(0to7);signalbintegerrange0to255;a<=to_stdlogicvector(X”AF”);b<=conv_ingeter(a);2.1.2數(shù)據(jù)類型轉(zhuǎn)換(Cont.)9/27/202434typetypeconv_typeisarray(std_ulogic’lowtostd_ulogic’high)ofbit;constanttypeconv:typeconv_type:=(‘0’|‘L’=>‘0’,‘1’|‘H’=>‘1’,others=>‘0’);signals:std_ulogic;signala:bit;a<=typeconv(s);常數(shù)轉(zhuǎn)換法2.1.2數(shù)據(jù)類型轉(zhuǎn)換(Cont.)9/27/202435Howtotransformbittypetobooleantype?signalbitty:bit;signalbooly:boolean;booly<=(bitty=‘1’);Discussion2.1.2數(shù)據(jù)類型轉(zhuǎn)換(Cont.)9/27/2024362.1.3邏輯運算與關(guān)系運算運算符:and,or,not,xor,nand,nor=,/=,<,<=,>,>=Discussion:Whatistheresultofthefollowingrelationalstatement?“1000”>“1111”=?“1000”>“1111”=false9/27/2024372.1.4算術(shù)操作運算符:+，–，*，mod，/，rem操作數(shù)類型:

std_logic_vector,integer,signed,unsigned右操作數(shù)必須為2的指數(shù)！！useieee.std_logic_unsigned.all;9/27/2024382.1.4算術(shù)操作（Cont.） signala,b:std_logic_vector(3downto0); q1<=unsigned(a)+unsigned(b); q2<=unsigned(a)+signed(b); q3<=signed(a)+signed(b); q4<=a+b; q5<=(‘0’&a)+b;--4bit--5bit--4bit--4bit--5bit9/27/2024392.1.5連字符和聚集連字符：concatenationoperator聚集： aggregates signalA,B:std_logic_vector(3downto0); signalC:std_logic_vector(7downto0); signalD:std_logic; C<=A&B;C(7)C(6)C(5)C(4)C(3)C(2)C(1)C(0)AB9/27/202440 C(7)<=‘Z’; C(6downto3)<=A; C(2downto0)<=‘0’&A(1downto0); C<=(7=>‘1’,6=>D,5downto2=>‘1’, others=>‘0’);

C<=“00000000”;-----初始化C<=(others=>‘0’);2.1.5連字符和聚集(Cont.)9/27/2024412.2并發(fā)/順序賦值語句并發(fā)賦值語句在architecture的begin和end之間，與書寫順序無關(guān)，每一條并發(fā)語句均可用一個process語句等價順序賦值語句只能在process和子程序的begin和end之間，它除信號賦值語句外，還有變量賦值9/27/2024422.2.1并發(fā)賦值語句D<=A+E;A<=B+C;++BCEAD9/27/2024432.2.1并發(fā)賦值語句(Cont.)A<=B+A;并發(fā)賦值語句：+ABAC<=A;C<=B;ABC組合邏輯環(huán)路?。ulti-driver,needresolvedfunction9/27/2024442.2.2順序賦值語句D<=A+E;A<=B+C;++BCEAD9/27/2024452.2.2順序賦值語句(Cont.)C<=A;C<=B;BCA<=B+A;組合進程：No!時序進程：Ok!+ABA9/27/2024462.3小結(jié)一個設(shè)計由entity和architecture描述數(shù)據(jù)對象類型有bit,boolean,integer,std_logic等標(biāo)準(zhǔn)類型和用戶自定義類型并發(fā)語句執(zhí)行與書寫順序無關(guān)（orderindependent）VHDL是一種強類型語言（類型不能自動相互轉(zhuǎn)換）元件例化語句不能在process中，if語句和for語句用于并發(fā)語句時，只能是generate語句，并發(fā)語句無變量賦值語句9/27/2024472.3小結(jié)(Cont.)entityshiftisport(reset,clk:instd_logic;din:instd_logic;dout:outstd_logic);endshift;architecturestrofshiftiscomponentdffport(reset,clk:instd_logic;d:instd_logic;q:outstd_logic);endcomponent;

signaltv:std_logic_vector(0to7);beginforIin0to7generateifI=0generateu1:dffportmap(reset,clk,din,tv(0));endgenerate;ifI>0andI<=7generateu2:dffportmap(reset,clk,tv(I–1),tv(I));endgenerate;endgenerate;dout<=tv(7);endstr;9/27/2024482.4process描述電路功能或行為。由于綜合后的電路對所有輸入信號變化敏感，因此所有被讀信號均應(yīng)包含在敏感表中，否則，綜合前的模擬結(jié)果與綜合后的模擬結(jié)果不一致！9/27/2024492.4.1syntax[process_label:]process(sensitivitylist)

[declarations;]beginstatements;--if,loop,case,subprogramcalletcendprocess[process_label];9/27/2024502.4.1syntaxP1:process(A,B)BeginD<=AorBandC;EndprocessP1;P1:process(A,B,C)BeginD<=AorBandC;EndprocessP1;9/27/2024512.4.2

communicationamongprocessAssignmentIf,case,loopetcSignal_NSignal_3Signal_1Signal_2ProcessAProcessBarchitectureexample9/27/2024522.4.3ifthenelse語句綜合i/.引入寄存器entitydffisport(d:instd_logic;clk:instd_logic;q:outstd_logic);Enddff;architecturertlofdffisbegininfer_reg:process(d,clk)beginif(clk’eventandclk=‘1’)thenq<=d;endprocessinfer;endrtl;9/27/2024532.4.3ifthenelse語句綜合(Cont.)ii/.引入鎖存器Infer_latch:process(A,B)beginif(A=‘1’)thenx<=B;endprocessinfer_infer_latch;Infer_latch:process(A,B)Beginx<=‘0’;if(A=‘1’)thenx<=B;endprocessinfer_infer_latch;隱含了A=‘0’時x<=x;不完全的else9/27/2024542.4.3ifthenelse語句綜合(Cont.)iii/.組合電路entitycombisport(a,b:inbit;select:inbit;y:outbit);endcomb;architecturearchofcombisbeginprocess(a,b,select)beginif(select=‘1’)theny<=b;elsey<=a;endif;endprocess;endarch;bayselect109/27/2024552.4.3ifthenelse語句綜合(Cont.)iv/.異步復(fù)位process(reset,clk,d)Beginif(reset=‘0’)thenq<=‘0’;elsif(clk’eventandclk=‘1’)thenq<=d;endif;endprocess;dclkresetq9/27/2024562.4.3ifthenelse語句綜合(Cont.)v/.三態(tài)邏輯signals,sel,data:std_logic;process(sel,data)Beginif(sel=‘1’)thens<=data;elses<=‘Z’;endif;endprocess;19/27/2024572.4.3ifthenelse語句綜合(Cont.)v/.三態(tài)邏輯architecturebehoftribufissignalasel,bsel,a,b,s:std_logic;beginpa:process(asel,a)begins<=‘Z’;if(asel=‘1’)thens<=a;endif;endprocesspa;2pb:process(bsel,b)begins<=‘Z’;if(bsel=‘1’)thens<=b;endif;endprocesspb;endbeh;Multidriver!!9/27/2024582.4.3ifthenelse語句綜合(Cont.)Discussionsignala,b,use_b:bit;process(a,b,use_b)Beginif(use_b=‘1’)thens<=b;elseif(use_b=‘0’)thens<=a;endif;endprocess;1Latch?9/27/2024592.4.3ifthenelse語句綜合(Cont.)Discussionsignala,b,use_b:std_logic;process(a,b,use_b)Beginif(use_b=‘1’)thens<=b;elseif(use_b=‘0’)thens<=a;endif;endprocess;2Latch?9/27/2024602.4.3ifthenelse語句綜合(Cont.)Discussionelseassertfalsereport“invaliduse_b”severityerror;endif;endprocess;3what?signala,b,use_b:std_logic;process(a,b,use_b)Beginif(use_b=‘1’)thens<=b;elseif(use_b=‘0’)thens<=a;9/27/2024612.4.3ifthenelse語句綜合(Cont.)vi/.在一個進程中，一個信號只能對應(yīng)一個三態(tài)驅(qū)動

process(b,ub,a,ua)Begindout<=‘Z’;if(ub=‘1’)thendout<=b;endif;if(ua=‘1’)thendout<=a;endif;endprocess;9/27/2024622.4.3ifthenelse語句綜合(Cont.)vii/.‘Z’值使用規(guī)則如：dout<=‘Z’anddin;如：if(sel=‘Z’)then相當(dāng)于

iffalsethen

某個信號被賦值‘Z’值時，將會引入三態(tài)驅(qū)動，但‘Z’值不能用于復(fù)雜的表達(dá)式中（邏輯/算術(shù)表達(dá)式）1當(dāng)信號與‘Z’值比較時，結(jié)果總為false，引用這樣的關(guān)系表達(dá)式將導(dǎo)致模擬與綜合結(jié)果不匹配29/27/2024632.4.3ifthenelse語句綜合(Cont.)vii/.ifthenelse語句小結(jié)可以描述順序行為1可以生成三態(tài)邏輯4生成組合邏輯2如果缺少else語句，可能生成latch3可以引入時序元件5一般用于process和subprogram中69/27/2024642.4.4case語句i/.syntaxcase(expression)iswhenvalue=>statements;whenvalue|value=>statements;whenvalue1tovalue2=>statements;……whenothers=>statements;endcase;9/27/2024652.4.4case語句(Cont.)ii/.case語句規(guī)則任意value互不相同

如無others分枝，必須窮盡所有可能的表達(dá)式值如有others分枝，必須至少有一個表達(dá)值未列出

任意分枝中的語句可以有多條9/27/2024662.4.4case語句(Cont.)entitydecoderisport(din:instd_logic_vector(0to2);q:outstd_logic_vector(0to7));enddecoder;architectureexofdecoderisbeginprocess(din)begincase(din)when“000”=>q<=“00000001”;when“001”=>q<=“00000010”;when“010”=>q<=“00000100”;when“011”=>q<=“00001000”;when“100”=>q<=“00010000”;when“101”=>q<=“00100000”;when“110”=>q<=“01000000”;when“111”=>q<=“10000000”;whenothers=>q<=“--------”;endcase;endprocess;endex;9/27/2024672.4.5forloop語句i/.語法loop_label:forloop_varinrangeloopsequentialstatements;endlooploop_label;說明：loop_label可選，loop_var不需聲明，綜合時，循環(huán)語句將unrolledWhyloopstatement?9/27/2024682.4.5forloop語句(Cont.)entityparsumisport(word:instd_logic_vector(0to7);par:outstd_logic);endparsum;architectureaddxorofparsumisbeginprocess(word)variablets:std_logic;begints:=‘0’;

forIinword’rangeloopts:=tsxorword(I);endloop;par<=ts;endprocess;endaddxor;Discussion:如果ts為信號，結(jié)果是什么？9/27/2024692.4.6數(shù)據(jù)對象constantvariablesignali/.constantandvariableconstantconst_name:type:=value;variablevar_name:type;格式constantmask:std_logic_vector(0to7):=“00000000”;constantled_zero:bit_vector(0to7):=X”7E”;variabletsum:std_logic_vector(3downto0);9/27/2024702.4.6數(shù)據(jù)對象(Cont.)ii/.signalandvariable相同點：值可變，可綜合為邏輯或線不同點：變量賦值有立即性，且只用于process和subprogram中（VHDL-1076-87），而信號除此之外，還可用于并行語句中應(yīng)用：簡單計算signal復(fù)雜計算variable中間結(jié)果variable9/27/2024712.4.6數(shù)據(jù)對象(Cont.)signala,b,c,x,y:shortprocess(a,b,c)beginc<=a;x<=c+2;c<=b;y<=c+4;endprocess;signala,b,

x,y:shortprocess(a,b,c)variablec:short;beginc:=a;x<=c+2;c:=b;y<=c+4;endprocess;9/27/202472++2b4xy++2b4xya2.4.6數(shù)據(jù)對象(Cont.)signalvariable9/27/2024732.4.6數(shù)據(jù)對象(Cont.)entitysigvarisport(a,b,c,d:std_logic;q:outstd_logic;endsigvar;architecturesigofsigvarissignalint:std_logic;Beginprocess(a,b,c,d,int)beginint<=aandbandc;q<=intord;endprocess;endsig;entitysigvarisport(a,b,c,d:std_logic;q:outstd_logic;endsigvar;architecturesigofsigvarisBeginprocess(a,b,c,d)variablelint:std_logic;beginint:=aandbandc;q<=intord;endprocess;endsig;9/27/2024742.4.7wait語句waituntil,wait,waiton,waitfor

wait語句表明了信號激活process的條件在process中，如有wait語句，敏感表必須取消在process中，如既無wait語句，也無敏感表，則不能正確模擬

綜合工具僅支持waituntil語句（引入寄存器）!!!9/27/2024752.4.7wait語句(Cont.)libraryieee;Useieee.std_logic_1164.all;entitycount4isport(updown:instd_logic;clk:instd_logic;dout:outintegerrange0to15);endcount4;architecturebehaveofcount4issignalcnt:integerrange0to15;beginprocessbeginwaituntilclk’eventandclk=‘1’;if(updown=‘1’)thenif(cnt=15)thencnt<=0;elsecnt<=cnt+1;endif;elseif(cnt=0)thencnt<=15;elsecnt<=cnt–1;endif;endif;endprocess;endbehave;9/27/2024762.5資源共享硬件資源：關(guān)系運算：=，/=，<，<=，>，>=算術(shù)運算：+，—，*，/每個運算符均要消耗大量的硬件資源，并產(chǎn)生延時!!!如何用最小的資源實現(xiàn)相同的功能？9/27/2024772.5資源共享(Cont.)i/.……if(sel_a=‘1’)thenz<=a+t;endif;if(sel_a=‘0’)thenz<=b+t;endif;……19/27/2024782.5資源共享(Cont.)i/.z<=a+twhensel_a=‘1’elseb+t;或if(sel_a=‘1’)thenz<=a+t;elsez<=b+t;endif;29/27/2024792.5資源共享(Cont.)ii/.dout:=0;found:=false;forkin1to4loopif(found=false)thenif(a(k)=‘1’)thendout:=b(k)+c(k);found:=true;endif;endif;endloop;19/27/2024802.5資源共享(Cont.)ii/.t1:=0;t2:=0;found:=false;forkin1to4loopif(found=false)thenif(a(k)=‘1’)thent1:=b(k);t2:=c(k);found:=true;endif;endif;endloop;dout:=t1+t2;29/27/2024812.5資源共享(Cont.)iii/.多進程P1：processbeginwaituntilclk’eventandclk=‘1’;if(sel=“00”)thenreg_0<=dA+dB;endif;endprocessP1;1P2：processbeginwaituntilclk’eventandclk=‘1’;if(sel=“01”)thenreg_1<=dA-dB;endif;endprocessP2;9/27/2024822.5資源共享(Cont.)iii/.多進程P3：processbeginwaituntilclk’eventandclk=‘1’;if(sel=“10”)thenreg_2<=dB-dA;endif;endprocessP1;2dout<=reg_0whensel=“00”elsereg_1whensel=“01”elsereg_2whensel=“10”else0;資源：3個加法器/減法器，資源共享不能在多進程間實現(xiàn)！9/27/2024832.5資源共享(Cont.)iv/.if((addr(31downto20)<=“000000000110”)and(addr(31downto20)>=“000000000001”))then資源：兩個12位比較器資源：兩個3位比較器+一個9位比較器if((addr(31downto23)=“000000000”)and(addr(22downto20)/=“111”)and(addr(22downto20)/=“000”))then9/27/2024842.5資源共享(Cont.)v/.s(0)<=A(0)andA(1);forkin1to7loopif(k>A–1)thens(k)<=‘1’;elses(k)<=‘0’;endif;endloop;資源：1個減法器，7個比較器說明：模擬時間長，因為每進入循環(huán)均要計算一次減法；綜合時間也會較長，因為綜合工具要移去循環(huán)中的定值表達(dá)式19/27/2024852.5資源共享(Cont.)v/.s(0)<=A(0)andA(1);tv:=A–1;forkin1to7loopif(k>tv)thens(k)<=‘1’;elses(k)<=‘0’;endif;endloop;資源：1個減法器，7個比較器說明：模擬、綜合時間短29/27/2024862.5資源共享(Cont.)v/.s(0)<=A(0)andA(1);forkin1to7loopif(k+1>A)thens(k)<=‘1’;elses(k)<=‘0’;endif;endloop;資源：0個減法器，7個比較器說明：下標(biāo)運算不產(chǎn)生額外資源消耗，綜合工具自動用2to8與A比較；模擬、綜合時間短39/27/2024872.5資源共享(Cont.)vi/.sum:=0;forkin0to7loopsum:=sum+A(k);endloop;dout<=sum;1++++A(0)A(1)A(6)A(7)0dout8個加法器，8級加法器延遲9/27/2024882.5資源共享(Cont.)vi/.cnt:=8;forlin0to2loopcnt:=cnt/2;forkin0tocnt–1loopA(k):=A(k*2)+A(k*2+1);endloop;endloop;dout<=A(0);27個加法器，3級加法器延遲++++A(0)A(1)dout+++A(2)A(3)A(4)A(5)A(6)A(7)9/27/2024892.6其它i/.正確使用后到達(dá)的信號process(A_late,B,C,D)beginif(A_late+B<24)thendout<=C;elsedout<=D;endif;endprocess;19/27/2024902.6其它(Cont.)i/.正確使用后到達(dá)的信號process(A_late,B,C,D)beginif(A_late<24-B)thendout<=C;elsedout<=D;endif;endprocess;29/27/2024912.6其它(Cont.)ii/.仿真與綜合結(jié)果不匹配processvariablecnt:integerrange0to255;beginwaituntilclk’eventandclk=‘1’;cnt:=cnt+1;dout<=cnt;endprocess;1變量將引入額外的寄存器！+1clkdoutOk?9/27/2024922.6其它(Cont.)ii/.仿真與綜合結(jié)果不匹配signalcnt:integerrange0to255;processbeginwaituntilclk’eventandclk=‘1’;cnt<=cnt+1;endprocess;dout<=cnt;2但是，仿真時，當(dāng)cnt的值為255時，再一次進入該process時，將報告越界錯誤！+1clkdoutOk!9/27/2024932.6其它(Cont.)ii/.仿真與綜合結(jié)果不匹配signalcnt:integerrange0to255;processbeginwaituntilclk’eventandclk=‘1’;if(cnt=255)thencnt<=0;elsecnt<=cnt+1;endprocess;dout<=cnt;3+1clkdoutOk!9/27/2024942.6其它(Cont.)iii/.避免不必要的重復(fù)調(diào)用函數(shù)functionadd8(in1,in2:bit_vector(7downto0))isreturnbit_vector(7downto0);……sign_bit:=add8(A,B)(7);lower_nibble:=add8(A,B)(3downto0);……tv:=add8(A,B);sign_bit:=tv(7);lower_nibble:=tv(3downto0);9/27/2024952.6其它(Cont.)iv/.元件例化端口映射問題inst1:comp1portmap(din_1=>‘0’;din_2=>con_A;dout=>con_out);signalgnd:std_logic;……gnd<=‘0’;inst1:comp1portmap(din_1=>gnd;din_2=>con_A;dout=>con_out);當(dāng)某一輸入端口接固定電平時，必須引入中間信號，且中間信號不能在說明時賦初值！19/27/2024962.6其它(Cont.)iv/.元件例化端口映射問題componentdffport(reset,clk:instd_logic;d:instd_logic;q,qn:outstd_logic);enddff;當(dāng)某一輸出端懸空時，應(yīng)連接open關(guān)鍵字！u1:dffportmap(reset=>reset,clk=>clk;q=>dout,qn=>open);29/27/2024972.6其它(Cont.)v/.避免陣列方向錯誤signaldata8:bit_vector(0to7);signaldout:bit_vector(7downto0);……dout<=data8(7downto0);forIin0to7loopdout(I)<=data8(7–I);endloop;9/27/2024982.6其它(Cont.)vi/.避免低效率語句

signal:l1,l2:bit;P1:process(l1,l2,A,B,C,D)begincase(l1&l2)iswhen“00”=>dout<=A;when“01”=>dout<=B;when“10”=>dout<=C;when“11”=>dout<=D;endcase;endprocessP1;signal:l1,l2:bit;P2:process(l1,l2,A,B,C,D)beginif(l1&l2=“00”)thendout<=A;elsif(l1&l2=“01”)thendout<=B;elsif(l1&l2=“10”)thendout<=C;elsedout<=D;endif;endprocessP2;Ok?No!19/27/2024992.6其它(Cont.)vi/.避免低效率語句

signal:l1,l2:bit;P3:process(l1,l2,A,B,C,D)subtypetwobitsisbit_vector(0to1);begincase(twobits’(l1&l2))iswhen“00”=>dout<=A;when“01”=>dout<=B;when“10”=>dout<=C;when“11”=>dout<=D;endcase;endprocessP3;29/27/20241002.6其它(Cont.)vii/.桶移位寄存器

entitybarrel_shifterisport(clk:inbit;din:inbit_vector(0to31);k:inintegerrange0to31;dout:outbit_vector(0to31));endbarrel_shifter;architecturebehaveofbarrel_shifterisbeginprocessbeginwaituntilclk’eventandclk=‘1’;dout<=din(kto31)&din(0tok);endprocess;endbehave;上述模型不可綜合，k是0~31中任意的數(shù)，屬于不可計算的，但上述模型可仿真！19/27/20241012.6其它(Cont.)vii/.桶移位寄存器

architecturesyn1ofbarrel_shifterisbeginprocessbeginwaituntilclk’eventandclk=‘1’;if(k=0)thendout<=din;elseforlin1to31loopif(l=k)thendout<=din(lto31)&din(0tol);endif;endloop;endif;endprocess;endsyn1;29/27/20241022.6其它(Cont.)vii/.桶移位寄存器architecturesyn2ofbarrel_shifterisbeginprocessbeginwaituntilclk’eventandclk=‘1’;case(k)iswhen0=>dout<=din;when1=>dout<=din(1to31)&din(0);

……when31=>dout<=din(31)&din(0to30);endcase;endprocess;endsyn2;39/27/2024