數(shù)字設(shè)計(jì) 第三章 數(shù)字電路基礎(chǔ)學(xué)習(xí)課件

Chpter3DigitalCircuit主要內(nèi)容：數(shù)字邏輯信號(hào)、門(mén)電路數(shù)字電路的開(kāi)關(guān)特性；數(shù)字電路的電氣特性；

2/28/2025頁(yè)面1數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.1LogicSignalsandGates1、LogicsignalsTwodiscreteelectricalsignals①logicvalue：0and1,couldbecombinedtorepresentconditions.②logiclevel：

HIGH—asignalintherangeofhighervoltagesLOW—asignalintherangeoflowervoltages2/28/20252數(shù)字邏輯設(shè)計(jì)及應(yīng)用

③logicconventionpositivelogic：HIGH—logic1；

LOW—logic0negativelogic：HIGH—logic0 LOW—logic12、representationofdigitalcircuitinputsoutputLogic

circuitXYZF2/28/20253數(shù)字邏輯設(shè)計(jì)及應(yīng)用①combinationalcircuitThecircuit’soutputdependonlyonitscurrentinputs.Truthtable:specifythefunctionalityofcombinationalcircuit.

inputsoutputXYZF00000011010001101000101011011111Allinputcombinations2/28/20254數(shù)字邏輯設(shè)計(jì)及應(yīng)用②SequentialcircuitAcircuitwithmemory,whoseoutputsdependonthecurrentinputandthesequenceofpastvalue.Statetable：specifythefunctionalityofsequentialcircuit.2/28/20255數(shù)字邏輯設(shè)計(jì)及應(yīng)用3、logicgatesANDgatesORgatesNOTgateslogicmultiplicationlogicaddition2/28/20256數(shù)字邏輯設(shè)計(jì)及應(yīng)用NANDgatesNORgates2/28/20257數(shù)字邏輯設(shè)計(jì)及應(yīng)用4.timingdiagraminputsoutputsdescribethecircuit’sbehaviors2/28/20258數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.3CMOSLogic1、CMOSlogiclevelsletVCC=5V，5.0V3.5V1.5V0.0Vlogic1（H）logic0（L）UndefinedlogiclevelLogicvoltagelevelsdecreasingwithprocess5→3.3→2.5→1.8V2/28/20259數(shù)字邏輯設(shè)計(jì)及應(yīng)用2.MOStransistorsIndigitalcircuits,MOStransistorworklikeaswitchwhichhastwostate–onoroff.Equivalentmodel：avoltage-controlledresistance.2/28/202510數(shù)字邏輯設(shè)計(jì)及應(yīng)用NMOStransistor：Vgs=0，Rds>106Ω，transistorisoff；Vgs>0，Rds≈10Ω，transistorison.2/28/202511數(shù)字邏輯設(shè)計(jì)及應(yīng)用PMOS晶體管：

Vgs=0，Rds>106Ω，transistorisoff；Vgs<0，Rds≈10Ω，transistorison.2/28/202512數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.CMOSinvertercircuitproperty：①VIN=0.0V(L)Q1:Vgs=0，offQ2:Vgs<0，on

VOUT=VDD=5.0V(H）②VIN=5.0V(H)Q1:Vgs>0，onQ2:Vgs=0，off

VOUT=Vss=0.0V(L）2/28/202513數(shù)字邏輯設(shè)計(jì)及應(yīng)用Switchmodel2/28/202514數(shù)字邏輯設(shè)計(jì)及應(yīng)用WritewithtruthtableLogicsymbol：inputVINoutputVOUT0（L）1（H）1（H）0（L）2/28/202515數(shù)字邏輯設(shè)計(jì)及應(yīng)用4.CMOSNANDandNORgates

Ak-inputgateusekp-channelandkn-channeltransistor.2-inputNANDgateIfeitherinputisLOW，thenonetransistorisalwaysoff,Z=H；OnlybothinputsareHIGH,thenZ=L.ABZ2/28/202516數(shù)字邏輯設(shè)計(jì)及應(yīng)用2-inputsNORgateIfeitherinputisHIGH,thenonetransistorisalwayson,soZ=L；OnlybothinputsareLOW，thenZ=H2/28/202517數(shù)字邏輯設(shè)計(jì)及應(yīng)用5.Fan-inThenumberofinputsthatagatecanhaveinaparticularlogicfamily.Fan-inislimitedbythecost.costisproportionaltothenumberoftransistorsorareainintegratedcircuit.2/28/202518數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.5CMOSStaticElectricalBehavior）1、LogicLevelandNoiseMarginstransfercharacteristicofinverter001.53.55.0VINVOUT1.53.55.0VTLH2/28/202519數(shù)字邏輯設(shè)計(jì)及應(yīng)用Finedefinitionoflogiclevel(p.102)NMH:HIGH-stateDCnoisemarginNML:LOW-stateDCnoisemarginoutputinputVccVOHmin0VOLmaxVIHminVILmaxNMHHLNMLVOHmin:Vcc-0.1VVIHmin:0.7VccVILmax:0.3VccVOLmax:ground+0.1V2/28/202520數(shù)字邏輯設(shè)計(jì)及應(yīng)用DCNoiseMarginameasureofhowmuchnoiseittakestocorruptaworst-caseoutputvoltageintoavaluethatmaynotberecognizedproperlybyaninput.（p.103）

HIGHstate：DC_N.M.=VOHmin-VIHminLOWstate：DC_N.M.=VILmax-VOLmaxCMOSinputcurrent:leakagecurrentIIH,IIL2/28/202521數(shù)字邏輯設(shè)計(jì)及應(yīng)用2.CircuitBehaviorwithResistiveLoadsresistiveloadsThecurrentIOHmaxandIOLmax

specifythemaximumloadforeachoutput-state.resistive

loadVccVINRn

RpIoNeednontrivialamountsofcurrenttooperate2/28/202522數(shù)字邏輯設(shè)計(jì)及應(yīng)用①outputHIGHleveldrivinggateloadinggateresistive

loadVccVINRn

>1MΩRpVOHminIOHmaxSourcingcurrentoutputvoltagemaydropifoutputtoomuchsourcecurrent.2/28/202523數(shù)字邏輯設(shè)計(jì)及應(yīng)用②outputLOWstateLdrivinggateloadinggateresistive

loadVccVINRnRp

>1MΩVOLmaxIOLmaxSinkingcurrentoutputvoltagemayriseifoutputtoomuchsinkcurrent.2/28/202524數(shù)字邏輯設(shè)計(jì)及應(yīng)用DifferentloadsP.107table3-4For“CMOS”loads,currentandvoltagedroparenegligiblebecauseitconsumeverylittlecurrent.ForTTLinputs,LEDs,terminations,orotherresistiveloads,currentandvoltagedroparesignificantandmustbecalculated.2/28/202525數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.Fan-out

thenumberofinputsthatthegatecandrivewithoutexceedingitsworst-caseloadingspecifications.

①outputHIGH

②outputLOWso,DCfan-out=MIN（NH,NL）

driverloader2/28/202526數(shù)字邏輯設(shè)計(jì)及應(yīng)用4.UnusedinputsUnusedCMOSinputsshouldneverbeleftunconnected(orfloating).howtodealwiththeunusedinputs:(p.112figure3-35)TietoanotherinputTietoaconstantlogicvaluethatshouldnotaffecttheoutputbyusingapull-uporpull-downresistor.2/28/202527數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.6

CMOSDynamicElectricalBehavior）

dynamic：

thecircuitbehaviorhappenswhendevice’soutputchangesbetweenstate.1、TransitionTimeTheamountoftimethattheoutputofalogiccircuittakestochangefromonestatetoanother.risetime(tr),falltime(tf)ACloadVccVINRnRpVoCL2/28/202528數(shù)字邏輯設(shè)計(jì)及應(yīng)用實(shí)際理想波形近似實(shí)際的波形實(shí)際波形2/28/202529數(shù)字邏輯設(shè)計(jì)及應(yīng)用2、PropagationDelayVINVOUTtpHLtpLH理想波形VINVOUTtpHLtpLH實(shí)際波形G1G2G3G4inputsoutputSignalpath1Signalpath2changeatt1changeatt2t1t2propagationdelay2/28/202530數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.PowerconsumptionStaticpowerdissipation:verylowDynamicpowerdissipation2/28/202531數(shù)字邏輯設(shè)計(jì)及應(yīng)用3.7otherCMOSinputandoutputstructures1.TransmissiongatesshortpropagationdelayWhenEN=1andEN_L=0,OUT=IN2.schmitt-triggerinputsENEN_LVINVOUTVT-VT+hysteresis2/28/202532數(shù)字邏輯設(shè)計(jì)及應(yīng)用

3.three-stateoutputsLogic0、1和Hi-Z（high-impeda