EDA技術(shù)實(shí)用教程課后答案---潘松-黃繼業(yè).doc

3-3 給出一個(gè)4選1多路選擇器的VHDL描述。選通控制端有四個(gè)輸入：S0、S1、S2、S3。當(dāng)且僅當(dāng)S0=0時(shí):Y=A；S1=0時(shí):Y=B；S2=0時(shí):Y=C；S3=0時(shí):Y=D。-解：4選1多路選擇器VHDL程序設(shè)計(jì)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS PORT( A,B,C,D : IN STD_LOGIC; S0,S1,S2,S3 : IN STD_LOGIC; Y : OUT STD_LOGIC); END ENTITY mux41a; ARCHITECTURE one OF mux41a IS SIGNAL S0_3 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN S0_3=S0&S1&S2&S3; y=A WHEN S0_3=0111 ELSE B WHEN S0_3=1011 ELSE C WHEN S0_3=1101 ELSE D WHEN S0_3=1110 ELSE Z; END ARCHITECTURE one;3-4 給出1位全減器的VHDL描述；最終實(shí)現(xiàn)8位全減器。要求:1)首先設(shè)計(jì)1位半減器,然后用例化語(yǔ)句將它們連接起來(lái),圖4-20中h_suber是半減器,diff是輸出差(diff=x-y),s_out是借位輸出(s_out=1,xy),sub_in是借位輸入。cyinxindiff_outba圖3-19 1位全加器-解(1.1)：實(shí)現(xiàn)1位半減器h_suber(diff=x-y；s_out=1,xy) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_suber IS PORT( x,y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END ENTITY h_suber; ARCHITECTURE hs1 OF h_suber IS BEGIN Diff = x XOR (NOT y); s_out xin,y=yin, diff=a, s_out=b); u2: h_suber PORT MAP(x=a, y=sub_in, diff=diff_out,s_out=c); sub_out x0,yin=y0,diff_out=diff0,sub_in=sin,sub_out=a0);u1:f_suber PORT MAP(xin=x1,yin=y1,diff_out=diff1,sub_in=a0,sub_out=a1);u2:f_suber PORT MAP(xin=x2,yin=y2,diff_out=diff2,sub_in=a1,sub_out=a2);u3:f_suber PORT MAP(xin=x3,yin=y3,diff_out=diff3,sub_in=a2,sub_out=a3);u4:f_suber PORT MAP(xin=x4,yin=y4,diff_out=diff4,sub_in=a3,sub_out=a4);u5:f_suber PORT MAP(xin=x5,yin=y5,diff_out=diff5,sub_in=a4,sub_out=a5);u6:f_suber PORT MAP(xin=x6,yin=y6,diff_out=diff6,sub_in=a5,sub_out=a6);u7:f_suber PORT MAP(xin=x7,yin=y7,diff_out=diff7,sub_in=a6,sub_out=sout);END ARCHITECTURE s8;3-8 設(shè)計(jì)一個(gè)求補(bǔ)碼的程序，輸入數(shù)據(jù)是一個(gè)有符號(hào)的8位二進(jìn)制(原碼)數(shù)。-解：5-9 設(shè)計(jì)一個(gè)求補(bǔ)碼的程序，輸入數(shù)據(jù)是一個(gè)有符號(hào)的8位二進(jìn)制數(shù)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY org_patch IS PORT( org_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);-原碼輸入 patch_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);-補(bǔ)碼輸出 END org_patch; ARCHITECTURE BHV OF org_patch IS BEGIN PROCESS(org_data) BEGIN IF(org_data(7)=0) THEN patch_data=0，補(bǔ)碼=原碼。 else patch_data=org_data(7)&(not org_data(6 DOWNTO 0)+1;-org_data0，補(bǔ)碼=|原碼|取反+1。 END IF; END PROCESS; END BHV;310library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity add isport(a:in std_logic_vector(7 downto 0); b:in std_logic_vector(7 downto 0); ci:in std_logic; co:out std_logic; count:out std_logic_vector(7 downto 0);end add;architecture bhv of add isbeginprocess(a,b,ci)variable data:std_logic_vector(1 downto 0);variable c:std_logic;beginc:=ci;for n in 0 to 7 loopdata:=(0&a(n)+(0&b(n)+(0&c);count(n)=data(0);c:=data(1);end loop;co=c;end process;end bhv;3-14 用循環(huán)語(yǔ)句設(shè)計(jì)一個(gè)7人投票表決器，及一個(gè)4位4輸入最大數(shù)值檢測(cè)電路。-解：5-7 用循環(huán)語(yǔ)句設(shè)計(jì)一個(gè)7人投票表決器，及一個(gè)4位4輸出最大數(shù)值檢測(cè)電路。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vote_7 IS PORT( DIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);-7位表決輸入(1:同意，0:不同意) G_4: OUT STD_LOGIC; -超過(guò)半數(shù)指示 CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);-表決結(jié)果統(tǒng)計(jì)數(shù) END vote_7; ARCHITECTURE BHV OF vote_7 IS BEGIN PROCESS(DIN) VARIABLE Q: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN Q:=000; FOR n IN 0 TO 6 LOOP - n是LOOP的循環(huán)變量 IF(DIN(n)=1) THEN Q:=Q+1; END IF; END LOOP; CNTH=4 THEN G_4=1; ELSE G_40); -計(jì)數(shù)器異步復(fù)位 ELSIF CLKEVENT AND CLK=1 THEN -檢測(cè)時(shí)鐘上升沿 IF EN=1 THEN -檢測(cè)是否允許計(jì)數(shù)或加載（同步使能） IF LOAD=0 THEN Q:=DATA; -允許加載 ELSE IF Q0); -大于等于9時(shí)，計(jì)數(shù)值清零 END IF; END IF; END IF; END IF; IF Q=9 THEN COUT=1; -計(jì)數(shù)大于9，輸出進(jìn)位信號(hào) ELSE COUT=0; END IF; DOUT 0); -計(jì)數(shù)器異步復(fù)位 ELSIF LOAD = 1 THEN CQI:=DATA; -LS_LOAD:=0; -計(jì)數(shù)器異步復(fù)位 ELSIF CLKEVENT AND CLK=1 THEN -檢測(cè)時(shí)鐘上升沿 IF ADD_EN=1THEN -檢測(cè)是否允許計(jì)數(shù)(同步他能) IF CQI 0); -大于65535,計(jì)數(shù)值清零 END IF; IF CQI=16#FFFF# THEN COUT=1; -計(jì)數(shù)大于9,輸出進(jìn)位信號(hào) ELSE COUT 0 THEN CQI:=CQI-1; -允許計(jì)數(shù),檢測(cè)是否小于65535 ELSE CQI:=(OTHERS = 1); -大于65535,計(jì)數(shù)值清零 END IF; IF CQI=0 THEN COUT=1; -計(jì)數(shù)大于9,輸出進(jìn)位信號(hào) ELSE COUT = 0; END IF; END IF; END IF; CQ=CQI; -將計(jì)數(shù)值向端口輸出 END PROCESS; END ARCHITECTURE A_S_16;5-9library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity m6 is port(clk,rst:in std_logic; q: out std_logic_vector(2 downto 0); end m6; architecture bhv of m6 is type states is(st0,st1,st2,st3,st4,st5); signal stx:states; begin process(clk) begin if rst=1 then stx=st0;qq=000;stxq=001;stxq=011;stxq=111;stxq=101;stxq=100;stx stx=st0; end case; end if; end process; end bhv;5-12 用同步時(shí)序電路對(duì)串行二進(jìn)制輸入進(jìn)行奇偶校驗(yàn)，每檢測(cè)5位輸入，輸出一個(gè)結(jié)果。當(dāng)5位輸入中1的數(shù)目為奇數(shù)時(shí)，在最后一位的時(shí)刻輸出1。-解：4-12 用同步時(shí)序電路對(duì)串行二進(jìn)制輸入進(jìn)行奇偶校驗(yàn)，每檢測(cè)5位輸入，輸出一個(gè)結(jié)果。- 當(dāng)5位輸入中1的數(shù)目為奇數(shù)時(shí)，在最后一位的時(shí)刻輸出1。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY odd_even_p_RXD_5 IS PORT(CLK,RST,S_in: IN STD_LOGIC;-CLK、RST、S_in:時(shí)鐘、復(fù)位、串行輸入數(shù)據(jù) P_out: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);-P_out:并行輸出數(shù)據(jù) o_e_out: OUT STD_LOGIC); -o_e_out:奇校驗(yàn)輸出位 END ENTITY odd_even_p_RXD_5; ARCHITECTURE one OF odd_even_p_RXD_5 IS BEGIN PROCESS(CLK,RST) VARIABLE shift_Q : STD_LOGIC_VECTOR(4 DOWNTO 0);-shift_Q:移位寄存器 VARIABLE shift_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);-shift_cnt:移位計(jì)數(shù)器 BEGIN IF CLKEVENT AND CLK=1 THEN -檢測(cè)時(shí)鐘上升沿 IF RST = 1 THEN shift_cnt:=100; -移位寄存器和計(jì)數(shù)器復(fù)位 ELSE IF shift_cnt=4 THEN -檢測(cè)到接收5位串行輸入數(shù)據(jù) shift_cnt:=000; -移位計(jì)數(shù)器清零，為接收下一組數(shù)據(jù)做準(zhǔn)備。 P_out=shift_Q;-接收數(shù)據(jù)并行輸出 o_e_out=shift_Q(4) XOR shift_Q(3) XOR shift_Q(2) XOR shift_Q(1) XOR shift_Q(0);-奇校驗(yàn)輸出 shift_Q:=S_in & shift_Q(4 DOWNTO 1);-采樣移位串行輸入 ELSE shift_cnt:=shift_cnt+1;-移位計(jì)數(shù) shift_Q:=S_in & shift_Q(4 DOWNTO 1);-采樣移位串行輸入 END IF; END IF; END IF; END PROCESS; END ARCHITECTURE one;5-5 分頻方法有多種，最簡(jiǎn)單的是二分頻和偶數(shù)分頻甚至奇數(shù)分頻，這用觸發(fā)器或指定計(jì)數(shù)模的計(jì)數(shù)器即可辦到。但對(duì)于現(xiàn)場(chǎng)實(shí)現(xiàn)指定分頻比或小數(shù)分頻率的分頻電路的設(shè)計(jì)就不是很簡(jiǎn)單了。 試對(duì)例3-20的設(shè)計(jì)稍作修改，將其進(jìn)位輸出COUT與異步加載控制LOAD連在一起，構(gòu)成一個(gè)自動(dòng)加載型16位二進(jìn)制數(shù)計(jì)數(shù)器，也即一個(gè)16位可控的分頻器，給出其VHDL表述，并說(shuō)明工作原理。設(shè)輸入頻率fi=4MHz，輸出頻率fo=516.51Hz(允許誤差0.1Hz)，16位加載數(shù)值是多少?-解：3-9 16位數(shù)控分頻器(可進(jìn)行奇偶數(shù)分頻)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DVF16 IS PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR(15 DOWNTO 0); FOUT : OUT STD_LOGIC);END ENTITY DVF16;ARCHITECTURE one OF DVF16 ISSIGNAL FULL : STD_LOGIC;BEGIN P_REG: PROCESS(CLK) VARIABLE CNT8 : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN IF CLKEVENT AND CLK = 1 THEN IF CNT8 = 0000000000000000 THEN CNT8 := D-1;-當(dāng)CNT8計(jì)數(shù)歸0時(shí)，預(yù)置CNT8=D-1; -計(jì)數(shù)范圍(D=n)：n-1n/2取整(n=10:98765計(jì)數(shù),前后半周期相同) FULL = 1;-同時(shí)使溢出標(biāo)志信號(hào)FULL輸出為高電平 -(n=11:1098765計(jì)數(shù),前比后半周期多一個(gè)時(shí)鐘) ELSIF CNT8 = (0 & D(15 DOWNTO 1) THEN CNT8 :=(0 & D(15 DOWNTO 1)-1;-當(dāng)CNT8=n/2取整時(shí)，預(yù)置CNT8=D/2取整-1; -計(jì)數(shù)范圍(D=n)：n/2取整0(n=10:43210計(jì)數(shù)) FULL = 1; -同時(shí)使溢出標(biāo)志信號(hào)FULL輸出為高電平 (n=11:43210計(jì)數(shù)) ELSE CNT8 := CNT8 - 1; -否則繼續(xù)作加1計(jì)數(shù) FULL = 0; -且輸出溢出標(biāo)志信號(hào)FULL為低電平 END IF; END IF; END PROCESS P_REG ; P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN IF FULLEVENT AND FULL = 1 THEN CNT2 := NOT CNT2;-如果溢出標(biāo)志信號(hào)FULL為高電平，D觸發(fā)器輸出取反 IF CNT2 = 1 THEN FOUT = 1; ELSE FOUT = 0; END IF; END IF; END PROCESS P_DIV;END ARCHITECTURE one;5-6 分別給出圖3-20所示的六個(gè)RTL圖的VHDL描述，注意其中的D觸發(fā)器和鎖存器的表述。圖3-20 RTL圖圖3-20 RTL圖（a）-解：實(shí)現(xiàn)圖3-20(a)RTL圖的VHDL程序t3_12_a.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY t3_12_a IS PORT (CL,CLK0: IN STD_LOGIC; OUT1: OUT STD_LOGIC); END ENTITY t3_12_a; ARCHITECTURE sxdl OF t3_12_a IS -時(shí)序電路sxdl SIGNAL Q : STD_LOGIC; BEGIN PROCESS(CLK0) BEGIN IF CLK0EVENT AND CLK0=1 THEN -檢測(cè)時(shí)鐘上升沿 Q = NOT(Q OR CL); END IF; END PROCESS; OUT1 = NOT Q; END ARCHITECTURE sxdl;圖3-20 RTL圖（b）-解：實(shí)現(xiàn)圖3-20(b)RTL圖的VHDL程序t3_12_b.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY t3_12_b IS PORT (A,B,C,D: IN STD_LOGIC; Y: OUT STD_LOGIC); END ENTITY t3_12_b; ARCHITECTURE sxdl OF t3_12_b IS -時(shí)序電路sxdl SIGNAL AB,CD,ABCD : STD_LOGIC; BEGIN PROCESS(A,B,C,D,AB,CD,ABCD) BEGIN AB=A OR B; CD=C AND D; ABCD Y Y NULL ; END CASE; END PROCESS; END ARCHITECTURE sxdl;圖3-20 RTL圖（c）-解1：實(shí)現(xiàn)圖3-20(c) RTL圖的VHDL程序mux21a.vhd底層設(shè)計(jì)描述。- 用(WHEN_ELSE)實(shí)現(xiàn)2選1多路選擇器程序(mux21a.vhd)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS PORT(a,b : IN STD_LOGIC; s : IN STD_LOGIC; y : OUT STD_LOGIC); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN y=a WHEN s=0 ELSE b; END ARCHITECTURE one;-解2：實(shí)現(xiàn)圖3-20(c)RTL圖的VHDL程序DFF6.vhd底層設(shè)計(jì)描述。- 電平觸發(fā)D型觸發(fā)器程序(DFF6.vhd) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF6 IS PORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUT STD_LOGIC); END; ARCHITECTURE bhv OF DFF6 IS BEGIN PROCESS(CLK,D) BEGIN IF CLK=1 THEN Q=D; END IF; END PROCESS; END bhv;-解3：實(shí)現(xiàn)圖3-20(c)RTL圖的VHDL程序t3_12_c.vhd頂層設(shè)計(jì)描述。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY t3_12_c IS PORT(D1,D2,CLK : IN STD_LOGIC; Q : OUT STD_LOGIC); END ENTITY t3_12_c; ARCHITECTURE one OF t3_12_c IS COMPONENT mux21a -調(diào)用2選1多路選擇器聲明語(yǔ)句 PORT(a,b : IN STD_LOGIC; s : IN STD_LOGIC; y : OUT STD_LOGIC); END COMPONENT; COMPONENT DFF6 -調(diào)用電平型D觸發(fā)器聲明語(yǔ)句 PORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUT STD_LOGIC); END COMPONENT; SIGNAL DD: STD_LOGIC; -定義1個(gè)信號(hào)作為內(nèi)部的連接線。 BEGIN u1: mux21a PORT MAP(CLK,D2,D1,DD); u2: DFF6 PORT MAP(CLK,DD,Q); END ARCHITECTURE one;圖3-20 RTL圖（d）-解1：實(shí)現(xiàn)圖3-20(d)RTL圖的VHDL程序DFF_PRE.vhd底層設(shè)計(jì)描述- 帶預(yù)置、清零和輸出使能的D觸發(fā)器程序(DFF_PRE.vhd)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF_PRE_CLR_ENA IS PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q :OUT STD_LOGIC; ENA : IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : IN STD_LOGIC); END; ARCHITECTURE bhv OF DFF_PRE_CLR_ENA IS SIGNAL Q1:STD_LOGIC; -類似于在芯片內(nèi)部定義一個(gè)數(shù)據(jù)的暫存節(jié)點(diǎn) BEGIN PROCESS(CLK,D,Q1,ENA,PRE,CLR) BEGIN IF CLR=1 THEN Q1=0; ELSIF PRE=1 THEN Q1=1; ELSIF CLKEVENT AND CLK=1 AND ENA=1 THEN Q1=D; END IF; -IF EN=1 THEN Q=Q1; -將內(nèi)部的暫存數(shù)據(jù)向端口輸出 -END IF; Q=Q1; -將內(nèi)部的暫存數(shù)據(jù)向端口輸出 END PROCESS; END bhv;-解2：實(shí)現(xiàn)圖3-20(d)RTL圖的VHDL程序t3_12_d.vhd頂層設(shè)計(jì)描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY t3_12_d IS PORT(SET,D,CLK,EN,RESET : IN STD_LOGIC; Q : OUT STD_LOGIC); END ENTITY t3_12_d; ARCHITECTURE one OF t3_12_d IS COMPONENT DFF_PRE_CLR_ENA -調(diào)用D觸發(fā)器聲明語(yǔ)句 PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q :OUT STD_LOGIC; ENA : IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : IN STD_LOGIC); END COMPONENT; SIGNAL SS: STD_LOGIC; -定義1個(gè)信號(hào)作為內(nèi)部的連接線。 BEGIN SS=SET AND (NOT RESET); u1: DFF_PRE_CLR_ENA PORT MAP(CLK,D,Q,EN,SS,RESET); END ARCHITECTURE one;圖3-20 RTL圖（e）-解1：實(shí)現(xiàn)圖3-20(e)RTL圖的VHDL程序DFF_PRE_CLR.vhd底層設(shè)計(jì)描述- 帶預(yù)置、清零和輸出使能的D觸發(fā)器程序(DFF_PRE_CLR.vhd) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF_PRE_CLR_ENA IS PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q :OUT STD_LOGIC; ENA : IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : IN STD_LOGIC); END; ARCHITECTURE bhv OF DFF_PRE_CLR_ENA IS SIGNAL Q1:STD_LOGIC; -類似于在芯片內(nèi)部定義一個(gè)數(shù)據(jù)的暫存節(jié)點(diǎn) BEGIN PROCESS(CLK,D,Q1,ENA,PRE,CLR) BEGIN IF CLR=1 THEN Q1=0; ELSIF PRE=1 THEN Q1=1; ELSIF CLKEVENT AND CLK=1 AND ENA=1 THEN Q1=D; END IF; -IF EN=1 THEN Q=Q1; -將內(nèi)部的暫存數(shù)據(jù)向端口輸出 -END IF; Q=Q1; -將內(nèi)部的暫存數(shù)據(jù)向端口輸出 END PROCESS; END bhv;-解2：實(shí)現(xiàn)圖3-20(e)RTL圖的VHDL程序t3_12_d.vhd頂層設(shè)計(jì)描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY t3_12_e IS PORT(D,EN,CLK,RST : IN STD_LOGIC; Q1,Q : OUT STD_LOGIC); END ENTITY t3_12_e; ARCHITECTURE one OF t3_12_e IS COMPONENT DFF_PRE_CLR_ENA -調(diào)用D觸發(fā)器聲明語(yǔ)句 PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q :OUT STD_LOGIC; ENA : IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : IN STD_LOGIC); END COMPONENT; SIGNAL D_EN: STD_LOGIC; -定義1個(gè)信號(hào)作為內(nèi)部的連接線。 BEGIN D_ENCLK,D=D,Q=Q,ENA=EN,PRE=0,CLR=RST); Q1=(NOT D_EN) OR RST; END ARCHITECTURE one;圖3-20