計(jì)算機(jī)組成原理ddca_ch4_h

1、Digital Design and Computer ArchitectureChapter 4 Chapter 4IntroductionCombinational Logic Structural Modeling Sequential LogicMore Combinational Logic Finite State Machines Parameterized ModulesTestbenchesChapter 4 Chapter 4 : TopicsHardware description language (HDL): specifies logic function only

2、 Computer-aided design (CAD) tool produces orsynthesizes the optimized gatesMost commercial designs built using HDLs Two leading HDLs: System Verilog VHDL 2008Chapter 4 IntroductionTwo leading HDLs: System Verilogdeveloped in 1984 by Gateway Design AutomationIEEE standard (1364) in 1995Extended in 2

3、005 (IEEE STD 1800-2009) VHDL 2008Developed in 1981 by the Department of DefenseIEEE standard (1076) in 1987Updated in 2008 (IEEE STD 1076-2008)Chapter 4 Introduction補(bǔ)充背景知識(shí)一、可編程邏輯器件(PLD)n PLD是可編程邏輯器件（Programmable Logic Device）的英文縮寫n PLD是EDA得以實(shí)現(xiàn)的硬件基礎(chǔ)n EDA是電子設(shè)計(jì)自動(dòng)化(Electronic Design Automation)的縮寫n 在20

4、世紀(jì)90年代初從計(jì)算機(jī)輔助設(shè)計(jì)（CAD）、計(jì)算機(jī)輔助制造（CAM）、計(jì)算機(jī)輔助測(cè)試（CAT）和計(jì)算機(jī)輔助工程（CAE） 的概念發(fā)展而來的。n PLD通過編程，可靈活方便地構(gòu)建和修改數(shù)字電子系統(tǒng)。補(bǔ)充背景知識(shí)一、PLD的分類目前使用的PLD器件根據(jù)集成度和結(jié)構(gòu)復(fù)雜度不同，分為：n 簡(jiǎn)單可編程邏輯器件（SPLD）n 可編程的與矩陣、不可編程的或矩陣、輸出宏單元、輸入/輸出單元n Lattice生產(chǎn)的GAL16V8、GAL22V10n 復(fù)雜可編程邏輯器件（CPLD）n 采用乘積項(xiàng)、EEPROM（或Flash）工藝n Altera公司的MAX7000n 現(xiàn)場(chǎng)可編程門矩陣（FPGA）n 采用矩陣式結(jié)構(gòu)分

5、布，擁有更多的觸發(fā)器和布線資源，多用于10000門以上的大規(guī)模設(shè)計(jì)，適合做復(fù)雜時(shí)序邏輯。補(bǔ)充背景知識(shí)VCC12V與陣列3.9kDAR在二極管與門的各支路與輸出之間接入熔絲。熔絲保留的各支路的輸入為有效輸入，輸出F是熔絲保留各支路輸入的與邏輯函數(shù)。圖 (b)是PLD表示。AFDB+VBCC熔絲RF（A，B，C）A A B B C CA AB C CB F ( A ，B ，C) = 0(a)(b)圖 (a)和圖 (b)是熔絲全部保留的與陣列表示情況。補(bǔ)充背景知識(shí)PLD中陣列交叉點(diǎn)的邏輯表示PLD邏輯陣列中交叉點(diǎn)的連接方式采用圖7-7所示的幾種邏輯表示。 (a)(b)(c) (a)表示實(shí)體連結(jié)，就是

6、行線和列線在這個(gè)交叉點(diǎn)處實(shí)在連接，這個(gè)交叉點(diǎn)是不可編程點(diǎn)，在交叉點(diǎn)處打上實(shí)心點(diǎn)。 (b)表示可編程連接。無論或表示該符號(hào)所在行線和列線交叉處是可編程點(diǎn)，具有一個(gè)可編程單元。 (c)表示熔絲燒斷的可編程點(diǎn)上的消失，行線和列線不相接。補(bǔ)充背景知識(shí)與門及或門的表示ABCABCA B CYYYABCA B CYY1&補(bǔ)充背景知識(shí)與陣列如圖(a)所示。在二極管與門的各支路與輸出之間接入熔絲。熔絲保留的各支路的輸入為有效輸入，輸出F是熔絲保留各支路輸入的與邏輯函數(shù)。圖 (b)是PLD表示。+VCC熔絲RF（A，B，C）A A B B C CAAB CCB F ( A ，B ，C) = 0(b)(a)圖 (

7、a)和圖 (b)是熔絲全部保留的與陣列表示情況。補(bǔ)充背景知識(shí)圖(c)是燒斷3個(gè)熔絲的情況，圖(d)是圖(c)的PLD表示。+VCC熔絲RF(A,B,C)=ABCA A B B C CAABBCCF (A，B，C)=ABC(c)(d)補(bǔ)充背景知識(shí)與門及或門的表示p1 p2p3f (p pp )=p+p1,2,313Rp1p2p3(c)f (p1,p2,p3)=p1+p3(d)補(bǔ)充背景知識(shí)與或陣列圖任一組合邏輯函數(shù)都可用“與或”式表示，即任何組合邏輯函數(shù)都可以用一個(gè)與門陣列與一個(gè)或門陣列來實(shí)現(xiàn)。如：Y1 ( A, B) = m(1,2) = AB + ABY2 ( A, B) = m(0,3) =

8、 AB + AB AA BBAB或陣列或陣列YY與陣列與陣列12簡(jiǎn)化畫法標(biāo)準(zhǔn)畫法Y1 Y 2補(bǔ)充背景知識(shí)利用效率低。例：可編程只讀存儲(chǔ)器PROM或陣列(可編程)A2A1A0實(shí)現(xiàn)組合邏輯函數(shù)： 將函數(shù)寫為最小項(xiàng)之和形式，將對(duì)應(yīng)的與項(xiàng)或起來即可。完全譯碼陣列容量與門數(shù)或門數(shù)2nm與陣列(固定)D2 D1 D0補(bǔ)充背景知識(shí)例：試用PROM實(shí)現(xiàn)4位二進(jìn)制碼到Gray碼的轉(zhuǎn)換。A3A2A1A0轉(zhuǎn)換真值表或陣列與陣列D3D2 D1D0輸入輸出A3A2A1A0D3D2D1D00000000000010001001000110011001001000110010101110110010101110100100

9、0110010011101101011111011111011001010110110111110100111111000補(bǔ)充背景知識(shí)例：可編程邏輯陣列PLA制造工藝復(fù)雜?；蜿嚵?可編程)A2A1A0實(shí)現(xiàn)組合邏輯函數(shù)：將 函數(shù)化簡(jiǎn)為最簡(jiǎn)與或式， 將對(duì)應(yīng)的與項(xiàng)或起來即 可。容量與門數(shù)或門數(shù)與陣列(可編程)D2 D1 D0補(bǔ)充背景知識(shí)二、可編程專用集成電路ASIC可編程專用集成電路ASIC(Application SpecificIntegrated Circuit) 是面向用戶特定用途或特定功能的大規(guī)模、超大規(guī)模集成電路。 分類：按功能分為數(shù)字的、模擬的、數(shù)字和模擬混和三種。按制造方式分為全定制

10、、半定制ASIC、可編程三種。 根據(jù)芯片的集成度和結(jié)構(gòu)復(fù)雜度分補(bǔ)類充背景知識(shí)簡(jiǎn)單可編程邏輯器件SPLD 特點(diǎn)是都具有可編程的與陣列、不可編程的或陣列、輸出邏輯宏單元OLMC和輸入輸出邏輯單元IOC。 復(fù)雜可編程邏輯器件CPLD 特點(diǎn)是具有更大的與陣列和或陣列，增加了大量的宏單元和布線資源，觸發(fā)器的數(shù)量明顯增加。 現(xiàn)場(chǎng)可編程邏輯門陣列 FPGA 運(yùn)算器、乘法器、數(shù)字濾波器、二維卷積器等具 有復(fù)雜算法的邏輯單元和信號(hào)處理單元的邏輯設(shè)計(jì)可選用FPGA實(shí)現(xiàn)。 補(bǔ)充背景知識(shí)按制造技術(shù)和編程方式進(jìn)行分類雙極熔絲制造技術(shù)的可編程A雙SI極C 熔絲和反熔絲ASIC通 萊迪思(Lattice)半導(dǎo)體公司的P 常

11、稱為OTP (one timeprogramming)器件反熔絲制造技術(shù)的可編程 Actel的FPGAEECMOS制造技術(shù)的可編程ASIC采用EECMOS和SRAM制造 Lattice的GAL和ispLSI / pLSISRAM制造技術(shù)的可編程ASIC 技術(shù)的可編程ASIC具有用戶可重復(fù)編程的特性，可以實(shí)現(xiàn)電擦電寫。 Xilinx的FPGA，Altera的FPGA補(bǔ)充背景知識(shí)按制造技術(shù)和編程方式進(jìn)行分類用SRAM技術(shù)制造的FPGA則具有數(shù)據(jù)揮發(fā)性，又稱易失性。具有揮發(fā)性的FPGA ，當(dāng)系統(tǒng)斷電或掉電后，寫入FPGA中的編程數(shù)據(jù)要丟失。因此，必須把要下載到FPGA的數(shù)據(jù)借用編程器固化到與其聯(lián)用的

12、EPROM或EEPROM中，待重新上電時(shí)，芯片將編程數(shù)據(jù)再下載到FPGA中。 FPGA的數(shù)據(jù)揮發(fā)性，決定有些環(huán)境不宜選用。 可采用專用編程器進(jìn)行編程 補(bǔ)充背景知識(shí)可編程ASIC的一般開發(fā)步驟設(shè)計(jì)輸入(entry)功能模擬(function simulation)邏輯分割(partitioning)布局和布線(place and routing)時(shí)間模擬(timing simulation)寫入下載數(shù)據(jù)(download)補(bǔ)充背景知識(shí)ASIC開發(fā)步驟流程圖狀態(tài)機(jī)輸入波形輸入邏輯圖輸入HDL輸入設(shè)計(jì)輸入NN功能模擬時(shí)間模擬YY邏輯分割編程下載器件驗(yàn)證 設(shè)計(jì)輸入布局布線 SimulationInpu

13、ts applied to circuit Outputs checked for correctnessMillions of dollars saved by debugging tead of hardwareimulationSynthesisTransforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them)IMPORTANT:When using an HDL, think of the hardware the HDL sho

14、uld produceChapter 4 HDL to Gatesa b cVerilog ModuleyTwo types of Modules: Behavioral: describe what a module does Structural: describe how it is built from simpler modulesChapter 4 SystemVerilog ModulesSystemVerilog:module example(inputoutputlogic logica, b,y);c,assign y=aa a& & &bbb& & &cc c;|endm

15、oduleChapter 4 Behavioral SystemVerilogSystemVerilog:module example(inputlogicoutput logica, b,y);c,assign y=aa a& & &bbb& & &cc c;|endmoduleChapter 4 HDL SimulationSystemVerilog:module example(inputlogicoutput logica, b,y);c,assign y =aa a& & &bbb& & &cc c;|endmodulebcyun5_ySynthesis:yaun8_yChapter

16、 4 HDL SynthesisCase sensitive Example: reset and Reset are not the same signal.No names that start with numbers Example: 2mux is an invalid nameWhitespace ignored Comments:/*single line commentmultilinecomment*/Chapter 4 SystemVerilog Syntaxmoduleand3(inputoutputlogic a, b, logic y);& c;c,assign y

17、= a & bEndmodulemoduleinv(inputoutputlogic logica, y);assign y = a; Endmodulemodule nand3(inputoutputlogic n1;logic logica,b, cy);/internalsignaland3 invandgate(a, b, c, n1); inverter(n1, y);/tance tanceof and3of inverterendmoduleChapter 4 Structural Modeling - Hierarchymodulegates(inputlogic 3:0a,

18、b,outputlogic 3:0 y1, y2,y3,y4,y5);/* Five different two-input logicgates actingon b;b;b;4bit/busses */ ANDOR XOR NAND NORassign assign assign assign assign endmoduley1 y2 y3 y4 y5=a a a&|(a(a& b);| b);Bitwise Operatorsmodule and8(inputlogic 7:0 a,output logicy);assign y = &a;/&a is mucheasierto wri

19、te thanassigny=a7a3&a6a2&a5a1&a4 &a0;endmoduleChapter 4 Reduction Operatorsmodule mux2(inputinput outputlogic logic logic3:0d0,s, y);d1,3:0assigny=s?d1:d0;endmoduleis also called a ternary operator because it operates on 3 inputs: s, d1, and d0.?:Chapter 4 Conditional Assignmentmodule fulladder(inpu

20、tlogic a, b,cin,output logic s, cout);logic p,g;/ internal nodesassign assignp g=a a &b;b;assign assigns=pcin;cout=g|(p&cin);endmodulessgcincouta bcoutChuanp1t_ecro4upInternal VariablesOrder of operationsHighestLowestChapter 4 NOT*, /, %mult, div, mod+, -add,subshiftarithmetic shift, , =comparison=,

21、 !=equal, not equal&, &AND, NAND, XOR, XNOR|, |OR, NOR?:ternary operatorPrecedenceFormat: NBvalueN = number of bits, B = baseNB is optional but recommended (default is decimal)Chapter 4 Number# BitsBaseDecimal EquivalentStored3b1013binary5101b11unsizedbinary30000118b118binary3000000118b1010_10118bin

22、ary171101010113d63decimal61106o426octal341000108hAB8hexadecimal1711010101142Unsizeddecimal42000101010Numbersassign y = a2:1, 3b0, a0, 6b100_010;/ if y is a 12-bit signal, the above statement produces:y = a2 a1 b0 b0 b0 a0 1 0 0 0 1 0/ underscores (_) are used for formatting onlytomake it them.easier

23、toread.SystemVerilogignoresChapter 4 Bit Swizzling : Example 1SystemVerilog:modulemux2_8(inputinput outputlogic logic logic7:0d0, d1, s,y);7:0mux2 mux2lsbmux(d03:0,msbmux(d07:4,d13:0,d17:4,s,s,y3:0);y7:4);endmodulemux2s d07:0d17:0s7:03:03:07:0 y7:0d03:0d13:0y3:07:03:0lsbmuxmux2s7:47:4d03:0d13:0y3:07

24、:4msbmuxBit Manipulations: Example 2SystemVerilog:module tristate(inputinput outputlogic logic logic4bz;3:0a,en, y);3:0assign yendmodule=en ?a :ena3:03:03:03:03:0 y3:0y_13:0Chapter 4 Z: Floating OutputSystemVerilog uses Idioms to describe latches, flip-flops and FSMsOther coding styles may simulate

25、correctly but produce incorrect hardwareChapter 4 Sequential LogicGeneral Structure:always (sensitivity list)statement;Whenever the eventensitivitylist occurs,statement is executedChapter 4 Always Statementmodule flop(inputinput outputlogic logic logicclk, d, q);3:03:0always_ff (posedge clk)q = d;/p

26、ronounced“qgetsd”endmoduleChapter 4 D Flip-Flopmodule flopr(inputinput input outputlogic logic logic logicclk, reset, d, q);3:03:0/ synchronous resetalways_ff (posedge clk)if (reset) elseq q=4b0;d;endmoduleclk d3:0resetq3:0q3:0Chapter 4 3:03:03:03:0D3:0Q3:0RResettable D Flip-Flopmodule flopr(inputin

27、put input outputlogic logic logic logicclk, reset,3:0 d,3:0 q);/ asynchronous resetalways_ff (posedge clk,posedgereset)if (reset) elseq q=4b0;d;endmoduleclk d3:03:03:03:0D3:0Q3:03:0 q3:0Rresetq3:0Chapter 4 Resettable D Flip-Flopmodule flopren(inputinput input input outputlogic logic logic logic logi

28、cclk, reset, en,3:0 d,3:0 q);/ asynchronousresetalways_ff ifelse if(posedgeclk, posedgereset)(reset) (en)q q=4b0;d;endmoduleChapter 4 D Flip-Flop with Enablemodule latch(inputinput outputlogic logic logicclk, d, q);3:03:0always_latchif (clk)q =d;endmoduled3:0clk 3:03:0q3:0Warning: We dont use latche

29、s in this text. But you might write code that inadvertently implies a latch. Check synthesized hardware if it has latches in it, theres an error.Chapter 4 3:03:0latD3:0Q3:0 Cq3:0Latch always （*）Statements that must be if / else case, casezide always statements:Chapter 4 Other Behavioral Statements/

30、combinational logic using analways statement a, b,y1, y2, y3, y4, y5);module gates(inputoutputlogic 3:0logic3:0always_comb beginalways/need begin/end because thereismore thanonestatementiny1 y2 y3 y4 y5endendmodule=a aa&|b;b;b;& b);| b);/AND OR XOR NANDNOR(a(aThis hardware could be described with as

31、sign statements using fewer lines of code, so its better to use assign statements in this case.Chapter 4 Combinational Logic using alwaysmodule mux8_1(inputlogiclogic7:0 a,2:0 addr,outputlogicb);modulemux8_1(inputlogic logiclogic7:0 a,2:0 addr, b);assign b =/8選1數(shù)據(jù)選擇output（addr = 3d0） ? a0 :（addr = 3

32、d1） （addr = 3d2） ? a2 :（addr = 3d3）always (*)/8選1數(shù)據(jù)選擇器case ( addr)/只有當(dāng)a以及addr有變化時(shí)，才觸發(fā)case的操作 3d0: b = a0;3d1: b = a1;（addr = 3d4） ? a4 :（addr = 3d5）（addr = 3d6） ? a6 : a7;endmodule3d2: b = a2;3d3: b = a3; 3d4: b = a4; 3d5: b = a5; 3d6: b = a6; 3d7: b = a7;endcaseendmoduleCombinational Logic using al

33、waysmodule sevenseg(inputoutputalways_comblogiclogic3:0 data,6:0 segments);case/ 0:1:2:3:4:5:6:7:8:9:(data)abc_defg 7b111_1110;7b011_0000;7b110_1101;7b111_1001;7b011_0011;7b101_1011;7b101_1111;7b111_0000;7b111_1111;7b111_0011;7b000_0000;segments segments segments segments segments segments segments

34、segments segmentssegments=default: segments endcaseendmodule=/requiredChapter 4 Combinational Logic using caseimplies combinational logic case statementonly if all possible input combinations describedRemember to use default statementChapter 4 Combinational Logic using casemodule priority_casez(inpu

35、toutputalways_comb casez(a)logic 3:0 a,logic 3:0 y);4b1?:4b01?:4b001?:4b0001:default: endcaseendmoduley y y yy=4b1000;4b0100;4b0010;4b0001;4b0000;/?=dontcareChapter 4 Combinational Logic using casezThree blocks: next state logic state register output logicCLKMnextkkNnextoutput logicinputsstate outpu

36、ts state state logicChapter 4 Finite State Machines (FSMs)S2S0S1The double circle indicates the reset stateChapter 4 FSM Example: Divide by 3module divideby3FSM (input logic clk, input logic reset,typedef enum logic 1:0 S0, S1, S2 statetype; statetype 1:0 state, nextstate;/ state registeralways_ff (

37、posedge clk, posedge reset) if (reset) state = S0;output logic q);elsestate = nextstate;/ next state logicalways_combcase (state)S0:S1:S2:nextstate = S1;nextstate = S2;nextstate = S0;default: nextstate = S0;endcase/ output logicassign q = (state = S0); endmoduleChapter 4 FSMystemVerilog2:1 mux:modul

38、e mux2#(parameter width = 8)/name and default d0, d1,s, y);value(input input outputassign y endmodulelogic logic logic= s ?width-1:0width-1:0d1 : d0;tance with 8-bit bus width (uses default):mux2 mux1(d0, d1, s, out);tance with 12-bit bus width:mux2 #(12) lowmux(d0, d1, s, out);Chapter 4 Parameteriz

39、ed ModulesHDL that tests another module: deviceunder test (dut)Not synthesizeable Types: Simple Self-checking Self-checking with testvectorsChapter 4 TestbenchesWrite SystemVerilog code to implement the followingfunction in hardware:y=bc+abName the module sillyfunctionChapter 4 Testbench ExampleWrit

40、e SystemVerilog code to implement the followingfunction in hardware:y=bc+abName the module sillyfunctionmodulesillyfunction(inputoutputlogiclogica,y);b,c,assignendmoduley=b&c|a&b;Chapter 4 Testbench Examplemodule testbench1();logic logic/a,y;b,c;tantiate device under testsillyfunctiondut(a, b, c, y)

41、;/ apply inputsinitial beginone ata timea c b c a c b cend=0;1;1;1;1;1;1;1;b = 0;#10;c = 0;#10;b = 0;#10;c = 0;#10;c = 0;#10;#10;c = 0;#10;#10;endmoduleChapter 4 Simple Testbenchmodule testbench2(); logica, b, c; logic y;sillyfunction dut(a, b, c, y);/tantiate dutinitial begin / apply inputs, check results timea = 0; b = 0; c = 0; #10;oneataif (y != 1) $display(000 c = 1; #10;if (y != 0) $display(001 b = 1; c = 0; #10;if (y != 0) $display(010 c = 1; #10;if (y != 0) $display(011 a = 1; b = 0; c = 0; #10;if (y != 1) $display(100 c = 1; #10;if (y != 1) $display(