電子線路講義相關(guān)ic第十章tc14433

1、TC14433 TC14433A3-1/2 DIGIT A/D CONVERTERSFEATURESGENERAL DESCRIPTIONThe TC14433 is a low power, high-performance, mono- lithic CMOS 3-1/2 digit A/D converter. The TC14433 com- bines both analog and digital circuits on a single IC, thus minimizing the number of external components. This dual- slope

2、A/D converter provides automatic polarity and zero correction with the addition of two external resistors and two capacitors. The full-scale voltage range of this ratiometric IC extends from 199.9 millivolts to 1.999 volts. The TC14433 can operate over a wide range of power supply voltages, includin

3、g batteries and standard 5-volt supplies.The TC14433 will interface with the TC7211A LCD display driver.The TC14433A features improved performance over the industry standard TC14433. Rollover, which is the measurement of identical positive and negative signals, is guaranteed to have the same reading

4、 within one count for the TC14433A. Power consumption of the TC14433A is typically 4 mW, approximately one-half that of the industry standard TC14433.Accuracy0.05% of Reading 1 CountTwo Voltage RangesV and 199.9 mVUp to 25 Conversions Per Second ZIN 1000M OhmsSingle Positive Voltage Reference Auto-P

5、olarity and Auto-ZeroOverrange and Underrange Signals Available Operates in Auto-Ranging CircuitsUses On-Chip System Clock or External Clock Wide Supply Range . e.g., 4.5V to 8VPackage Available. 24-Pin DIP 324-Pin CerDIP, 28-POIC and 28-Pin PLCCAPPLICATIONS Portabletruments Digital Voltmeters Digit

6、al Panel Meters Digital Scales Digital Thermometers Remote A/D Sensing Systems MPU Systems See Application Notes 19 and 21ORDERING INFORMATIONPart No.PackageTemp.Range 40C to +85C 40C to +85CTC14433AEJG24-Pin CerDIPTC14433AELI28-Pin PLCC24-Pin Plastic DIP 40C to +85CTC14433AEPG0C to +70C 40C to +85C

7、TC14433COG24-POICTC14433EJG24-Pin CerDIP 40C to +85CTC14433ELI28-Pin PLCCTC14433EPG24-Pin Plastic DIP 40C to +85CFUNCTIONAL BLOCK DIAGRAMTC14433/A-6 10/21/963-127TELCOM SEMICONDUCTOR, INC.2023Q0 Q3 BCD DATAMULTIPLEXERRC1619DS1DS 4DIGIT STROBE10CLK1LATCHESPOLARITY DETECT1S10S100S1,000SOVERFLOW15 OR O

8、VERRANGECMOS2VREF REFERENCE VOLTAGECONTROLANALOG1VAG ANALOG GROUNDLOGIC SUBSYSTEM3VXANALOG INPUT45678VDD = PIN 24R1 R1 / C1C1 CO1CO2VSS = PIN 13DISPLAY 9 14 END OFVEE = PIN 12UPDATECONVERSIONDUEOCINTEGRATOROFFSETCLOCK11CLK03-1/2 DIGIT A/D CONVERTERSTC14433TC14433AABSOLUTE MAXIMUM RATINGS*Supply Volt

9、age (VDD VEE)V to +18VVoltage on Any Pin,SOIC940mWCerDIP1.45WStorage Temperature Range65C to +160CLead Temperature (Soldering, 10 sec)+300C*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the spec

10、ifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Reference to VEE0.5V to (VDD +0.5)DC Current, Any Pin10mAOperating Temperature Range40C to +85CPower Dissipation (TA 70C)Plastic PLCC1.0WPlastic DIP940mWELECTRICAL CHARACTERIS

11、TICS:VDD = +5V, VEE = 5V, C1 = 0.1mF (mylar), CO = 0.1mF, RC = 300kW, R1 =470kW VREF = 2V, R1 = 27kW VREF = 200mV, unless otherwise specified.Analog InputDigitalPowerTELCOM SEMICONDUCTOR, INC.3-128IQQuiescent CurrentVDD to VEE, ISS = 0, 14433A:VDD = 5, VEE = 5 VDD = 8, VEE = 8VDD to VEE, ISS = 0, 14

12、433: VDD = 5, VEE = 5VDD = 8, VEE = 80.41.40.91.824243.77.43.77.4mAPSRRSupply RejectionVDD to VEE, ISS = 0, VREF = 2VVDD = 5, VEE = 50.5mV/VVOLOutput VoltageVSS = 0V,0 Level P14 to 23 (Note 3)VSS = 5V,0 Level0 50.054.950.05 4.95VVOHOutput VoltageVSS = 0V,1 Level P14 to 23 (Note 3)VSS = 5V,1 Level4.9

13、54.95554.954.95VIOHOutput CurrentVSS = 0V, VOH = 4.6V Source P14 to 23VSS = 5V, VOH = 5V Source 0.2 0.5 0.36 0.9 0.14 0.35mAIOLOutput CurrentVSS = 0V, VOL = 0.4V SinkP14 to 23VSS = 5V, VOL = 4.5V Sink0.511.30.882.250.360.9mAfCLKClock FrequencyRC = 300kW66kHzIDUInput Current DU0.000010.31mASYERollove

14、r Error (Positive200mV Full Scale VIN1+1CountsNLLinearity OutputVREF = 2V Reading (Note 1)VREF = 200mV 0.05 1 count+0.05+0.05+1 count%rdgSORStability Output ReadingVX = 1.99V, VREF = 2V (Note 2)VX = 199mV, VREF = 200mV23LSDZORZero Output ReadingVX = 0V, VREF = 2V00LSDIINBias Current: Analog Input Re

15、ference Input Analog Ground202020100100500pACMRRCommon-Mode Rejection VX = 1.4V, VREF = 2V,fOC = 32kHz65dBSymbol ParameterTest ConditionsTA = +25C 40C TA +85CUnitMinTypMaxMinTypMax3-1/2 DIGIT A/D CONVERTERSTC14433 TC14433ANOTES: 1.Accuracy The accuracy of the meter at full-scale is the accuracy of t

16、he setting of the reference voltage. Zero is recalculated during each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs other than positive full-scale and zero is defined as the linearity specification.The LSD stability for

17、 200mV scale is defined as the range that the LSD will occupy 95% of the time. Pin numbers refer to 24-pin DIP.2.3.PIN CONFIGURATIONS 3TELCOM SEMICONDUCTOR, INC.3-129CLK1 CLK0VEENC VSS EOCORVX VREF VAG NCVDD Q3 Q2VAG 124 VDDVAG 124 VDDVREF 223 Q3VREF 223 Q3VX 322 Q2VX 322 Q2R1 421 Q1R1 421 Q1R1/C1 5

18、 20 Q0R1/C1 520 Q0C1 6 TC14433AEPG 19 DS1C1 619 DS1CO1 7 TC14433EPG 18 DS2CO1TC14433COGDS 7(SOIC)182CO2 8 TC14433AEJG 17 DSCO2 817 DSTC14433EJG33DU 9(PDIP)16 DS4DU 916 DS4(CerDIP)CLK1 1015 ORCLK1 1015 ORCLK0 1114 EOCCLK0 1114 EOCVEE 1213 VSSVEEVSS12134321 28 27 26R1Q1R1/C1 624 Q0C1 7 23 DS1NC 8TC144

19、33AELI22 NCCO1 9TC14433ELI21 DS2CO2 10(PLCC)20 DS3DU 1119 DS412 13 14 15 16 17 185253-1/2 DIGIT A/D CONVERTERSTC14433 TC14433APIN DESCRIPTIONSPin No. 24-PinPDIP/CerDipPin No.Pin No. 28-Pin PLCCSymbolDescription112VAGThis is the analog ground; it has a high input impedance This pin determines the ref

20、erence level for the unknown input voltage (VX) and the reference voltage (VREF).223VREFReference voltage Full-scale output is equal to the voltage applied to VREF. Therefore, full-scale voltage of 1.999V requires 2V reference and199.9 mV full-scale requires a 200 mV reference. VREF functions as sys

21、tem reset also. When switched to VEE, the system is reset to the beginning of the conversion cycle.334VXThe unknown input voltage (VX) is measured as a ratio of the reference voltage (VREF) in a ratiometric A/D conversion.445R1These pare for external components used for the integration function inth

22、e dual slope conversion. Typical values are 0.1 mF (mylar) capacitor for C1.556R1/C1R1 = 470 kW (resistor) for 2V full-scale.667C1R1 = 27 kW (resistor) for 200 mV full-scale. Clock frequency of 66 kHz gives 250 msec conversion time. See equation below for calculation of integrator component values.

23、779CO1These pare used for connecting the offset correction capacitor. Therecommended value is 0.1 mF.8810CO29911DUDisplay update input pin When DU is connected to the EOC output every conversion is displayed. New data will be strobed into the output latches during the conversion cycle if a positive

24、edge is received on DU prior to the ramp-down cycle. When this pin is driven from an external source, the voltage should be referenced to VSS.101012CLK1Clock input p The TC14433 has its own oscillator system clock.Connecting a single resistor between CLK1 and CLK0 sets the clock frequency.111113CLK0

25、A crystal or OC circuit may beerted in lieu of a resistor for improvedCLK1, the clock input, can be driven from an external clock source,which need only have standard CMOS output drive. This pin is referenced to VEE for external clock inputs. A 300 kW resistor yields a clock frequency of about 66 kH

26、z. (See typical characteristic curves; see Figure 9 for alternate circuits.)VEE121214Negative power current Connection pin for the most negative supply. Please note the current for the output drive circuit is returned through VSS. Typical supply current is 0.8 mA.131316VSSNegative power supply for o

27、utput circuitry This pets the low voltage levelfor the output p(BCD, Digit Selects, EOC, OR). When connected to analogground, the output voltage is from analog ground to VDD. If connected to VEE, the output swing is from VEE to VDD. The recommended operating range for VSS is between the VDD 3 volts

28、and VEE.141417EOCEnd of conversion output generates a pulse at the end of each conversion cycle. This generated pulse width is equal to one-half the period of the system clock.151518OROverrange pin Normally this pin is set high. When VX exceeds VREF the OR pin is low.TELCOM SEMICONDUCTOR, INC.3-1303

29、-1/2 DIGIT A/D CONVERTERSTC14433 TC14433APIN DESCRIPTIONS (Cont.)Pin No. 24-PinPDIP/CerDipPin No.Pin No. 28-Pin PLCCSymbolDescription161619DS4Digit select p The digit select output goes high when the respective digitis selected. The MSD (1/2 digit) turns on immediately after an EOC pulse.171720DS3Th

30、e remaining digits turn onequence from MSD to LSD.181821DS2To ensure that the BCD data has settled, an inter-digit blanking time of two clock periods is included. 3191923DS1Clock frequency divided by 80 equals multiplex rate. For example, a system clock of 60 kHz gives a multiplex rate of 0.8 kHz.20

31、2024Q0See Figure 12 for digit select timing diagram.212125Q1BCD data output p Multiplexed BCD outputs contain three full digits ofinformation during digit select DS2, DS3, DS4.222226Q2During DS1, the 1/2 digit, overrange, underrange and polarity information is available.232328Q3Refer to truth table.

32、242428VDDPositive power supply This is the most positive power supply pin.8,15, 22NCNot Used.voltage of the comparator is stored in the offset latches for later use in the auto-zero process. The time for this segment is variable and less than 800 clock periods.CIRCUIT DESCRIPTIONThe TC14433 CMOS IC

33、becomes a modified dual- slope A/D with a minimum of external components. This IC has the customary CMOS digital logic circuitry, as well as CMOS analog circuitry. It provides the user with digital functions (such as counters, latches, multiplexers) and analog functions (such as operational amplifie

34、rs and com- parators) on a single chip.Features of this system include auto-zero, high input impedances and auto-polarity. Low power consumption and a wide range of power supply voltages are also advan- tages of this CMOS device. The systems auto-zero function compensates for the offset voltage of t

35、he internal amplifiers and comparators. In this ratiometric system, the output reading is the ratio of the unknown voltage to the reference voltage, where a ratio of 1 is equal to the maximum count of 1999. It takes approximately 16,000 clock periods to com- plete one conversion cycle. Each conversi

36、on cycle may be divided into 6 segments. Figure 7 shows the conversion cycle in 6 segments for both positive and negative inputs. Segment 1 The offset capacitor (CO), which com- pensates for the input offset voltages of the buffer and integrator amplifiers, is charged during this period. How- ever,

37、the integrator capacitor is shorted. This segmentrequires 4000 clock periods.Segment 2 During this segment, the integrator output decreases to the comparator threshold voltage. At this time, a number of counts equivalent to the input offsetTELCOM SEMICONDUCTOR, INC.Figure 7. Integrator Waveforms at

38、Pin 6Figure 8. Equivalent Circuit Diagrams of the Analog Section During Segment 4 of the Timing Cycle3-131C1BUFFERR1INTEGRATOR COMPARATOR VX + +STARTENDTIME123456 SEGMENTVNUMBERXTYPICAL POSITIVE INPUT VOLTAGEVXTYPICAL NEGATIVE INPUT VOLTAGE3-1/2 DIGIT A/D CONVERTERSTC14433TC14433AFigure 9. Alternate

39、 Oscillator CircuitsSegment 3 This segment of the conversion cycle is the same as Segment 1.Segment 4 Segment 4 is an up-going ramp cycle with the unknown input voltage (VX) as the input to the integrator. Figure 8 shows the equivalent configuration of the analog section of the TC14433. The actual c

40、onfiguration of the analog section is dependent upon the polarity of the input voltage during the previous conversion cycle.Segment 5 This segment is a down-going rampperiod with the reference voltage as the input to the integra- tor. Segment 5 of the conversion cycle has a time equal to the number

41、of counts stored in the offset storage latches during Segment 2. As a result, the system zeros automati- cally.Segment 6 This is an extension of Segment 5. The time period for this portion is 4000 clock periods. The results of the A/D conversion cycle are determined in this portion of the conversion

42、 cycle.Figure 10. 3-1/2 Digit Voltmeter Common-Anode Displays, Flashing OverrangeTELCOM SEMICONDUCTOR, INC.3-132TC0420K+5V1230.1 mF5V300k+5V+5V+5V0.1mF0.10.1 mFRCSEGMENTRESISTORS11 10 2 12 24116150 W (7)Vx 3234971012221061121311512420512413 5TC144334543B 13314 6135V142150.1 mF*151 1413 16798 6 7814

43、5V5VMINUS SIGN0.1 mF15 19 18 17 16f g e d c b a5V200W5VMPS-A12 PLUS SIGN 65V5151k110W D S Q3 C R Q 2COMMONANODE LED4 8+5VDISPLAY14013B9 D S Q 13 11 C R Q 1250 mF0.1 mF7 1014MPS-A12(4)DS 45V+5V5V DS 3*R 1 = 470kW FOR 2V RANGEDS 2R 1 = 27kW FOR 200mV RANGEDS 1*MYLAR CAPACITORR1*(A) Crystal Oscillator

44、Circuit(B) LC Oscillator Circuit10 CLK110 CLK118MLCC1TC14433TC1443311 CLK011 CLK047kCCf = 1 =2/LC22 p10 pF C1 AND C2 200 pFFOR L = 5 mH AND C = 0.01 mF, f 32 kHz3-1/2 DIGIT A/D CONVERTERSTC14433 TC14433A 3Figure 11.3-1/2 Digit Voltmeter with LCD DisplayFigure 12. Digit Select Timing DiagramTELCOM SE

45、MICONDUCTOR, INC.3-133 16 00 CLOCK CYCLESEOC 1/2 CLOCK CYCLEBE WEEN EOC PULSESDS118 CLOCK CYCLES 1/2 DIGIT(MSD)2 CLOCKDS2CYCLESDS3DS4 (LSD)0.1 mF470k 0.1 mFC 14024BVRC01 C02 R1R1/C 1C1+V VxDS4DS3VAG DS227kDS1TC14433Q0Q1TC0420kVREFQ2Q3 VDD VSS VEE EOC DU RCRC14070B 1/4+V V300k+V14013B14070B1/4 DQ1/2

46、DIGITC RR Q14013BPLUS DQSIGNBI D C B A Ph LDBI D C B A Ph LD+V BI D C B A Ph LDC RR Q+V+V+VV 1/4 14070B14543BV14543BV14543BMINUSg f e d c b ag f e d c b ag f e d c b aV SIGN+V3-1/2 DIGIT A/D CONVERTERSTC14433TC14433AAPPLICATIONS INFORMATIONFigure 10 is an example of a 3-1/2 digit voltmeter using the

47、 TC14433 with common-anode displays. This system requires a 2.5V reference. Full-scale may be adjusted to 1.999V or 199.9 mV. Input overrange is indicated by flashing a display. This display uses LEDs with common anode digit lines. Power supply for this system is shown as a dual 5V supply; however,

48、the TC14433 will operate over a wide voltage range (see recommended operating conditions, page 2).The circuit in Figure 11 shows a 3-1/2 digit LCD voltme- ter. The 14024B provides the low frequency square wave signal drive to the LCD backplane. Dual power supplies are shown here; however, one supply

49、 may be used when VSS is connected to VEE. In this case, VAG must be at least 2.8V above VEE.When only segments b and c of the decoder are con- nected to the 1/2 digit of the display, 4, 0, 7 and 3 appear as 1. The overrange indication (Q3 = 0 and Q0 = 1) occurs when the count is greater than 1999; e.g., 1.999V for a reference of 2V. The underrange indication, useful for auto- rangi