VHDL程序設(shè)計(jì)題

1、vhdl程序設(shè)計(jì)題四、 編程題（共50分）1、請(qǐng)補(bǔ)全以下二選一vhdl程序（本題10分）entity mux isport(d0,d1,sel:in bit;q:out bit ); (2)end mux;architecture connect of mux is (4) signal tmp1, tmp2 ,tmp3:bit; (6)begin cale:block begin tmp1=d0 and sel; tmp2=d1 and (not sel) tmp3= tmp1 and tmp2;q = tmp3; (8) end block cale; end connect ; (10)

2、2、編寫一個(gè)2輸入與門的vhdl程序，請(qǐng)寫出庫、程序包、實(shí)體、構(gòu)造體相關(guān)語句，將端口定義為標(biāo)準(zhǔn)邏輯型數(shù)據(jù)結(jié)構(gòu)（本題10分）&abylibrary ieee; use ieee.std_logic_1164.all; （2） entity nand2 is port (a，b:in std_logic; （4） y:out std_logic); （6） end nand2; architecture nand2_1 of nand2 is （8） begin y = a nand b; -與y =not( a and b);等價(jià) （10） end nand2_1;3、根據(jù)下表填寫完成一個(gè)3-8

3、線譯碼器的vhdl程序（16分）。library ieee;use ieee.std_logic_1164.all;entity decoder_3_to_8 is port (a,b,c,g1,g2a,g2b:in std_logic; y:out std_logic_vector(7 downto 0); （2）end decoder_3_to_8;architecture rtl of decoder_3_to_8 is signal indata:std_logic_vector (2 downto 0);（4）begin indata y y y y y y y y y = xxxx

4、xxxx; end case; else y = 11111111;（14） end if; end process;（16）end rtl; 4、三態(tài)門電原理圖如右圖所示，真值表如左圖所示，請(qǐng)完成其vhdl程序構(gòu)造體部分。（本題14分）library ieee; use ieee.std_logic_1164.all;entity tri_gate isport(din,en:in std_logic; dout : out std_logic);end tri_gate ;architecture zas of tri_gate isbegin process (din,en) begin

5、if (en=1) then dout = din;else dout = z; end if; end process ;end zas ;四、 編程題（共50分）1、根據(jù)一下四選一程序的結(jié)構(gòu)體部分，完成實(shí)體程序部分（本題8分）entity mux4 is port( (2)s:in std_logic_vector(1 downto 0); (4)d:in std_logic_vector(3 downto 0); (6)y:out std_logic (8); end mux4; architecture behave of mux4 isbeginprocess(s)beginif (

6、s=00) theny=d(0); elsif (s=01) theny=d(1); elsif (s=10) theny=d(2); elsif (s=11) theny=d(3); elsenull; end if;end process;end behave; 2、編寫一個(gè)數(shù)值比較器vhdl程序的進(jìn)程（不必寫整個(gè)結(jié)構(gòu)框架），要求使能信號(hào)g低電平時(shí)比較器開始工作，輸入信號(hào)p = q，輸出equ為0，否則為1。（本題10分）process(p,q)(2)beginif g=0 then(4)if p = q thenequ = 0; (6)else equ = 1; (8)end if;el

7、se equ = 1; (10)end if;end process;3、填寫完成一個(gè)8-3線編碼器的vhdl程序（16分）。library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity eight_tri is port(b:in std_logic_vector(7 downto 0); （2）en:in std_logic;y:outstd_logic_vector(2 downto 0) （4）);end eight_tri;arc

8、hitecture a of eight_tri is （6）signal sel: std_logic_vector(8 downto 0);beginsel=en & b; （8）y= “000” when (sel=”100000001”)else“001” when (sel=”100000010”)else （10）“010” when (sel=”100000100”)else“011” when (sel=”100001000”)else“100” when (sel=”100010000”)else （12） “101” when (sel=”100100000”)else“1

9、10” when (sel=”101000000”)else （14）“111” when (sel=”110000000”)else （16）“zzz”;end a;4、圖中給出了4位逐位進(jìn)位全加器，請(qǐng)完成其vhdl程序。（本題16分）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity full_add isport (a,b: instd_logic_vector (3 downto 0); （2）carr: inout st

10、d_logic_vector (4 downto 0);sum: outstd_logic_vector (3 downto 0);end full_add;architecture full_add_arch of full_add iscomponent adder （4）port (a,b,c:instd_logic;carr: inoutstd_logic;sum: out std_logic （6）);end component;begincarr(0)=0;u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0);u1:adder por

11、t map(a(1),b(1),carr(1),carr(2),sum(1); （8）（10）u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2); （12）u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3); （14）（16）end full_add_arch;四、 編程（共50分）1、完成下圖所示的觸發(fā)器。（本題10分）clrclkdqqnlibrary ieee;use ieee.std_logic_1164.all;entity vposdff is port (clk, clr, d:

12、in std_logic; -2分 q, qn: out std_logic ); -4分end vposdff;architecture vposdff_arch of vposdff isbegin process ( clk, clr ) -6分 begin if clr=1 then q = 0; qn =1; elsif clkevent and clk=1 then q = d; qn = not d; -8分 end if; end process; -10分end vposdff_arch; 2、完成以下4位全加器代碼（本題10分）library ieee;use ieee.s

13、td_logic_1164.all;entity full_add isport (a,b: instd_logic_vector (3 downto 0);cin: instd_logic;cout: out std_logic;sum: outstd_logic_vector (3 downto 0);end full_add;architecture full_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr: outstd_logic;sum: out std_logic);end component;

14、signal c1,c2,c3: std_logic; 2分beginu0:adder port map(a(0),b(0),cin,c1,sum(0); 4分u1:adder port map(a(1),b(1),c1,c2,sum(1); 5分u2:adder port map(a(2),b(2),c2,c3,sum(2); 6分u3:adder port map(a(3),b(3),c3,cout,sum(3); 10分end full_add_arch;3、補(bǔ)充完整如下代碼，使之完成4狀態(tài)不斷循環(huán)。(本題10分)architecture arc of ss istype states

15、is ( st0,st1,st2,st3 ); 2分signal outc: states; 4分beginprocess(clk) begin if reset=1 then outc outc outc outc outc outc =st0; end case; end if;end process;end arc; 4、設(shè)計(jì)異或門邏輯：（本題20分）如下異或門，填寫右邊的真值表。（此項(xiàng)5分）aby000011101110其表達(dá)式可以表示為：（此項(xiàng)5分） 這一關(guān)系圖示如下：試編寫完整的vhdl代碼實(shí)現(xiàn)以上邏輯?？梢圆捎萌魏蚊枋龇?。（此項(xiàng)10分）library ieee;use ieee.

16、std_logic_1164.all; 1分entity yihuo1 isport(a,b:in std_logic;y:out std_logic);end yihuo1; 4分architecture yihuo1_behavior of yihuo1 isbegin 7分process(a,b) y=a xor b;begin （第2種寫法）if a=b theny=0;elsey=1;end if;end process; end yihuo1_behavior; 10分四、 編程（共50分，除特殊聲明，實(shí)體可只寫出port語句，結(jié)構(gòu)體要寫完整）1、用if語句編寫一個(gè)二選一電路，要求

17、輸入a、b, sel為選擇端，輸出q。（本題10分）entity sel2 isport (a,b : in std_logic;sel : in std_logic;q : out std_logic);end sel2;(3)architecture a of sel2 isbeginif sel = 0 thenq = a;(6)elseq = b;(9)end if;end a;(10)2、編寫一個(gè)4位加法計(jì)數(shù)器vhdl程序的進(jìn)程（不必寫整個(gè)結(jié)構(gòu)框架），要求復(fù)位信號(hào)reset低電平時(shí)計(jì)數(shù)器清零，變高后，在上升沿開始工作；輸入時(shí)鐘信號(hào)為clk，輸出為q。（本題10分）process(re

18、set,clk)(2)beginif reset = 0 thenq = “0000”;(4)elsif clkevent and clk = 1 then(6)q = q + 1;(9)end if;end process;(10)3、填寫完成一個(gè)8-3線編碼器的真值表（5分），并寫出其vhdl程序（10分）。8 -3線編碼器真值表enby0y1y21000000000001000000100011000001000101000010000111000100001001001000001011010000001101100000001110xxxxxxxx高阻態(tài)entity eight_tr

19、i is port(b:in std_logic_vector(7 downto 0);en:in std_logic;y:outstd_logic_vector(2 downto 0);end eight_tri;(3)architecture a of eight_tri is signal sel: std_logic_vector(8 downto 0);(4)beginsel=en & b;y= “000” when (sel=”100000001”)else“001” when (sel=”100000010”)else“010” when (sel=”100000100”)els

20、e“011” when (sel=”100001000”)else“100” when (sel=”100010000”)else“101” when (sel=”100100000”)else“110” when (sel=”101000000”)else“111” when (sel=”110000000”)else(9)“zzz”;(10)end a;4、根據(jù)已給出的全加器的vhdl程序，試寫出一個(gè)4位逐位進(jìn)位全加器的vhdl程序。（本題15分）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;us

21、e ieee.std_logic_unsigned.all;entity adder isport (a,b,c:in std_logic;carr: inout std_logic;sum: out std_logic);end adder;architecture adder_arch of adder isbeginsum = a xor b xor c;carr = (a and b) or (b and c) or (a and c);end adder_arch;entity full_add isport (a,b: instd_logic_vector (3 downto 0)

22、;carr: inout std_logic_vector (4 downto 0);sum: outstd_logic_vector (3 downto 0);end full_add;(5)architecture full_add_arch of full_add iscomponent adderport (a,b,c:instd_logic;carr: inoutstd_logic;sum: out std_logic);end component;(10)begincarr(0)=0;u0:adder port map(a(0),b(0),carr(0),carr(1),sum(0

23、);u1:adder port map(a(1),b(1),carr(1),carr(2),sum(1);u2:adder port map(a(2),b(2),carr(2),carr(3),sum(2);u3:adder port map(a(3),b(3),carr(3),carr(4),sum(3);end full_add_arch;(15)四、 編程（共50分，除特殊聲明，實(shí)體可只寫出port語句，結(jié)構(gòu)體要寫完整）1、用if語句編寫一個(gè)四選一電路，要求輸入d0d3, s為選擇端，輸出y。（本題10分）entity mux4 is port(s:in std_logic_vector

24、(1 downto 0);d:in std_logic_vector(3 downto 0);y:out std_logic);end mux4; (3)architecture behave of mux4 isbeginprocess(s)beginif (s=00) theny=d(0); (4)elsif (s=01) theny=d(1); (5)elsif (s=10) theny=d(2); (6)elsif (s=11) theny=d(3); (7)elsenull; (9)end if;end process;end behave; (10)2、編寫一個(gè)數(shù)值比較器vhdl程

25、序的進(jìn)程（不必寫整個(gè)結(jié)構(gòu)框架），要求使能信號(hào)g低電平時(shí)比較器開始工作，輸入信號(hào)p = q，輸出equ為0，否則為1。（本題10分）process(p,q)(2)beginif g=0 then(4)if p = q thenequ_tmp = 0;(6)else equ_tmp = 1;(8)end if;else equ_tmp = 1;(10)end if;end process;3、填寫完成一個(gè)3-8線譯碼器的真值表（5分），并寫出其vhdl程序（10分）。3-8譯碼器的真值表ena2a1a0y10000000000110010000001010100000010010110000100

26、01100000100001101001000001110010000001111100000000xxx00000000entity tri_eight is port(a:in std_logic_vector (2 downto 0);en:in std_logic;y:outstd_logic_vector (7 downto 0);end tri_eight;(2)architecture a of tri_eight is signal sel:std_logic_vector (3 downto 0);(4)beginsel(0) = a(0);sel(1) = a(1);sel(2) = a(2);sel(3) = en;(5)with sel selecty = 00000001 whe