姜書艷數(shù)字邏輯設(shè)計(jì)及應(yīng)用11

1、1 1chapter 4 combinational logic chapter 4 combinational logic design principlesdesign principles( (組合邏輯設(shè)計(jì)原理組合邏輯設(shè)計(jì)原理) ) basic logic algebra (邏輯代數(shù)基礎(chǔ)邏輯代數(shù)基礎(chǔ)) combinational-circuit analysis (組合電路分析組合電路分析) combinational-circuit synthesis (組合電路綜合組合電路綜合)digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯

2、設(shè)計(jì)及應(yīng)用) )2 2review of switching algebrareview of switching algebra ( (開關(guān)代數(shù)內(nèi)容回顧開關(guān)代數(shù)內(nèi)容回顧) )補(bǔ)充：補(bǔ)充：同或同或(xnor)、異或（異或（xor)a0 a1 an = 1 1的個(gè)數(shù)是奇數(shù)的個(gè)數(shù)是奇數(shù)(odd number)0 1的個(gè)數(shù)是偶數(shù)的個(gè)數(shù)是偶數(shù)(even number)a0 a1 an = 1 0的個(gè)數(shù)是偶數(shù)的個(gè)數(shù)是偶數(shù)0 0的個(gè)數(shù)是奇數(shù)的個(gè)數(shù)是奇數(shù)digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )3 3review of swit

3、ching algebrareview of switching algebra ( (開關(guān)代數(shù)內(nèi)容回顧開關(guān)代數(shù)內(nèi)容回顧) )補(bǔ)充：補(bǔ)充：同或同或、異或異或aby =aby=1abyabydigital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )4 4formula minimization(formula minimization(公式法化簡(jiǎn)公式法化簡(jiǎn)) )并項(xiàng)法：并項(xiàng)法： 利用利用 ab+ab=a(b+b)=a吸收法：吸收法： 利用利用 a+ab=a(1+b)=a消項(xiàng)法：消項(xiàng)法： 利用利用 ab+ac+bc = ab+ac消因

4、子法：利用消因子法：利用 a+ab = a+b配項(xiàng)法：配項(xiàng)法： 利用利用 a+a=a a+a=1digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )5 54.2 combinational-circuit analysis4.2 combinational-circuit analysis ( (組合電路分析組合電路分析) )get the logic expression or truth table from logic circuit (由邏輯電路圖得出邏輯表達(dá)式或真值表由邏輯電路圖得出邏輯表達(dá)式或真值表)digita

5、l logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )6 6exhausting way (exhausting way (窮舉法窮舉法) )（圖（圖410）將全部輸入組合加到輸入端；將全部輸入組合加到輸入端；根據(jù)基本邏輯關(guān)系，從輸入端到輸出端，根據(jù)基本邏輯關(guān)系，從輸入端到輸出端，寫出每一級(jí)門的輸出；寫出每一級(jí)門的輸出；根據(jù)最后輸出結(jié)果列出真值表；根據(jù)最后輸出結(jié)果列出真值表；digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )7 7algebra way (algebr

6、a way (代數(shù)法代數(shù)法) )（圖（圖411，12，13，14，15，16，17）從輸入端到輸出端，逐級(jí)寫出每一級(jí)門的從輸入端到輸出端，逐級(jí)寫出每一級(jí)門的輸出邏輯式；輸出邏輯式；及時(shí)利用基本定理對(duì)邏輯式化簡(jiǎn)；及時(shí)利用基本定理對(duì)邏輯式化簡(jiǎn)；由最后輸出端得到輸出函數(shù)式；由最后輸出端得到輸出函數(shù)式；digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )8 8minimize logic function minimize logic function ( (化簡(jiǎn)邏輯函數(shù)化簡(jiǎn)邏輯函數(shù)) )什么是最簡(jiǎn)什么是最簡(jiǎn) 項(xiàng)數(shù)最少項(xiàng)數(shù)最少 每項(xiàng)

7、中的變量數(shù)最少每項(xiàng)中的變量數(shù)最少公式法化簡(jiǎn)公式法化簡(jiǎn)卡諾圖化簡(jiǎn)卡諾圖化簡(jiǎn) 卡諾圖表示邏輯函數(shù)卡諾圖表示邏輯函數(shù) 卡諾圖的特點(diǎn)卡諾圖的特點(diǎn) 合并最小項(xiàng)（化簡(jiǎn)）合并最小項(xiàng)（化簡(jiǎn)）digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )9 9karnaugh maps(karnaugh maps(卡諾圖表示邏輯函數(shù)卡諾圖表示邏輯函數(shù)) ) 真值表的圖形表示真值表的圖形表示digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1010karnaugh maps(karn

8、augh maps(卡諾圖表示邏輯函數(shù)卡諾圖表示邏輯函數(shù)) )digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )the coordinates are ordered in gray codes;each cell differs from its neighbors in only one variable!11 11karnaugh maps(karnaugh maps(卡諾圖表示邏輯函數(shù)卡諾圖表示邏輯函數(shù)) )yx0 101m0m2m1m3m0m2m6m4m1m3m7m5 真值表的圖形表示真值表的圖形表示zxy00

9、01 11 1001yzwx00000111100111100412151393715261410811digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1212karnaugh maps(karnaugh maps(卡諾圖表示邏輯函數(shù)卡諾圖表示邏輯函數(shù)) )0 0 0 10 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 0a b cff = (a,b,c)(0,3,5,6)10100101cab00 01 11 1001例：填寫下面兩個(gè)函數(shù)的卡諾圖例：填寫下面兩個(gè)函數(shù)的卡諾圖

10、 f1 = (a,b,c) (1,3,5,7) f2(a,b,c) = ac+bcd+bdigital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1313卡諾圖的特點(diǎn)卡諾圖的特點(diǎn)邏輯相鄰性：邏輯相鄰性：相鄰兩方格只有一個(gè)因子互為反變量相鄰兩方格只有一個(gè)因子互為反變量合并最小項(xiàng)合并最小項(xiàng)兩個(gè)最小項(xiàng)相鄰可消去一個(gè)因子兩個(gè)最小項(xiàng)相鄰可消去一個(gè)因子四個(gè)最小項(xiàng)相鄰可消去兩個(gè)因子四個(gè)最小項(xiàng)相鄰可消去兩個(gè)因子八個(gè)最小項(xiàng)相鄰可消去三個(gè)因子八個(gè)最小項(xiàng)相鄰可消去三個(gè)因子2n個(gè)最小項(xiàng)相鄰可消去個(gè)最小項(xiàng)相鄰可消去n個(gè)因子個(gè)因子digital logic

11、design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1414兩個(gè)最小項(xiàng)相鄰兩個(gè)最小項(xiàng)相鄰 可消去一個(gè)因子可消去一個(gè)因子111111zxy00 01 11 1001yzwx000001111001111011111111xyz+ xyz = xy xyz + xyz = yz digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1515abcd00 01 11 100001111011111111111111abcd+abcd+abcd+abcd= abd + abd = bd四個(gè)最小

12、項(xiàng)相鄰四個(gè)最小項(xiàng)相鄰 可消去二個(gè)因子可消去二個(gè)因子zxy00 01 11 10011 1 1 11 1 1 1digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1616abcd00 01 11 10000111101111111111110000ad八個(gè)最小項(xiàng)相鄰八個(gè)最小項(xiàng)相鄰 可消去三個(gè)因子可消去三個(gè)因子f1 = abc+abd+acd+cd+abc+acddigital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1717karnaugh maps mini

13、mizationkarnaugh maps minimization( (卡諾圖化簡(jiǎn)卡諾圖化簡(jiǎn)) )化簡(jiǎn)函數(shù)：化簡(jiǎn)函數(shù)：f2 = (a,b,c,d) ( 0, 2, 3, 5, 7, 8, 10, 11, 13)abcd00 01 11 1000011110abdbcdbcbd1111111111 1、填圖、填圖2 2、圈組、圈組3 3、讀圖，得到結(jié)果、讀圖，得到結(jié)果f2 = abd+bcd+bc+bddigital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1818卡諾圖化簡(jiǎn)步驟卡諾圖化簡(jiǎn)步驟填寫卡諾圖填寫卡諾圖可以先將函數(shù)化為

14、最小項(xiàng)之和的形式可以先將函數(shù)化為最小項(xiàng)之和的形式圈組：找出可以合并的最小項(xiàng)圈組：找出可以合并的最小項(xiàng)組組(圈圈)數(shù)最少、每組數(shù)最少、每組(圈圈)包含的方塊數(shù)最多包含的方塊數(shù)最多方格可重復(fù)使用，但至少有一個(gè)未被其它組圈過方格可重復(fù)使用，但至少有一個(gè)未被其它組圈過讀圖：寫出化簡(jiǎn)后的乘積項(xiàng)讀圖：寫出化簡(jiǎn)后的乘積項(xiàng)消掉既能為消掉既能為0也能為也能為1的變量的變量保留始終為保留始終為0或或1的變量的變量乘積項(xiàng)：乘積項(xiàng)：0 反變量反變量1 原變量原變量digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )1919圈組原則圈組原則圈圈1，得

15、化簡(jiǎn)，得化簡(jiǎn)“與或式與或式”所有的所有的1必須必須圈定圈定圈圈0，得化簡(jiǎn)，得化簡(jiǎn)“或與式或與式”所有的所有的0必須必須圈定圈定每個(gè)圈中每個(gè)圈中0或或1的個(gè)數(shù)為的個(gè)數(shù)為 2i 個(gè)個(gè) a. 首先，保證圈組數(shù)最少首先，保證圈組數(shù)最少 b. 其次，圈組范圍盡量大其次，圈組范圍盡量大 c. 每個(gè)圈組至少要有一個(gè)每個(gè)圈組至少要有一個(gè)1或或0未被其他組未被其他組圈過圈過digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )2020圈組步驟圈組步驟先圈孤立的先圈孤立的1格（格（0格）格）再圈只能按一個(gè)方向合并的分組圈子再圈只能按一個(gè)方向合并的

16、分組圈子盡量大盡量大其余可任意方向合并其余可任意方向合并將每個(gè)圈組寫成與項(xiàng)（或項(xiàng)），再進(jìn)行邏將每個(gè)圈組寫成與項(xiàng)（或項(xiàng)），再進(jìn)行邏輯加（乘）輯加（乘）digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )2121卡諾圖法化簡(jiǎn)卡諾圖法化簡(jiǎn)舉例舉例f1 = (a,b,c,d) ( 0, 3, 4, 5, 6, 7, 9, 12, 14, 15)f2 = (a,b,c,d) ( 1, 5, 6, 7, 11, 12, 13, 15)f3 = (a,b,c,d) ( 0, 1, 3, 4, 5, 7)f4 = (a,b,c,d) ( 1

17、, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14)digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )222222k-maps for variablesk-maps for variables5 and 6 variable maps existbut hard to use two-variable maps existbut not very useful easy to do algebraically by hand0 101fzy2323several concepts (several co

18、ncepts (幾幾 個(gè)個(gè) 概概 念念) ) a logic function p(x1,xn) implies a logic function f(x1,xn) if for every input combination such that p=1,then f=1 also. (對(duì)于邏輯函數(shù)對(duì)于邏輯函數(shù) p(x1,xn) 和和 f(x1,xn) ，若，若對(duì)任何使對(duì)任何使p=1的輸入組合，也能使的輸入組合，也能使f為為1，則稱，則稱p隱含隱含f，或者，或者f包含包含p。)p1(a,b,c) = abcf(a,b,c) = ab + bcp2(a,b,c) = bcp = a,b,c (1

19、,3,6)f = a,b,c (1,3,5,6,7)digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )2424several concepts (several concepts (幾幾 個(gè)個(gè) 概概 念念) ) a prime implicant of a logic function f(x1,xn) is a product term p(x1,xn) that inplies f, such that if any variable is removed from p, then the resulting prod

20、uct term does not imply f. (邏輯函數(shù)邏輯函數(shù) f(x1,xn) 的的主蘊(yùn)含項(xiàng)主蘊(yùn)含項(xiàng) 是隱含是隱含 f 的乘積的乘積項(xiàng)項(xiàng) p(x1,xn) ，如果從，如果從 p 中移去任何變量，則所得的中移去任何變量，則所得的乘積項(xiàng)不隱含乘積項(xiàng)不隱含f。)f(a,b,c) = abc + bc + ac = bc + ac主蘊(yùn)含項(xiàng)定理：最小和是主蘊(yùn)含項(xiàng)之和主蘊(yùn)含項(xiàng)定理：最小和是主蘊(yùn)含項(xiàng)之和digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )2525several concepts (several concept

21、s (幾幾 個(gè)個(gè) 概概 念念) )蘊(yùn)含項(xiàng)（蘊(yùn)含項(xiàng)（implicant） ：只包含：只包含1的一個(gè)矩的一個(gè)矩形圈；形圈；主蘊(yùn)含項(xiàng)（主蘊(yùn)含項(xiàng)（prime implicant） ：擴(kuò)展到最：擴(kuò)展到最大的蘊(yùn)含項(xiàng)；大的蘊(yùn)含項(xiàng)；digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )2626several concepts (several concepts (幾幾 個(gè)個(gè) 概概 念念) )distinguished 1-cell ( (奇異奇異“ “ 1 ”1 ”單元單元) )an input combination that is cov

22、ered by only one prime inplicant (僅被單一主蘊(yùn)含項(xiàng)覆蓋的僅被單一主蘊(yùn)含項(xiàng)覆蓋的輸入組合輸入組合)沒有可能被重復(fù)沒有可能被重復(fù)“圈圈”過的過的1 1單元單元abcd00 01 11 10000111101111111111digital logic design and application ( (數(shù)字邏輯設(shè)計(jì)及應(yīng)用數(shù)字邏輯設(shè)計(jì)及應(yīng)用) )2727several concepts (several concepts (幾幾 個(gè)個(gè) 概概 念念) )essential prime implicant (質(zhì)主蘊(yùn)含項(xiàng)質(zhì)主蘊(yùn)含項(xiàng))a prime implicant that covers one or more distingui