verilog語法練習(xí)

1、1,八位數(shù)據(jù)通路控制器define ON 1b1define OFF 1b0wire controlswitch;wire 7:0 in out;assign out = (controlswitch = ON) ? in : 8h00;2,數(shù)據(jù)在寄存器中的暫時(shí)保存module reg8(en ,clk, data,rst,out);input en,clk,rst;input 7:0 data;output 7:0 out;reg 7:0 out;always (posedge clk)begin if(!rst) out <= b0; else if (en) out <= d

2、ata; else out <= 8h00;endendmodule3,狀態(tài)機(jī)module fsm(clk,rst,a,k1,k2);input clk,rst,a;output k1,k2;reg k1,k2;reg state;parameteter Idle = 2b00, Start = 2b01, Stop = 2b10, Clear = 2b11;always (posedge clk)begin if (!rst) begin state <= Idle; k2 <= 0; k1 <= 0; endelsecase (state) Idle: begin

3、If(a) begin state <= Start; k1 <= 0; end else state <= Idle; end Start : begin If(!a) state <= Stop; else state <= Start; end Stop ：begin If (a) Begin state <= Clear; k2 <= 1; end else state <= Stop; endClear : begin If (!a) begin state <= Idle; k2 <= 0; k1 <= 1; end

4、 else state <= Clear; endendcaseendmodule 4,組合邏輯電路設(shè)計(jì)實(shí)例8位帶進(jìn)位端的加法器的設(shè)計(jì)實(shí)例module adder_8 (cout, sum, a,b,cin);output 7:0 sum;output cout;input 7:0 a;input 7:0 b;input cin;assign cout,sum = a+b+cin;endmodule5,指令譯碼電路的設(shè)計(jì)實(shí)現(xiàn)（利用電平敏感的always快來設(shè)計(jì)組合邏輯）。/操做碼的宏定義define plus 3d0define minus 3d1define band 3d2defin

5、e bor 3d3define unegate 3d4module alu (out, opcode,a,b);output 7:0 out;input 2:0 opcode;input 7:0 a,b;reg 7:0 out;always (opcode or a or b)begin case(opcode) /算術(shù)運(yùn)算 plus : out = a+b; minus : out = a-b;/位運(yùn)算 band : out =a&b; bor ： out =a|b;/單目運(yùn)算 unegate out=a;default: out= 8hx;endcaseendendmodule6,

6、利用task和電平敏感的always塊設(shè)計(jì)比較后重組信號(hào)的組合邏輯module sort4(ra,rb,rc,rd,a,b,c,d);parameter t = 3;output t:0 ra,rb,rc,rd;input t:0 a,b,c,d;reg t:0 ra,rb,rc,rd;always (a or b or c or d)/用電平敏感的always塊描述組合邏輯begin reg t:0 va,vb,vc,vd;va,vb,vc,cd=a,b,c,d;sort2(va,vc);sort2(vb,vd);sort2(va,vb);sort2(vc,vd);sort2(vb,vc);

7、ra,rb,rc.rd=va,vb,vc,vd;endtask sort2;. inout t:0 x,y; reg t:0 temp;if (x>y) begin tmp = x; x = y; y = tmp; endendtaskendmodule7,比較器的設(shè)計(jì)實(shí)例（利用賦值語句設(shè)計(jì)組合邏輯電路）module compare (equal,a,b);output equal;input a,b;assign equal = (a=b)?1:0;endmodule8,3-8譯碼器設(shè)計(jì)實(shí)例（利用賦值語句設(shè)計(jì)組合邏輯）module decoder(out,in);output 7:0

8、out;input 2:0 in; assign out = 1b1<<in;/*把最低位的1左移in（根據(jù)從in端口輸入的值）位，并賦予out*/endmodule9,8-3編碼器的設(shè)計(jì)實(shí)例module encoder1(none_on,out,in); output none_on; output 2:0 out; input 7:0 in; reg 2:0 out; reg none_on; always (in) begin : local integer i; out = 0; none_on = 1;/* returns the value of the highest

9、 bit number turned on*/for (i= 0; i<8; i=i+1) begin if(ini) begin out = i; none_on = 0; endendendendmodule編碼器設(shè)計(jì)方案之二：module encoder2 (none_on,out2,out1,out0,h,g,f,e,d,c,b,a);output none_on,out2,out1,out0;wire 3:0 outvec;assign outvec = h?4b0111:g?4b0110:f?4b0101:e?4b0100:d?4b0011:c?4b0010:b?4b0001

10、:a?4b0000:4b1000;assign none_on = outvec3;assign out2 = outvec2;assign out1 = outvec1;assign out0 = outvec0;endmodule編碼器設(shè)計(jì)方案之三10，多路器的設(shè)計(jì)實(shí)例多路器設(shè)計(jì)方案之一：module emux1(out, a,b,sel); output out; input a,b,sel; assign out = sel?a:b;endmodule 多路器設(shè)計(jì)方案之二： module mux2(out,a,b,sel); output out; input a,b,sel; reg

11、 out;/用電平觸發(fā)的always塊來設(shè)計(jì)多路器的組合邏輯always (a or b or sel)begin/*檢測(cè)輸入信號(hào)sel的值*/case(sel) 1b1:out = a; 1b0:out = b;default : out = bx;endcaseendendmodule三態(tài)輸出驅(qū)動(dòng)器設(shè)計(jì)方案一module trist1(out,in,enable);output out;input in,enable;assign out = enable? In:bz;endmodule三態(tài)輸出驅(qū)動(dòng)器設(shè)計(jì)方案二module trist2(out, in, enable); output

12、out;input in, enable;/ bufif1是一個(gè)Verilog門級(jí)原語（primitive）bufif1 mytrist2(out,in,enable);endmodule 時(shí)序邏輯設(shè)計(jì)實(shí)例觸發(fā)器設(shè)計(jì)實(shí)例module dff(q,data,clk); output q; input data,clk; reg q; always (posedge clk) begin q<= data; endendmodule電平敏感型鎖存器設(shè)計(jì)實(shí)例一module latch1(q,data,clk); output q; input data,clk; assign q=clk?da

13、ta:q;endmodule帶復(fù)位和置位端的電平敏感型鎖存器設(shè)計(jì)實(shí)例二module latch2(q,data,clk,set,reset); output q; input data, clk, set, reset; assign q = reset?0:(set?1:(clk?data:q);endmodule電平敏感型鎖存器設(shè)計(jì)實(shí)例三module latch3(q,data,clk); output q; input data,clk; reg q; always (clk or data) begin if(clk) q=data; endendmodule 移位寄存器設(shè)計(jì)實(shí)例mod

14、ule shifter (din, clk, clr, dout);input din, clk, clr;output 7:0 dout;reg 7:0 dout;always (posedge clk)beginif(clr) dout <= 8b0;else begin dout <= dout<<1; dout0 <= din; endendendmoduleverilog-2001 generate1,一個(gè)參數(shù)化的 gray-code to binary-code 轉(zhuǎn)換器；這里采用復(fù)制產(chǎn)生多個(gè)assign語句的形式來實(shí)現(xiàn)；module gray2bin1

15、(bin,gray);parameter SIZE =8; /this module is parameterizableoutput SIZE-1:0 bin;input SIZE-1:0 gray;genvar i;generate for(i=0;i<SIZE; i=i+1) begin:bit assign bini = graySIZE-1:i; endendgenerateendmodule等同于下面的語句：assign bin 0 = graySIZE-1:0;assign bin 1 = graySIZE-1:1;assign bin 2 = graySIZE-1:2;

16、assign bin 7 = graySIZE-1:7;2,采用always語句的形式來實(shí)現(xiàn)module gray2bin1(bin,gray);parameter SIZE =8; /this module is parameterizableoutput SIZE-1:0 bin;input SIZE-1:0 gray;genvar i;generate for(i=0;i<SIZE; i=i+1) begin:bit always (graySIZE-1:i) /fixed part select assign bini = graySIZE-1:i; endendgenerate

17、endmodule產(chǎn)生時(shí)鐘信號(hào)module gen_clk (clk,reset);output clk;output reset;reg clk;reg reset;initialbegin reset = 1; clk = 0; #3 reset = 0; #5 reset = 1;endalways #5 clk = clk;endmodule用門級(jí)結(jié)構(gòu)來描述D觸發(fā)器module flop(data, clock, clear, q, qb); input data,clock,clear; output q,qb; nand # 10 nd1(a,data,clock,clear),

18、nd2(b,ndata,clock), nd4(d,c,b,clear), nd5(e,c,nclock), nd6(f,d,nclock), nd8(qb,q,f,clear);nand # 9 nd3(c,a,d), nd7(q,e,qb);not #10 iv1(ndata,data), iv2(nclock,clock);endmodule用觸發(fā)器組成帶清零端的4位寄存器include “flop.v”module hardreg(d,clk,clrb,q);input clk,clrb;input 3:0 d;output 3:0 q;flop f1(.data(d0),.clock

19、(clk),.clear(clrb),.q(q0), f2(.data(d1),.clock(clk),.clear(clrb),.q(q3), f3(.data(d2),.clock(clk),.clear(clrb),.q(q2), f4(.data(d3),.clock(clk),.clear(clrb),.q(q3);endmodule用行為描述的方法來描述帶清零端的4位寄存器module hardreg(d,clk,clrb,q);input clk,clrb;input 3:0 d;output 3:0 q;reg 3:0 q;always (posedge clk or pose

20、dge clrb)begin if(clrb) q<=0; else q<=d;endendmodule 分頻電路module divf #( parameter Div_num = 12 , / 分頻數(shù) parameter state=0 /半分頻為0，奇數(shù)分頻為1，偶數(shù)分頻為2) (input clr, input clk, output Div_clk);reg 24:0 count;case(state)1: begin /ji_shu reg pos_clk; reg neg_clk; always(posedge clk or negedge clr) if(!clr)

21、 count<=0; else if(count=0 & pos_clk) count<=Div_num/2-1; else if(count=0) count<=Div_num/2; else count<=count-1; always(posedge clk or negedge clr) if(!clr) pos_clk<=0; else if(count=0) pos_clk<=pos_clk; else pos_clk<=pos_clk; always(negedge clk or negedge clr) if(!clr) neg

22、_clk<=0; else neg_clk<=pos_clk; assign Div_clk = pos_clk & neg_clk; end2: begin /ou_shu reg Div_clk1; always(posedge clk or negedge clr) if(!clr) count<=0; else if(count=0) count<=Div_num/2-1; else count<=count-1; always(posedge clk or negedge clr) if(!clr) Div_clk1<=0; else if(count=0) Div_clk1<=Div_clk1; assign Div_clk = Div_clk1; end 0: begin /ban_fen_pin reg coun