FSK調(diào)制與解調(diào)VHDL程序及仿真

1、.8.10 FSK調(diào)制與解調(diào)VHDL程序及仿真1. FSK調(diào)制VHDL程序-文件名：PL_FSK-功能：基于VHDL硬件描述語(yǔ)言，對(duì)基帶信號(hào)進(jìn)行FSK調(diào)制-最后修改日期：2004.3.16library ieee;use ieee.std_logic_arith.all;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity PL_FSK isport(clk :in std_logic; -系統(tǒng)時(shí)鐘 start :in std_logic; -開(kāi)始調(diào)制信號(hào) x :in std_logic; -基帶信號(hào) y :out

2、 std_logic); -調(diào)制信號(hào)end PL_FSK;architecture behav of PL_FSK issignal q1:integer range 0 to 11; -載波信號(hào)f1的分頻計(jì)數(shù)器signal q2:integer range 0 to 3; -載波信號(hào)f2的分頻計(jì)數(shù)器signal f1,f2:std_logic; -載波信號(hào)f1，f2beginprocess(clk) -此進(jìn)程通過(guò)對(duì)系統(tǒng)時(shí)鐘clk的分頻，得到載波f1beginif clk'event and clk='1' then if start='0' then

3、q1<=0; elsif q1<=5 then f1<='1'q1<=q1+1; -改變q1后面的數(shù)字可以改變，載波f1的占空比 elsif q1=11 then f1<='0'q1<=0; -改變q1后面的數(shù)字可以改變，載波f1的頻率 else f1<='0'q1<=q1+1; end if;end if;end process;process(clk) -此進(jìn)程通過(guò)對(duì)系統(tǒng)時(shí)鐘clk的分頻，得到載波f2beginif clk'event and clk='1' then i

4、f start='0' then q2<=0; elsif q2<=0 then f2<='1'q2<=q2+1; -改變q2后面的數(shù)字可以改變，載波f2的占空比 elsif q2=1 then f2<='0'q2<=0; -改變q2后面的數(shù)字可以改變，載波f2的頻率 else f2<='0'q2<=q2+1; end if;end if;end process;process(clk,x) -此進(jìn)程完成對(duì)基帶信號(hào)的FSK調(diào)制beginif clk'event and clk

5、='1' then if x='0' then y<=f1; -當(dāng)輸入的基帶信號(hào)x=0時(shí)，輸出的調(diào)制信號(hào)y為f1 else y<=f2; -當(dāng)輸入的基帶信號(hào)x=1時(shí)，輸出的調(diào)制信號(hào)y為f2 end if;end if;end process;end behav;2. FSK調(diào)制VHDL程序仿真圖FSK調(diào)制VHDL程序仿真圖如圖8.10.7所示。（a）FSK調(diào)制VHDL程序仿真全圖注：a. 載波f1、f2分別是通過(guò)對(duì)clk的12分頻和2分頻得到的。b.基帶碼長(zhǎng)為載波f1的2個(gè)周期，為載波f2的6個(gè)周期。c.輸出的調(diào)制信號(hào)y在時(shí)間上滯后于載波信號(hào)一個(gè)cl

6、k，滯后于系統(tǒng)時(shí)鐘2個(gè)clk。（b）FSK調(diào)制VHDL程序仿真局部放大圖圖8.10.7 FSK調(diào)制VHDL程序仿真圖 8.10.5 FSK解調(diào)方框圖及電路符號(hào)FSK解調(diào)方框圖如圖8.10.8所示， FSK解調(diào)電路符號(hào)如圖8.10.9所示。說(shuō)明：圖中沒(méi)有包含模擬電路部分，調(diào)制信號(hào)為數(shù)字信號(hào)形式。FPGA clkstart調(diào)制信號(hào)分頻器q寄存器xx計(jì)數(shù)器m判決基帶信號(hào)圖8.10.8 FSK解調(diào)方框圖圖8.10.9 FSK解調(diào)電路符號(hào)8.10.6 FSK解調(diào)VHDL程序及仿真1. FSK解調(diào)VHDL程序-文件名：PL_FSK2-功能：基于VHDL硬件描述語(yǔ)言，對(duì)FSK調(diào)制信號(hào)進(jìn)行解調(diào)-最后修改日期：

7、2004.3.16library ieee;use ieee.std_logic_arith.all;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity PL_FSK2 isport(clk :in std_logic; -系統(tǒng)時(shí)鐘 start :in std_logic; -同步信號(hào) x :in std_logic; -調(diào)制信號(hào) y :out std_logic); -基帶信號(hào)end PL_FSK2;architecture behav of PL_FSK2 issignal q:integer range 0

8、 to 11; -分頻計(jì)數(shù)器signal xx:std_logic; -寄存器 signal m:integer range 0 to 5; -計(jì)數(shù)器beginprocess(clk) -對(duì)系統(tǒng)時(shí)鐘進(jìn)行q分頻beginif clk'event and clk='1' then xx<=x; -在clk信上升沿時(shí)，x信號(hào)對(duì)中間信號(hào)xx賦值 if start='0' then q<=0; -if語(yǔ)句完成Q的循環(huán)計(jì)數(shù) elsif q=11 then q<=0; else q<=q+1; end if;end if;end process

9、;process(xx,q) -此進(jìn)程完成FSK解調(diào)begin if q=11 then m<=0;-m計(jì)數(shù)器清零elsif q=10 then if m<=3 then y<='0' -if語(yǔ)句通過(guò)對(duì)m大小，來(lái)判決y輸出的電平 else y<='1' end if;elsif xx'event and xx='1'then m<=m+1; -計(jì)xx信號(hào)的脈沖個(gè)數(shù)end if;end process;end behav;2.FSK解調(diào)VHDL程序仿真圖及注釋FSK解調(diào)VHDL程序仿真圖及注釋如圖8.10.10所示。（a）FSK解調(diào)VHDL程序仿真全圖注：a.在q=