edA考試卷(帶答案)

1、20082009學(xué)年第一學(xué)期EDA技術(shù)A卷適用：06級(jí)電子信息工程專業(yè)EDA技術(shù)A一、填空題：（共20分，每空1分）1、在VHDL程序設(shè)計(jì)中，常用的庫有（ IEEE庫 ）（ STD ）（ WORK ）庫等。2、Max_plusII為原理圖輸入設(shè)計(jì)配備了各種需要的元件庫，它們分別是（ 基本邏輯元件庫）（ 宏功能元件庫 ）（ 宏功能塊LPM庫 ）。3、采用原理圖輸入設(shè)計(jì)的文件后綴為（ .gdf ），采用波形圖輸入設(shè)計(jì)的文件后綴為（ .wdf ）4、在VHDL中的數(shù)值類屬性測試函數(shù)主要有（left）（ right）（ high ）和LOW。5、FPGA/CPLD的設(shè)計(jì)流程為（ 設(shè)計(jì)輸入 ）、（ 綜合

2、 ）（ 適配 ）（ 時(shí)序仿真與功能仿真 ）（ 編程下載 ）（ 硬件測試 ）。6、 若D<= “11” & 00 & “01”，則D的值為（ “110001” ）。7、 若定義W : BUFFER STD_LOGIC_VECTOR(0 TO 5)，程序中有W<=“100111”；則W(2)的值為（ 0 ）。8、 定義signal f,g:std_logic_vector(5 downto 0); 若f的值為“101011”，若執(zhí)行g(shù)<=(5=>f(1),4=>1, others=>f(4); 則g的值是（ 110000 ）。二、簡答題：（共10

3、分）1、VHDL程序一般包括幾個(gè)組成部分，每部分的作用是什么？答：VHDL程序一般包括3個(gè)組成部分，它們是（1）實(shí)體，它描述的是電路器件的端口構(gòu)成和信號(hào)屬性；（2）結(jié)構(gòu)體，描述設(shè)計(jì)實(shí)體的內(nèi)部結(jié)構(gòu)和外部設(shè)計(jì)實(shí)體端口間的邏輯關(guān)系；（3）庫及程序包的聲明，在設(shè)計(jì)實(shí)體中的語句可以使用庫中相應(yīng)程序包的數(shù)據(jù)和文件。2、什么叫順序語句，它的適用范圍是什么？VHDL有那幾種基本的順序語句？答：執(zhí)行順序與它們的書寫順序基本一致的語句叫順序語句，順序語句只能出現(xiàn)在進(jìn)程和子程序中，子程序包括函數(shù)和過程。Vhdl有六類基本順序語句：賦值語句、流程控制語句、等待語句、子程序調(diào)用語句、返回語句、空操作語句。三、改錯(cuò)，請(qǐng)指

4、出下列描述中的語法錯(cuò)誤并改正（10分）LIBRARY IEEE; -缺分號(hào)USE IEEE.STD_LOGIC_1164.ALL; -缺程序包名ENTITY h_adder IS -實(shí)體名不一致 PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC) ; -分號(hào)放外邊END ENTITY h_adder; ARCHITECTURE fh1 OF h_adder is signal abc : STD_LOGIC_vector(1 downto 0) ; -改成signal 且數(shù)據(jù)寬度不對(duì)BEGIN abc <= a & b ; PRO

5、CESS(abc) Begin -缺begin CASE abc IS WHEN "00" => so<='0' co<='0' ; WHEN "01" => so<='1' co<='0' ; WHEN "10" => so<='1' co<='0' ; -串行數(shù)據(jù)用單引號(hào) WHEN "11" => so<='0' co<='

6、;1' ; -并行數(shù)據(jù)用雙引號(hào)WHEN OTHERS => NULL ;End case; -缺 end case;END PROCESS;END ARCHITECTURE fh1 ; -結(jié)構(gòu)體名不一致四、編程題（60分）1、Use VHDL language to realize the logic function of figure（5分）Library ieee;Use ieee.std_logic_1164.all;Entity MULTI_DFF isPort( CLK,A,D :IN STD_LOGIC; QQ : OUT STD_LOGIC )

7、 END MULTI_DFF ARCHITECTURE bhv OF MULTI_DFF IS SIGNAL Q1,Q2 : STD_LOGIC; BEGINPRO1: PROCESS (CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN Q1 <= NOT (Q2 OR A); END IF; END PROCESS ;PRO2:PROCESS (Q1) BEGIN IF Q1'EVENT AND Q1='1' THEN Q2 <= D; END IF; QQ <= Q2 ;

8、END PROCESS ; 2、用for_loop語句實(shí)現(xiàn)一個(gè)16位的串入并出移位寄存器。（10分）library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;entity chuan_bing is port(load : in std_logic; d_in : in std_logic; d_out:buffer std_logic_vector(15 downto 0); clk :in std_logic);end chuan_bing;ar

9、chitecture arch of chuan_bing issignal l: std_logic_vector(15 downto 0); begin process(clk) begin if(clk'event and clk='1') then l(0)<=d_in; if(load='0') then for i in 14 downto 0 loop l(i+1)<=l(i); end loop; else d_out<=l; end if; end if;end process;end arch;3、用VHDL設(shè)計(jì)2位

10、全減器電路，要求首先設(shè)計(jì)一個(gè)1位全減器，然后用元件例化語句設(shè)計(jì)2位全減器。（15分）一位全減器LIBRary ieee;use ieee.std_logic_1164.all;entity suber isport(a,b,c : in std_logic; dout,sub : out std_logic);end suber;architecture arch of suber issignal s : std_logic_vector(2 downto 0);begins<=c&b&a;process(s)begincase s is when"000&q

11、uot; =>dout<='0'sub<='0' when"001" =>dout<='1'sub<='0'when"010" =>dout<='1'sub<='1'when"011" =>dout<='0'sub<='0'when"100" =>dout<='1'sub<='

12、1'when"101" =>dout<='0'sub<='0'when"110" =>dout<='0'sub<='1'when"111" =>dout<='1'sub<='1'when others=>null;end case;end process;end arch;2位全減器LIBRary ieee;use ieee.std_logic_1164.all;entit

13、y fullsuber isport(x,y : in std_logic_vector(1 downto 0); sin : in std_logic; dout1 : out std_logic_vector(1 downto 0); sub1 : out std_logic);end fullsuber;architecture arch of fullsuber iscomponent suber port(a,b,c : in std_logic; dout,sub : out std_logic);end component;signal e : std_logic;beginu1

14、: suber port map (a=>x(0),b=>y(0),c=>sin,dout=>dout1(0),sub=>e);u2: suber port map (a=>x(1),b=>y(1),c=>e,dout=>dout1(1),sub=>sub1);end arch;4、用VHDL描述一個(gè)具有計(jì)數(shù)使能、異步復(fù)位和計(jì)數(shù)器并行預(yù)置功能的16位加法計(jì)數(shù)器。（15分）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; 輸入輸出ENclr

15、ldCLKQ15.0X0XX0000000000000000X10XP15.0011á保持111非á保持111á自加計(jì)數(shù)entity t74ls161 isport(clr,ld,en,clk : in std_logic;q :out std_logic_vector(15 downto 0); p: in std_logic_vector(15 downto 0);end t74ls161;architecture arch of t74ls161 is signal m : std_logic_vector(15 downto 0);begin proces

16、s(clr,ld,en,clk) begin if(clr='0') thenm<=(others=>0);elsif(ld='0') then m<=p; elsif(clk'event and clk='1') then if (en=1) then m<=m+1; end if; end if;q<=m;end process;end arch;5、下圖為一狀態(tài)機(jī)的狀態(tài)圖，根據(jù)其輸出判斷其類型，并用VHDL描述之（15分）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

17、ENTITY moore ISPORT(clk,ready,rw: IN Std_Logic; oe,we : OUT Std_Logic);END moore;ARCHITECTURE state_machine OF Moore ISTYPE state_type IS (idle,decision,read,write);SIGNAL present_state,next_state: state_type;BEGINstate_comb: PROCESS(present_state,ready,read_write) BEGIN CASE present_state IS WHEN i

18、dle => oe<='0' we<='0' IF(ready='1') THEN next_state<=decision; ELSE next_state<=idle; END IF; WHEN decision => oe<='0' we<='0' IF(rw='1') THEN next_state<=read; ELSE next_state<=write; END IF; WHEN read => oe<='1' we<='0' IF(ready='1') THEN next_state<=idle; ELSE next_state<=read; END IF; WHEN write => oe<