EDA程序設(shè)計試題及答案

1、1?請畫出下段程序的真值表，并說明該電路的功能LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY aaa ISP0RT( oe,dir :IN STD_L0GIC ;a,b : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0 );END aaa;ARCHITECTURE ar OF aaa IS輸入alaO"zzzzzzzz''00011 0輸岀x3x2 xl xO000100100 1 0 01000BEGINPROCESS(oe , dir)BEGINIF oe='O'THEN av

2、二"zzzzzzzz'' b<ELSIF oe= T THENIF dir 二'O' THEN b<=a;ELSIF dir 二 T THEN a<=b;ENDIF;END IF ;END PROCESS ;END ar;功能為：24譯碼器 2.請說明下段程序的功能，寫出真值表，并畫出輸入輸出波形LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_u nsig ned.all;ENTITY aaa ISPORT

3、( reset,elk: IN STD_LOGIC;q: BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0)；END aaa;ARCHITECTURE bd OF aaa ISBEGINPROCESS(clk,reset)BEGINIF (wset='0 ) THEN q<= n000H;ELSIF (clk'eve nt AND clk=T) THENIF (q=5) THEN q<=' '000"ELSE q<=q+l;END IF;END IF;END PROCESS;END bd;功能為：帶進位借位的4位加

4、/減法器。 3分輸入輸出波形圖如下： 7分LIBRARY ieee;1. 試用VHDL語言編程實現(xiàn) 74LS273芯片的功能。USEieee.std_logic_l 164.ALL;TENTITYls273ISVPORT(dr,elk :INstd_logic;dINstdo gic_vector(7 DOWNTO 0);qOUTstd_logic_vector(7 DOWNTO 0 );4'y丿ENDARCHITECTURElock8OFls273IS1'BEGINa3.O Cb3.Oc3.0J CPROCESS ( elk )BEGINIF (CLR= O) THEN qC

5、OOOOOOOO''3'ELSEIF (clk ?event AND elk 二'1') THEN q<=d;ELSEIF ( clk= O) THEN qv 二 q；END IF;END PROCESS;END lock& 3.請用VHDL語言編程實現(xiàn)一個狀態(tài)向量發(fā)生器。LIBRARY ieee;USEieee.std_logic_l 164.ALL;TENTITYstasISrPORT(cp, rst :INstd_logic;P:BUFFER std_logic_vector(7 DOWNTO 0 );TENDstas;y丿，ARCH

6、ITECTUREarstasOF stasISVBEGINPROCESS (cp)BEGIN二'1')IF(rst= ,0,?) THEN pv= ” 0000000(F;ELSEIF (cp 9event AND cpp<= AA10101010AAWITH p SELECT WHEN “ 00000000"” 01010101"WHENT0101010"5001111 ”WHEN“01010101AA11110000AWHEN“ 00001111'” 11111111 ”WHENTil 10000"” 00000000

7、”WHEN“ ”niiiiii ；"00000000"WHENOTHERS;END IFEND PROCESS;END arstas;1 ?閱讀下段程序，畫出該電路的真值表，并詳細說明該電路的功能LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ab_8 ISPORT( a,b : IN STD_L0GIC_VECT0R(7 DOWNTO 0);ahb, alb, aeb: OUT STD_LOGIC);END ab_8;ARCHITECTURE bd OF ab_

8、8 ISBEGINPROCESS(a,b)BEGINIF a>b THEN ahbv 二 T; alb<= ,0,; aeb<=O;ELSIF a<b THEN ahb<= O; alb<=4' aeb<= ,0,;ELSE ahbv='O' albv 二'O' aebv 二 T;END IF;END PROCESS;END bd;1. (1)真值表如下：(5J輸入輸岀a> bahbalbaeba>b100a<b010a=b001（2）該電路是一個 8位兩輸入比較器， （20a、b是兩個8位輸入

9、端；（1 ）'ahb、alb和aeb為比較結(jié)果輸岀端，某種比較結(jié)果為真時，相應(yīng)的輸岀端為"1 ”，其余端輸岀為“0”（25）1. 試用VHDL語言編程實現(xiàn)一個2-4譯碼器，其真表如下輸入端輸岀端enselecty0XXTill ”100Tiio101T101"110T011"111“0111 ”2-4譯碼器碼參考程序如下：（答案不唯一，用 case語句、withselect語句都可以。）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;(1JENTITY ym24 ISP0RT( en: IN STD_LOGIC;selec

10、t: OUT STD_LOGIC_VECTOR( 1 DOWNTO 0);y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)(3 J)；END ym24;ARCHITECTURE bd OF ym24 ISBEGINPROCESS(e n)(1JIF(e n=T) THENyv="110'，WHENse8ct=WELSE”nor'WHENselect ="01"ELSEWHENselect 二"IO"ELSE"Olli” WHENselect =''ll"ELSE(4&#

11、39;)ELSE y<=”iiir'；END PROCESS;END bd;2?試用VHDL語言設(shè)計一個六路8位總線復(fù)用器, 其中A、B、C、D、E、F都是8位輸入總 線，Q為8位輸出總線，S為3位選擇端，其功能如下：輸入端輸岀端S2SIsoQ7Q0000Q=A001Q=B010Q=C011Q 二 D100Q=E101Q=F其它B= “00000000'六路8位總線復(fù)用器參考程序：(答案不唯一)LIBRARY ieee;USE ieee.std_logic_l 164.ALL;ENTITY mux6 IS(V)PORT(S : IN std_logic_vector(2

12、DOWNTO 0);A,B,C,D,E,F: IN std_logic_vector(7 DOWNTO 0);Q: OUT std_logic_vector(7 DOWNTO 0)；(3 END mux6;ARCHITECTURE bd OF mux6 ISBEGINPROCESS(S)BEGIN(1JCASE S ISWHEN n000n=>Qv=A;WHEN n001H=>Q<=B;WHEN n010H=>Q<=C;WHEN n0Hn=>Q<=D;WHEN n100H=>Q<=E;WHEN n101H=>Q<=F;WHEN

13、OTHERS=>Q<= HOOOOOOOO n;(4')END CASE;END PROCESS;END bd;(10 分)2、已知三選一電路如圖，判斷下列程序是否有錯誤，如有則指出錯誤所在，并給出完整程序。library ieee;use ieee.std_logic_1164.all;ENTITY MAX isport(al,a2,a3,s0,sl:i n bit;outy:out bit);end max:(20architecture one of max iscomp onent mux21aport(a,b,s:in std_logic;y:out stdo g

14、ic);end component: (2')signal temp std_logic; (2 )'beginul:mux21a port map(a2,a3,s0,temp); (2')u2:mux21a port map(al,temp,sl,outy); (2 )，end one;1己知電路原理圖如下，請用 VHDL語言編寫其程序答：library ieee;use ieee.std_logic_l 164.all;en tity mux21 isport(a,b,s:in bit;y:out bit);end mux21;(4')architectur

15、e one of mux21 issi ngle d,e:bit;begind<=a and (no t)s;e<=b and s;yv=d or e;end one;2. 設(shè)計一個帶有異步清零功能的十進制計數(shù)器。計數(shù)器時鐘elk上升沿有效、清零端CLRN、進位輸出COoCOUNTER10CLKCLRNDOUT3.OCO1答：library ieee;use ieee.std_logic_l 164.all;en tity cou nter 10 isport(clk,CLRN: in std_logic;dout:out in teger range 0 to 9);end co

16、u nter 10;(50architecture behav of cou nter 10 ISbeginprocess(clk)variable en t: in teger range 0 to 9; beg in(3 )IF CLRN=O THENCNT:=0;ELSIFclkA'l'and clk'event thenif cn t=9 the ncn t:=0;elsecn t:=c nt+l;end if;end if;dout<=c nt;end process;end behav;(703. 1)用VHDL語言編寫半加器和或門器件的程序，如圖所示

17、：H_ADDE : RRCOBSO答：半加器程序：library ieee;use ieee.std_logic_l 164.all;en tity h_adder is port(a,b:in std_logic;co,so:out std_logic);end h_adder;architecture one of h_adder isbeginso<=no t(a xor( not b);co<=a and b;end one;或門程序：library ieee;use ieee.std_logic_1164.all;en tity or2a isport(a,b:in st

18、d_logic;c:out stdo gic);end or2a;architecture one of or2a isbeginc<=a or b;end one;2)在上道題目的基礎(chǔ)上用元件例化語句設(shè)計1位全加器。RCBOR2A(2')(30主程序：library ieee;use ieee.std_logic_l 164.all;en tity f_adder isport(ai n,bi n,ci n:in stdo gic; cout,sum:out std_logic); end en tity Cadder;architecture fdl of Odder isc

19、omp onent h_adderport(a,b:in std_logic;co,so:out std_logic);(5')(50end comp onent;comp onent or2aport(a,b:in std_logic;c:out stdo gic);end comp onent;sig nal d,e,f:std_logic;beginul : h_adder port map(a=>a in ,b=>b in, co=>d,so=>e); u2 : h_adder port map(a=>e,b=>c in, co=>f,

20、so=>sum); u3 : or2a port map(d,f,cout);end fdl;1.試用VHDL語言編程實現(xiàn)一個總線開關(guān)，其真值表如下:輸入輸出enselectA0-A6B0-B6Y0-Y6，0'，x'、亠 »這 zzzzzzzTr ，0'ATTB1.總線開關(guān)的參考程序如下：LIBRARY ieee;USE ieee.std_logic_l 164.all;(1')ENTITY aaa ISPORT( en, select: IN STD_LOGIC ;A, B : IN STD_LOGIC_VECTOR(6 DOWNTO 0 );

21、Y : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)END aaa; (4') ARCHITECTURE ar OF aaa ISBEGINPROCESS(en, select)BEGINIF en=,0, THEN YVZZZZZZZ” ；ELSIF en=T THENIF select 二'O' THEN Y<=A;ELSIF select 二 T THEN Y<=B;END IF;END IF ;END PROCESS ;END ar;(5 )2. 試用 VHDL 語言編程實現(xiàn)個 MIO 計數(shù)器，要求該計數(shù)器有一個時鐘輸入端 elk

22、, 一個復(fù)位端rst （低電平復(fù)位），個使能端en （高電平時允許計數(shù)），個“計數(shù)到”輸出端cout,個4位二進制當前計數(shù)值輸出口 q; cout端僅當計數(shù)滿的個時鐘周期輸出高電平，其余時刻全保持低電平2.M10 計數(shù)器參考程序：LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;(1')(4')USE ieee.std_logic_unsigned.all;ENTITY aaa ISPORT(clk, rst, en : IN STD_LOGIC; cout: OUT STD_LOGIC;

23、q: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END aaa;ARCHITECTURE bd OF aaa ISBEGINPROCESS(clk,reset,en)BEGINIF (rst= ,O,) THEN q<="0000 n;ELSIF (clk'event AND elk 二 T) THENIF erTT THENIF (q=9) THEN q<= n0000n;ELSE q<=q+l;END IF;END IF;END IF;END PROCESS;3. 請用 VHDL 語言編程，用一個狀態(tài)機模型實現(xiàn)一個七段碼 L

24、ED 字符發(fā)生器。該電路有一個復(fù)位輸入端RST,個時鐘輸入端CP,組七段碼輸出端ag。在LED上七個段的排列位置如圖所示。該電路 的 功能為，當復(fù)位輸入端RST為低電平時，輸出端口輸出全零，無顯示；當 RST為高電平時，在時鐘 信 號CP的每個上升沿，輸出端依次輪流輸出 5個字符“HAPPY的七段碼（共陰極接法），周而復(fù)始。3. 用 VHDL 語言編程實現(xiàn)一個 LED 字符發(fā)生器參考程序：LIBRARY ieee;USE ieee.std_logic_l 164.ALL;ENTITY gene IS(1 )PORT( rst, cp : IN STD_LOGIC;a,b,c,d,e,f,g:

25、OUT STD_LOGIC) ； (1 )END gene;ARCHITECTURE aa OF gene ISTYPE state IS(sO,sl, s2, s3, s4, s5 );SIGNAL pstate: state;SIGNAL dout: STD_LOGIC_VECTOR(6 DOWNTO 0 );(2 ')BEGINprl: PROCESS(cp, rst,) BEGINIF rst='O* THEN pstate <=s0;ELSIF (cp*eventAND cp= !0' ) THENCASE pstate ISWHEN s0=> p

26、state <=sl;WHEN sl=> pstate <=s2;WHEN s2=> pstate <=s3;WHEN s3=> pstate <=s4;WHEN s4=> pstate <=s5;WHEN s5=> pstate <=sl;WHEN OTHERS=> pstate <=s0;END CASE;END IF;END PROCESS;pr2: PROCESS(pstate)BEGINCASE state ISWHEN sO => dout<= n0000000n;無顯示W(wǎng)HEN si =&g

27、t; dout<= H0110111"一 “ H"WHEN s2 => dout<= ,'11101ir,;一 “ A”WHEN S3 => doutv= ” 1100111”“ P"WHEN s4 => doutv= ” 1100111”“ P"WHEN s5 => dout<="0111011"一 “ Y"WHEN OTHERS=> dout<= n0000000n;-無顯示END CASE;END PROCESS;(50 a<=dout(6); b&l

28、t;=dout(5); c<=dout(4); d<=dout(3); e<=dout(2); fv=dout(l); gv=dout(0);END aa;（102?試用VHDL語言和進程語句，編程實現(xiàn)個 3-8譯碼器。該譯碼器的功能為，當使能信號 EN為低 電平時，輸出端丫7? Y0全為高電平（沒有輸出端被選中）;當EN為高電平時，每種ABC的輸入狀態(tài)組合能惟一地選中一路輸出（被選中的端輸出低電平）。真值表如下:輸入輸出ABcENY7Y6Y5Y4Y3Y2Y1Y00 :0 0111 I111 I1100011111111010101111110110 :1r 11111 11

29、10 :111 110011110111110111101111111 0110 1111111111101111111XXX011111111LIBRARY ieee;USEieee.std _lo gic_1164.ALL;TENTITYym38ISVPORT(a, b, c, en:INstd_logic;yOUTstd_logic_vector(7 DOWNTO 0);yy丿END,ARCHITECTUREarc38OF ls273 ISVBEGINPROCESS(en)VSIGNAL din :std_logic_vector(7 DOWNTO 0);1'BEGINdin&l

30、t;=a&b&c&en;WITH din SELECT yv 二' '11111110" WHEN “ 0001"” 11111101 "WHEN“ 0011；” 11111011" WHEN“ 0101；"11110111" WHEN“ 0111"”11101111" WHENT001”；”11011111" WHENT011 "”10111111 "WHENT101"” 01111111 "when “1111;"

31、;"llllllll"WHENOTHERS;END PROCESS;END arc38;1. 試用VHDL語言編程實現(xiàn)一個多路開關(guān)。該電路的功能為，當選擇端So和Si為不同狀態(tài)組合時，如果使能信號EN為電平，輸岀端 X和丫分別與不同的輸入通AoB。、A1B1、A2B2和A3B3接通并保持，當 EN為低電平時，X、丫輸岀為高阻態(tài)。真值表如下：輸入輸出SiSoENAoBoAiBiA2B2A3B3X丫001XXXXXXXXAoB ()011XXXXXXXXAiBi101XXXXXXXXA2B2111XXXXXXXXA3B3XX0XXXXXXXXzz1多路開關(guān)的參考程序如下：LIB

32、RARY ieee;USE ieee.std_logic_l 164.ALL;ENTITY mulkey ISPORT(sO,sl,e n, aO,bO,al,b 1 ,a2,b2,a3,b3:IN std_logic;x, y :OUT std_logic_vector(7 DOWNTO 0);3')；END mulkey;ARCHITECTURE armk OF mulkey ISSIGNAL sei :std_logic_vecter (1 DOWNTO 0 )BEGINsel<=sl&sO;2'PROCESS (en)BEGINIF (en =O) THE

33、N x<= Z;yv=!Z'ELSEIF (sel= ,OO,?) THENx<=a0 ;yv=bO;ELSEIF (sel= ,OF,) THENx<=al;y<=bi;ELSEIF (sehlOJ THENx<=a2;y<=b2 ；ELSEIF (sel= ,ir,) THENx<=a3;y<=b3 ；END IF;END PROCESS;END armk;六' 寫 VHDL 程序：(10分)1. 設(shè)計 10 進制加法計數(shù)器，要求含異步清 0 和同步時鐘使能。 注意：時鐘信號命名為 CLK, 使能信號為 EN, 清零信號為 R

34、ST, 計數(shù)輸出為 CQ。 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT10 ISPORT (CLK,RST,EN : IN STD_LOGIC;CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT : OUT STD_LOGIC );END CNT10;ARCHITECTURE behav OF CNT10 IS BEGINPROCESS(CLK, RST, EN)VARIABLE CQI : STD_LOGIC_VECTOR(3 DOWN

35、TO 0); BEGINIF RST = * 1 * THEN CQI := (OTHERS =>' 0 * );ELSIF CLK * EVENT AND CLK=' 1 * THENIF EN = 'I* THENIF CQI < 9 THEN CQI := CQI + 1;ELSECQI := (OTHERS => ' 0 * );- 計數(shù)器異步復(fù)位- 檢測時鐘上升沿- 檢測是否允許計數(shù) （ 同步使能 ） 一一允許計數(shù)，檢測是否小于 9- 大于 9, 計數(shù)值清零END IF;END IF;END IF;IF CQI = 9 THEN CO

36、UT <= *1'ELSE COUT <= * 0 *;END IF;CQ <= CQI; - 將計數(shù)值向端口輸出 END PROCESS;END behav;- 計數(shù)大于 9, 輸出進位信號2. 試描述一個帶進位輸入、輸出的 8 位全加器端口： A、B 為加數(shù)， CIN 為進位輸入， S 為加和， COUT 為進位輸出LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER8 ISPORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0)；CIN : IN STD_LOGIC;COUT

37、 : OUT STD_LOGIC ；S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);END ADDER8 ；ARCHITECTURE ONE OF ADDER8 ISSIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0);BEGINTS <= (、0，& A) + ('0，& B) + CIN;S <= TS(7 DOWNTO 0);COUT <= TS(8);END ONE;MUX七、 VHDL 程序設(shè)計： (20分) 設(shè)計一數(shù)據(jù)選擇器 MUX, 其系統(tǒng)模塊圖和功能表如下圖所示。試采用下面三種方

38、式中的兩種來描述該數(shù)據(jù)選擇器 的結(jié)構(gòu)體。SEL(1:0)SEL00011011OTHERS(a)用 if 語句。 (b)用 case 語句。(c)用 whe n else 語句。Library ieee;Use ieee. stdo gic_1164. all;En tity mymux isPort ( sei : in std_logic_vector(1 dow nto 0);Ai n. Bin : in stdo gic_vector(1 dow nto 0); Cout : out std_logic_vector(1 dow nto 0);End mymux;Architectur

39、e one of mymux isBeginProcess (sei, ain, bin)BeginIf sei =、' 00" then cout <= ain and bin; Elsif sei = ''01"then cout <= ain xor bin; Elsif sei = 'TO" then cout <=not ain; Else cout <= not bin;End if;End process;End one;Architecture two of mymux isBeginProc

40、ess (sei, ain, bin)BeginCase sei iswhen ''00"=>cout<=ainand bin;when ''01"=>cout<=ainxor bin;when、' 10"=>cout<=not ain;when others => cout <= not bin;End case;End process;End two;Architecture three of mymux isBeginCout <= ain and bin when

41、 sei = ''00" elseAin xor bin when sei = ''01 elseNot ain when sei = ''10" else not bin;End three;設(shè)計一個7段數(shù)碼顯示譯碼器，并逐行進行解釋LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;COUTAIN AND BINAIN XOR BINNOT AINNOT BIN"XX"-選擇信號輸入數(shù)據(jù)輸入ENTITY DECL7S ISPORT ( A : IN STD_LOGIC_

42、VECTOR (3 DOWNTO 0);LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) END ;ARCHITECTURE one OF DECL7S ISBEGINPROCESS( A )BEGINCASE A ISWHEN“0000”=>LED7S< ="Ollllll"WHEN“0001”=>LED7S< ="OOOOllO"WHEN” 0010”=>LED7S<=n1011011 nWHEN"OOH"=>LED7S< ="lOOllll

43、"WHEN“0100”=>LED7S< ="HOOllO"WHENn0101 n=>LED7S<=n1101101 nWHEN"OHO"=>LED7S< ="lllllOl"WHEN"Olli"=>LED7S< ="OOOOlll"WHEN” 1000”=>LED7S<=n1111111"WHEN” 1001”=>LED7S<="llOllll"WHEN "1010"

44、; => LED7S <= n1110111 n ;WHEN "lOll"=>LED7S <= "1111100AAWHEN "HOO"=>LED7S <= n 0111001 nWHEN "1101"=>LED7S <= n1011110 nWHEN "lllO"=>LED7S <= "1111001"WHEN "llll"=>LED7S <= "1110001"WHEN

45、OTHERS=>NULL ;END CASE ;END PROCESS ;END ;關(guān)于數(shù)據(jù)選擇器餓設(shè)計1、4選1多路選擇器的工F語句描述library ieee;use ieee.std_lo gic_ll64.all;entity multiplexersisport (m, b, c, d : in std_logic;s : in std_logic_vector (1 downto 0);o : out std_logic);end multiplexers；architecture archi of multiplexers_l is b eginprocess (a a b

46、, c, d, s)b eginif (s = "00") then o <= a;elsif (s = "01") then o <= b;elsif (s = "10") then o <= c;else o <= d;end if;end process;end archi;2、4選1多路選擇器的CASE語句描述library ieee;use ieee.std_logic_1164.all;entity multiplexers_2 isport (a, b, c, d : in std_logic;s

47、 : in std_logic_vector (1 downto 0); o : out std_logic);end multiplexers_2;architecture archi of multiplexers_2 is b eginprocess(a, b, c,d,s)b egincase siswhen"00” => o<=a;when"01" => o<=b;when"IO" => o<=c;whenothers =>o ?<=dend case;end process;entit

48、y mux4 isend archi;3、用選擇用條件信號賦值語句描述四選一電路port (iO, il,i2 f i3 : in std_logic;sei: in stdo gic_vector(1 downto 0);:outstd_logic);end mux 4Architecturertl of mux4isbeginqv=i0whensei="00"elseilwhensei=“01”elsei2whensei=“10”else13whensei=iirend rtl;4、信號賦值語句描述四選一電路entity mux4 isoutport(iO, 11r 1

49、2 r i3 : in std_logic;sei: in std_logic_vector(1 downto 0); q :stdo gic);end mux4;architecture rtl of mux 4 issignal sei : std_logic_vector (1 downto 0); b eginwith sei selectq<=i0 when sei ="00"ilwhensei =“01”i2whensei =“10”i3whensei =“11”X'when othersend rtl;關(guān)于編碼器和譯碼器的設(shè)計1、順序描述語句中i

50、f語句之8-3線編碼器library ieee;use ieee.std_logic_ll64.all;entity priority_encoder isport ( sei : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0);end priority_encode工；architecture archi of priority_encoder is BeginProcess (sei)BeginIf sei (0) = '1' then code<=n 000 nElsi

51、fsei (1) = '1'thencode<="001 n;Elsifsei(2)='1'thencode<="010 n;Elsifsel (3)=Tthencode<="011"Elsifsei(4)='1'thencode<="100 n;Elsifsei(5)='1'thencode<="101 n;Elsifsel(6)=Tthencode<= n 110n;Elsecode<= n lll"End ifEn

52、d process;End archi;2、并發(fā)描述語句之8-3線編碼器library ieee;use ieee . std_丄 ogic_1164 . mH;entity priority_encoder_l isport ( sei : in std_logic_vector (7 downto 0);code :out std_logic_vector (2 downto 0); end priority_encoder_l;architecture archi of priority_encoder_l is begincode="000" when sei (0

53、)_i '1 *"OOl"whensei (1)=11*else elsewhensei (2)='1'else"Oil 1'whensei 二11*else"100"whensei (4)=11*else"lOl"whensei (5)='1'else"HO1'whensei (6)=11kelsewhen sei (7) = * 1 * else"ZZZ"end archi;3、順序描述語句中case語句之3-8譯碼器library i

54、eee;use ieee.std_logic_ll64.all; entity encoder_38 isport ( sei : in std_logic_vector (2 downto 0); en : instd_logiccode :out std_logic_vector (7 downto 0); end encoder_38;architecture rtl of encoder_38 isb eginprocess (sei,en) b eginif (en= '1' ) thencase sei iswhen"000" =>code

55、<="00000001when” 001” =>code<="00000010when"010 n =>code<=n00000100 n;when"Oil" =>code<="00001000 n;when"100" =>code<=00010000 ”；when"101 ” =>code<=00100000 ”；when“110 “ =>code<=01000000 ”；when111" =>code<=10000000 ”；whenothers =>code<=00000000 "end case;else code <=zzzzzzzzend if;end process;end rtl;并發(fā)描述語句之3-8譯碼器library ieee;use ieee.std_logic_1164.all;entity encoder_38 isport