EDA技術(shù)與VHDL基礎(chǔ)課后習(xí)題答案

1、 EDA技術(shù)與VHDL基礎(chǔ)課后習(xí)題答案第一章 EDA技術(shù)概述一、填空題1、電子設(shè)計(jì)自動(dòng)化2、非常高速集成芯片硬件描述語言3、CAD、CAE、EDA4、原理圖輸入、狀態(tài)圖輸入、文本輸入5、VHDL、Verilog HDL6、硬件特性二、選擇題1、A2、C3、A4、D5、C6、D7、A第二章 可編程邏輯器件基礎(chǔ)一、填空題1、PLD2、Altera公司、Xilinx公司、Lattice公司3、基于反熔絲編程的 FPGA4、配置芯片二、選擇題1、D2、C3、C4、D第三章 VHDL程序初步程序結(jié)構(gòu)一、填空題1、結(jié)構(gòu)、行為、功能、接口2、庫和程序包、實(shí)體、結(jié)構(gòu)體、配置3、實(shí)體名、類型表、端口表、實(shí)體說明

2、部分4、結(jié)構(gòu)體說明語句、功能語句5、端口的大小、實(shí)體中子元件的數(shù)目、實(shí)體的定時(shí)特性6、設(shè)計(jì)庫7、元件、函數(shù)8、進(jìn)程PROCESS、過程PROCEDURE9、順序語句、并行語句二、選擇題1、D2、C3、C4、B5、D6、B7、A8、C三、簡答題2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY nand_3in ISPORT(a,b,c:IN STD_LOGIC; y:OUT STD_LOGIC);END;ARCHITECTURE bhv OF nand_3in ISBEGINy<=NOT(a AND b AND c);END bhv;5、0

3、0006、11110111（247）第四章 VHDL基礎(chǔ)一、填空題1、順序語句、并行語句2、跳出本次循環(huán)3、等待、信號(hào)發(fā)生變化時(shí)4、函數(shù)、過程5、值類屬性、函數(shù)類屬性、信號(hào)類屬性、數(shù)據(jù)類型類屬性、數(shù)據(jù)圍類屬性6、程序調(diào)試、時(shí)序仿真7、子程序、子程序二、選擇題1、B2、A3、A4、C5、B6、C7、D三、判斷題1、2、3、4、5、×6、×四、簡答題9、修改正確如下所示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count ISPORT(clk:IN BIT;

4、q:OUT BIT_VECTOR(7 DOWNTO 0);END count;ARCHITECTURE a OF count ISBEGINPROCESS(clk)IF clk'EVENT AND clk='1' THEN q<=q+1;END PROCESS;END a;10、修改正確如下所示：SIGNAL invalue:IN INTEGERRANGE 0 TO 15;SIGNAL outvalue:OUT STD_LOGIC;CASE invalue IS WHEN 0=>outvalue<='1' WHEN 1=>outv

5、alue<='0' WHEN OTHERS=>NULL;END CASE;11、修改正確如下所示：ARCHITECTURE bhv OF com1 ISBEGINSIGNAL a,b,c:STD_LOGIC;pro1:PROCESS（clk）BEGINIF NOT (clk'EVENT AND clk='1') THENx<=a XOR b OR c;END IF;END PROCESS;END;12、(1)PROCESS() -本題中兩條IF語句均為信號(hào)c進(jìn)行可能賦值，VHDL語言不允許IF a=b THEN c<=d; END

6、 IF; IF a=4 THEN c<=d+1; END IF; END PROCESS;(2)ARCHITECTURE behave OF mux IS -同時(shí)為q進(jìn)行多次可能賦值，VHDL語言不允許BEGIN q<=i0 WHEN a='0' AND b='0' ELSE '0' -WHEN ELSE語句語法錯(cuò)誤 q<=i1 WHEN a='0' AND b='1' ELSE '0' q<=i2 WHEN a='1' AND b='0' E

7、LSE '0' q<=i3 WHEN a='1' AND b='1' ELSE '0' END behave;13、next1<=1101WHEN(a='0' AND b='0')ELSE d WHEN a='0' ELSE c WHEN b='1' ELSE1011;15、（1）、STD_LOGIC_UNSIGNED（2）、GENERIC（3）、IN（4）、width-1（7）（5）、counter_n（6）、“00000000”（7）、clkEVENT

8、 AND clk=1（8）、ELSIF（9）、END IF（10）、q<= count16、修改正確如下所示：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY CNT10 IS PORT ( clk: IN STD_LOGIC;q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END CNT10; ARCHITECTURE bhv OF CNT10 ISSIGNAL q1 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS (clk)BEGINIF RISING_EDGE(clk

9、) begin begin修改為THENIF q1 < 9 THEN -q1為STD_LOGIC數(shù)據(jù)類型，而9為整型不可直接比較q1 <= q1 + 1; - q1為STD_LOGIC數(shù)據(jù)類型，而1為整型不可直接相加ELSE q1 <= (OTHERS => '0'); END IF;END IF; END PROCESS;q <= q1;END bhv;17、使用IF語句實(shí)現(xiàn)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 ISPORT(ain,bin,sel:IN STD_LOGIC_V

10、ECTOR(1 DOWNTO 0); cout:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);END;ARCHITECTURE bhv OF mux21 ISSIGNAL cout_tmp:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINPROCESS(ain,bin,sel)BEGINIF (sel="00") THEN cout_tmp<=ain OR bin;ELSIF (sel="01") THEN cout_tmp<=ain XOR bin; ELSIF (sel="10"

11、) THEN cout_tmp<=ain AND bin; ELSE cout_tmp<=ain NOR bin;END IF;END PROCESS;cout<=cout_tmp;END bhv;第五章 Quartus集成開發(fā)軟件初步一、填空題1、實(shí)體名2、FPGA、CPLD3、.vhd4、輸入、綜合、適配、仿真、下載5、RTL Viewer、Technology Map Viewer6、功能、參數(shù)含義、使用方法、硬件描述語言、模塊參數(shù)設(shè)置7、mif、hex8、根目錄二、選擇題1、C2、D第七章 有限狀態(tài)機(jī)設(shè)計(jì)一、設(shè)計(jì)題1、LIBRARY IEEE;USE IEEE.STD

12、_LOGIC_1164.ALL;ENTITY ztj ISPORT(clk,reset:IN STD_LOGIC;in_a:IN STD_LOGIC_VECTOR(1 DOWNTO 0); out_a:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE bhv OF ztj ISTYPE state IS(s0,s1,s2,s3); -用枚舉類型定義狀態(tài)，簡單直觀SIGNAL current_state,next_state:state; -定義存儲(chǔ)現(xiàn)態(tài)和次態(tài)的信號(hào)BEGINp1:PROCESS(clk) -狀態(tài)更新進(jìn)程BEGINIF clk&#

13、39;EVENT AND clk='1' THENIF reset='1' THEN current_state<=s0;ELSE current_state<=next_state;END IF;END IF;END PROCESS;p2:PROCESS(current_state,in_a) -次態(tài)產(chǎn)生進(jìn)程BEGINCASE current_state ISWHEN s0=>IF in_a/=”00” THEN next_state<=s1; ELSE next_state<=s0; END IF;WHEN s1=>IF

14、in_a=/'”01” THEN next_state<=s2; ELSE next_state<=s1; END IF;WHEN s2=>IF in_a=”11” THEN next_state<=s0 ELSE next_state<=s3; END IF;WHEN s3=>IF in_a/='11' THEN next_state<=s0; ELSE next_state<=s3; END IF;WHEN OTHERS=>NULL;END CASE;END PROCESS;p3:PROCESS(current_

15、state) BEGINCASE current_state ISWHEN s0=>out_a<='”0101”;WHEN s1=>out_a<=”1000”;WHEN s2=>out_a<=”1100”;WHEN s3=>out_a<=”1101”;WHEN OTHERS=>NULL;END CASE;END PROCESS;END;2、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ztj ISPORT(clk,reset:IN STD_LOGIC;ina:IN STD_LOGIC

16、_VECTOR(2 DOWNTO 0); outa:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE bhv OF ztj ISTYPE state IS(s0,s1,s2,s3); -用枚舉類型定義狀態(tài)，簡單直觀SIGNAL current_state,next_state:state;BEGINp1:PROCESS(clk) -狀態(tài)更新進(jìn)程BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THEN current_state<=s0;ELSE curr

17、ent_state<=next_state;END IF;END IF;END PROCESS;p2:PROCESS(current_state,ina) BEGINCASE current_state ISWHEN s0=> IF ina =”101” THEN outa<=”0010”; ELSIF ina=”111” THENouta <=”1100”; END IF;IF ina =”000” THEN next_state<=s1; ELSE next_state<=s0; END IF;WHEN s1=> outa<=”1001”;I

18、F ina =”110” THEN next_state<=s2; ELSE next_state<=s1; END IF;WHEN s2=> outa<=”1111”;IF ina =”011” THEN next_state<=s1; ELSIF ina =”100” THEN next_state<=s2;ELSE next_state<=s3; END IF;WHEN s3=> IF ina =”101” THEN outa<=”1101”; ELSIF ina=”011” THENouta <=”1100”; END IF;

19、IF ina =”010” THEN next_state<=s0; ELSE next_state<=s1; END IF;WHEN OTHERS=>NULL;END CASE;END PROCESS;END;3、LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ztj ISPORT(clk,reset:IN STD_LOGIC;ina:IN STD_LOGIC_VECTOR(1 DOWNTO 0); outa:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);END;ARCHITECTURE bhv OF zt

20、j ISTYPE state IS(s0,s1,s2,s3); -用枚舉類型定義狀態(tài)，簡單直觀SIGNAL state:istate;BEGINp1:PROCESS(clk)BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THEN state<=s0;result<='0'ELSECASE state ISWHEN s0=>outa<=”0000”;IF ina=”00”THEN state<=s1;ELSE state<=s0;END IF;WHEN s1=> outa <=”0001”;IF ina=”01” THEN state<=s2;ELSE s