lab3復雜流水線實驗報告

1、lab3復雜流水線實驗報告Lab3復雜流水化實驗Experiment1: To study the basics of forwarding. For all the programs please select Stall Detection and Forwarding should be ON.(a) Write a sample program that forwards between EXE stage and MEM stage on upper input of the the program below and show forwarding with arrow. Test

2、 it on the simulator and mention what value is being forwarded. DO NOT USE LW INSTRUCTION.Instruction123456789ADD R1,R2,R3IFIDEXEMEMWBSUB R5,R1,R4IFIDEXEMEMWB其中ADD指令中在MEM階段的ALUout-555（R2+R3）前遞到SUB指令的EXE階段的upper input。(b) Write a sample program that forwards between EXE stage and WB stage on upper in

3、put of the the program below and show forwarding with arrow. Test it on the simulator and mention what value is being forwarded. DO NOT USE LW INSTRUCTION.Instruction123456789ADD R1,R2,R3IFIDEXEMEMWBNOPIFIDEXEMEMWBSUB R5,R1,R4IFIDEXEMEMWB其中ADD指令中在WB階段的輸出555（R2+R3）前遞到SUB指令的EXE階段的upper input。(c) Write

4、 a sample program that forwards between EXE stage and MEM stage on lower input of the the program below and show forwarding with arrow. Test it on the simulator and mention what value is being forwarded. DO NOT USE LW INSTRUCTION.Instruction123456789ADD R1,R2,R3IFIDEXEMEMWBSUB R5,R4,R1IFIDEXEMEMWB其中

5、ADD指令中在MEM階段的ALUout-555（R2+R3）前遞到SUB指令的EXE階段的upper input。(d) Write a sample program that forwards between EXE stage and WB stage on lower input of the the program below and show forwarding with arrow. Test it on the simulator and mention what value is being forwarded. DO NOT USE LW INSTRUCTION.Instr

6、uction123456789ADD R1,R2,R3IFIDEXEMEMWBNOPIFIDEXEMEMWBSUB R5,R4,R1IFIDEXEMEMWB其中ADD指令中在WB階段的輸出555（R2+R3）前遞到SUB指令的EXE階段的upper input。(e) Write a sample program that forwards between MEM stage and WB stage. Write the program below and show forwarding with arrow. Test it on the simulator and mention wha

7、t value is being forwarded.Instruction123456789LW R1,0(R2)IFIDEXEMEMWBSW R3,0(R1)IFIDEXEMEMWB其中ADD指令在WB階段的輸出555（R2+R3）前遞到SW指令的MEM階段。(f) Write a program that causes Load Use Delay Stall. See what data is to be moved and notice exactly when the required Data is passed on to the waiting instruction. Sh

8、ow it as an arrow on the following diagram.Instruction123456789LW R1,0(R3)IFIDEXEMEMWBADD R2,R1 ,R3IFIDEXEEXEMEMWBBRANCH HAZARDS. (Lab Experiment 2)(a) Let us now study some branch hazard. First of all make sure that the Aggressive branching option is OFF, Stall Detection is ON and Forwarding is ON.

9、 Select Always Flush option from the branch Policy and write the following program. Does this program work properly. If not modify the program so that it works properly. It fills 10 memory locations memory with a value 222. Check what should be the values of all the registers if this program work is

10、 to properly (no useful instruction turning into NOP or getting flushed). Carefully note the use of SLTI instruction in the following loop.ADDI R3, R0, 0ADDI R1, R0, 0ADDI R2, R0, 222Loop: Addi R1, R1, 4SW R2, 100(R1)ADDI R3, R3, 1SLTI R5, R3, 10BNEQ R5, R0, loopADDI R7, R1, 10ADDI R8, R2, 5ADDI R2,

11、 R2, 100(i)Calculate the CPI for this program. 61/65 (ii)What changes can we make to this program so that it works properly (useful instructionsafter the program do not flush) 可以在BNEQ跳轉(zhuǎn)后面加3條ADD R0，R0，R0(iii)Run the same program with Predict NT option in Branch Policy. What difference do you seewhen

12、loop completes. Predict NT：循環(huán)執(zhí)行完了順序執(zhí)行了剩下3條語句。Always Flush：循環(huán)執(zhí)行完了依然將剩下3條語句flush掉了。(b) This problem is similar to problem A-1 at the end of the book. (Exercise A-1.)Note that you need to calculate the offset in the actual program in terms of number of instructions.Offset = -6 (A) Processor Configurati

13、on. Stall Detection ON., Forwarding: OFF, Aggressive Branching: YES, Branch Policy: Always Flush. Run the above program and fill the following table for the instructions in the loop body for first 2 or 3 iterations. Total Clock cycles to run the program _12345678910111213LW R1, 0(R2)IFIDEXEMEMWBADDI

14、 R1,R1, #1IFIDIDIDEXEMEMWBSW R1, 0(R2)IFIFIFIDIDIDEXEMEMWBADDI R2,R2, #4IFIFIFIDEXEMEMWBSUB R4,R3,R2IFIDIDIDEXEBNEZ R4, Loop1IFIFIFIDADDI R2, R0, 0IFADDI R3, R0, 014151617181920212223242526LW R1, 0(R2)IFIDEXEMEMWBADDI R1,R1, #1IFIDIDIDEXEMEMWBSW R1, 0(R2)IFIFIFIDIDIDEXEMEMWBADDI R2,R2, #4IFIFIFIDEXE

15、MEMSUB R4,R3,R2MEMWBIFIDIDBNEZ R4, Loop1IDIDEXEMEMWBIFIFADDI R2, R0, 0FLUSHEDIFIDEXEMEMWBADDI R3, R0, 0(b) Redo the part (a) with forwarding ON and other processor configuration is same. Total clock cycles _12345678910111213LW R1, 0(R2)IFIDEXEMEMWBIFIDEXEMEMADDI R1,R1, #1IFIDEXEEXEMEMWBIFIDEXESW R1,

16、 0(R2)IFIDIDEXEMEMWBIFIDADDI R2,R2, #4IFIFIDEXEMEMWBIFSUB R4,R3,R2IFIDEXEMEMWBBNEZ R4, Loop1IFIDIDEXEMEMWBADDI R2, R0, 0IFIFIDEXEMEMWBADDI R3, R0, 014151617181920212223242526LW R1, 0(R2)WBIFIDEXEMEMWBADDI R1,R1, #1EXEMEMWBIFIDEXEEXEMEMWBSW R1, 0(R2)IDEXEMEMWBIFIDIDEXEMEMWBADDI R2,R2, #4IFIDEXEMEMWBIFIFIDEXEMEMSUB R4,R3,R2IFIDEXEEXEWBIFIDEXEBNEZ R4, Loop1