基于dds參數(shù)可調(diào)諧波信號發(fā)生器的研究

1、附錄AResearch of Parameter Adjustable Harmonic Signal Generator Based on DDSLI WeiCollege of Computer and Information Engineering Hohai UniversityChangzhou, 213022, China liwei_2142ZHANG JinboCollege of Computer and Information Engineering Hohai University Changzhou, 213022, China zhangjbAbstractHarmo

2、nic signal generator whose frequency, phase and harmonic proportion are adjustable is designed for the detecting equipment of power system. The principle of DDS and the design requirement are introduced. Then the algorithm of ROM compression based on the symmetry of sine wave is expounded. Finally,

3、using Altera FPGA, the detail design of the whole system is presented and test waveforms are given. Test results indicate that the system fulfils the design requirements.1. IntroductionAn ideal power system supplies power with sine wave, but the practical waveform of power supply often has many harm

4、onic components. The basic reason of harmonic is that the power system supplies power to the electrical equipment with nonlinear characteristic. These nonlinear loads feed higher harmonic back to the power supply, and make the waveform of current and voltage in power system produce serious distortio

5、n. In the detection field of power system, standard signal generators which can simulate the power harmonic are highly needed to calibrate the power detecting equipment, such as phase detector, PD detector, and so on. So the research of parameter adjustable harmonic signal generator provides the exa

6、ct basis for the stable operation of power detecting equipment, and has great economic benefit and social value.2. Principle of direct digital synthesisDirect digital synthesis (DDS) is a new frequency synthesis technology which directly synthesizes waveform on the basis of phase. Using the relation

7、ship between phase and amplitude, the phase of waveform is segmented and assigned relevant addresses. In each clock period, these addresses are extracted and the relevant amplitudes are sampled. The envelope of these sampled amplitudes is the expected waveform. If the clock frequency is constant, th

8、e frequency of output signal is adjustable with different extracted steps of addresses.DDS is composed of phase accumulator, ROM table, DAC and LPF. In each clock period, the output of phase accumulator is accumulated with frequency control word, and high L-bit of the output are used as address to q

9、uery the ROM table. In the ROM, these addresses are converted to the sampled amplitudes of the expected waveform. Then DAC converts the sampled amplitudes to ladder wave. In the LPF, the ladder wave is smoothed, and the output is the continuous analog waveform.Suppose that the clock frequency is fc,

10、 frequency control word is K, phase accumulator is N-bit, then output frequency is fout=(K/2N)fc, frequency resolution is fmin=fc/2N. According to the Nyquist Sample Criterion, output frequency upper limit is fmax<0.5fc. Because of the non-ideal characteristic of LPF, output frequency upper limit

11、 of DDS is fmax=0.4fc.3. Scheme design3.1. Design requirementsThe goal of the system is to design a harmonic signal generator, whose frequency, phase and harmonic proportion are adjustable. The output waveform is composed of fundamental wave, 3th harmonic, 5th harmonic and 7th harmonic. Frequency re

12、solution is 1Hz. The adjustable range of initial phase is 02 and its resolution is 1o. The adjustable range of harmonic proportion is 050% and its resolution is 1%. According to the design requirements, system clock frequency is 15MHz and phase accumulator is 24-bit. In order to make the most of EAB

13、, 211×8 bits ROM table is adopted. 11-bit phase control word is used to meet the requirement of initial phase resolution. 7-bit proportion control word is adopted to realize the setting of harmonic proportion.3.2. Algorithm of ROM compressionAs is known, phase truncation error is the main facto

14、r of output waveform distortion. To avoid this, the ROM size must be exponentially increased, however the EAB of FPGA is limited. So the algorithm of ROM compression based on the symmetry of sine wave is adopted in the system. Sine wave of one period is divided into 4 sections: 0/2 、/2 、3/2 、3/22. U

15、sing the symmetry of sine wave, sampled amplitudes of the first section are stored in the ROM table. By address conversion and amplitude conversion, sampled amplitudes of one period sine wave can be generated. By this means, the ROM size is a quarter of the previous size. In the same ROM, sampling p

16、oints can be increased by 4 times with this method.Sampled amplitudes of quarter wave are stored in the ROM table. The output address of phase accumulator is (L+2)-bit. The low L-bit are used to query the ROM table while the high 2-bit are used to identify phase sections. When the highest bit is 1,

17、the output of ROM table should be symmetrically converted by the amplitude convertor. When the second highest bit is 1, the L-bit address should be symmetrically converted by the address convertor.4. System design based on FPGAThe system can be divided into two function modules: sine wave generation

18、 module and harmonic synthesis module. Sine wave generation module is the key part of the system. It can be divided into phase accumulator module and ROM compression module . Altera FPGA EP2C5Q208C8 is adopted as the core component of the system. VHDL is used to program the whole system. Compilation

19、 and simulation are implemented in Quartus .4.1. Sine wave generation modulephase accumulator module is composed of 24-bit accumulator and 11-bit adder. Under the control of system clock, the output of 24-bit accumulator is accumulated with 9-bit frequency control word. Then 11-bit adder adds 11-bit

20、 phase control word to the output of accumulator. High 13-bit of the final result are used as address to query the ROM compression module. ROM compression module is composed of address convertor, amplitude convertor and ROM table. 13-bit address of phase accumulator module is divided into three part

21、s. The highest bit is used as trigger signal of the amplitude convertor. The second highest bit is used as trigger signal of the address convertor. The low 11-bit are used to query the ROM table. Then sampled amplitudes of sine wave are generated. Simulation result of sine wave generation module is

22、shown in Fig.4. Frequency control word is set as 50 while phase control word is set as 180. When the enable signal is turned into low level, the first output value is the waveform data of address 180 in the ROM table. With each rising edge of system clock, the waveform data of address 180, 181, 182,

23、 183 are sent out. The output values are respectively 76, 76, 77, 77.4.2. Harmonic synthesis moduleHarmonic synthesis module implements the synthesis of fundamental wave, 3th harmonic, 5th harmonic and 7th harmonic. The 3th, 5th and 7th harmonic data are respectively multiplied by their proportion c

24、ontrol words. Then the results of multiplication are added to the fundamental wave data. The realization of multiplication is the emphasis of the module. Because it is difficult to implement the multiplication of floating-point format on FPGA, harmonic proportion is divided into numerator and denomi

25、nator. The numerator is defined as proportion control word while the denominator is 100. Firstly, harmonic data is multiplied by the proportion control word in the multiplier. Then, the product of multiplier is divided by 100 in the divider. Finally, the remainder is excluded and the quotient is pre

26、served. Using Altera IP tools, the multiplier and the divider of harmonic synthesis module are realized. Block diagram of harmonic synthesis module is shown. Simulation result of harmonic synthesis module is. Control words are set before 2.0ms. Fundamental wave frequency is 50Hz, and its initial pha

27、se is 0o. The 3th harmonic frequency is 150Hz, initial phase is 45o and proportion is 50%. The 5th harmonic frequency is 250Hz, initial phase is 90o and proportion is 25%. The 7th harmonic frequency is 350Hz, initial phase is 135o and proportion is 17%. When enable signal is turned into low level, h

28、armonic synthesis module begins to generate the harmonic synthesis data.5. Test resultsFigure 7. Two-channel sine waves (frequency is50Hz and phase difference is 180o)Figure 8. Two-channel sine waves (frequency is50Hz and phase difference is 120o)Figure 9. Harmonic synthesis waveformAfter the design

29、 of the system, the whole function is tested. Fig.7 shows two-channel sine waves whose frequency is 50Hz and phase difference is 180o. Fig.8 shows two-channel sine waves whose frequency is 50Hz and phase difference is 120o. Fig.9 shows the harmonic synthesis waveform, whose fundamental wave proporti

30、on is 100%, 3th harmonic proportion is 25%, and 5th harmonic proportion is 10%. Test waveforms indicate that the parameter adjustable harmonic signal generator fulfils the design requirements.6. ConclusionIn the detection field of power system, standard signal generators which can simulate the power

31、 harmonic are highly needed to calibrate the power detecting equipment. To solve this problem, a harmonic signal generator whose frequency, phase and harmonic proportion are adjustable is presented. Using Altera FPGA, the whole system is implemented. Test results indicate that the adjustment and sta

32、bilization precision of parameters meet the design requirements. This subject provides the exact basis for the stable operation of power detecting equipment, and has great economic benefit and social value.References1 Li Xiaoming and Qu xiujie, “Application of DDS/FPGA in Signal Generator Systems”,

33、Modern Electronics Technique, 2021 ：78-79.2 Yu Yong and Zheng Xiaolin, “Design and Implementation of Direct Digital Frequency Synthesis Sine Wave Generator Based on FPGA”, Journal of Electron Devices, 2021 ：596-599.3 M.A. Taslakow, “Direct Digital Synthesizer with improved spectrum at low frequencie

34、s”, 2021 IEEE/EIA International Frequency Control Symposium and Exhibition, 2021 ：280-284.4 Yang Li and Li Zhen, “Multi-wave shape Signal Generator Based on FPGA”, Radio Engineering, 2021 ：46-48.5 D.J. Betowski and V. Beiu, “Considerations for phase accumulator design for Direct Digital Frequency Sy

35、nthesizers”, IEEE International Conference on Neural Networks and Signal Processing, 2021 ：176-179.6 J. Vankka, “Methods of mapping from phase to sine in Direct Digital Synthesis”, 1996 IEEE International Frequency Control Symposium, 1996：942-950.7 K.A. Essenwanger and V.S. Reinhardt, “Sine output D

36、DSs A survey of the state of the art”, 2021 IEEE International Frequency Control Symposium, 2021：370-376.附錄B基于DDS參數(shù)可調(diào)諧波信號發(fā)生器的研究李煒學(xué)院計(jì)算機(jī)與信息工程河海大學(xué)常州， 213022 ，中國liwei_2142張金波學(xué)院計(jì)算機(jī)與信息工程河海大學(xué)常州， 213022 ，中國zhangjb摘要諧波信號發(fā)生器的頻率，相位和諧波比例可調(diào)的目的是為檢測設(shè)備的電源系統(tǒng)。介紹了DDS的原理和設(shè)計(jì)要求。然后在ROM的壓縮算法的基礎(chǔ)上闡述了正弦波的對稱性。最后，利用Altera的FPGA詳

37、細(xì)的設(shè)計(jì)了整個系統(tǒng)，并給出了測試波形。實(shí)驗(yàn)結(jié)果表明，該系統(tǒng)滿足了設(shè)計(jì)要求。1簡介一個理想的電力系統(tǒng)是正弦波供電，但實(shí)際波形電源往往有許多諧波成分。產(chǎn)生諧波的基本原因是電力系統(tǒng)供電的電氣設(shè)備的非線性特性。這些非線性負(fù)載依靠高次諧波回到電源，使波形的電流和電壓的電力系統(tǒng)產(chǎn)生嚴(yán)重的失真。在電力系統(tǒng)的檢測領(lǐng)域，標(biāo)準(zhǔn)信號發(fā)生器可以模擬電力諧波非常需要標(biāo)定功率檢測設(shè)備，如相位檢測器，局部放電檢測儀，等等。因此，為參數(shù)可調(diào)諧波信號發(fā)生器的研究提供準(zhǔn)確的依據(jù)和穩(wěn)定運(yùn)行的電力檢測設(shè)備，并具有很大的經(jīng)濟(jì)利益和社會價值。2直接數(shù)字頻率合成的原理直接數(shù)字合成（ DDS ）是一種在相位的基礎(chǔ)上直接合成波形的新的頻率合成

38、技術(shù)，利用相位和振幅之間的關(guān)系，對相位的波形分割和分配有關(guān)的地址。在每一個時鐘周期，提取這些地址和有關(guān)振幅采樣。系統(tǒng)中這些被抽樣幅度是預(yù)期的波形。如果時鐘頻率是恒定的，頻率可調(diào)輸出信號的地址可有不同提取步驟。直接數(shù)字頻率合成器由累加器，存儲器， DAC和低通濾波器組成。在每一個時鐘周期，輸出相位累加器是由頻率控制字累計(jì)，高左旋位輸出作為地址查詢存儲器。在ROM中，這些地址被轉(zhuǎn)換為預(yù)期波形的抽樣振幅。然后數(shù)模轉(zhuǎn)換器轉(zhuǎn)換采樣振幅為階梯波。在低通濾波器，平滑階梯波，輸出的是連續(xù)的模擬波形。假設(shè)時鐘頻率是fc，頻率控制字為K ，相位累加器為N位，則輸出頻率fout = （ K/2N ）fc，頻率分辨率

39、是fmin = fc/2N 。根據(jù)奈奎斯特采樣標(biāo)準(zhǔn)，輸出頻率上限是fmax<0.5fc 。由于非理想特性的低通濾波器，DDS的輸出頻率上限的是fmax = 0.4fc。3方案設(shè)計(jì)3.1設(shè)計(jì)要求該系統(tǒng)的目標(biāo)是設(shè)計(jì)一個諧波信號發(fā)生器，其頻率相位和諧波比例可調(diào)。輸出波形是由基波，第三諧波，第五次諧波和第七次諧波構(gòu)成。頻率分辨率是1赫茲?？烧{(diào)范圍的初始階段為02，其圖形分辨率為1?？烧{(diào)范圍的諧波比例為050，其圖形分辨率是1。根據(jù)設(shè)計(jì)要求，系統(tǒng)時鐘頻率是15MHz，相位累加器是24位。為了產(chǎn)生最多的EAB,采用211×8位ROM。11位相位控制字是用來滿足初始階段的圖形分辨率。7位比例

40、控制字采用正確設(shè)定的諧波比例。3.2ROM的算法正如人們所知，相位截斷誤差的主要因素是輸出波形畸變。為避免出現(xiàn)這種情況，ROM大小必須成倍增加，但EAB的FPGA是有限的。因此，該算法壓縮的ROM基于系統(tǒng)中正弦波的對稱性。正弦波一期分為4個部分：0/2，/2 ，3/2，3/22。使用對稱的正弦波，取樣振幅的第一部分都存儲在ROM。通過地址轉(zhuǎn)換和振幅轉(zhuǎn)換，一期正弦波的采樣振幅可以生成。通過這一手段，ROM大小是之前大小的四分之一。在相同的ROM中應(yīng)用這種方法，采樣點(diǎn)可提高4倍。采樣波振幅分塊存儲在ROM中。輸出相位累加器地址是（L+2）-bit。低左旋位是用來查詢表的ROM，而高2位是用來識別階

41、段部分。當(dāng)最高位為1 ，輸出的ROM表為對稱轉(zhuǎn)換的幅度變換器。當(dāng)?shù)诙€最高位是1 ，L型位地址為對稱轉(zhuǎn)換的地址轉(zhuǎn)換。4基于FPGA的系統(tǒng)設(shè)計(jì) 該系統(tǒng)可分為兩個功能模塊：正弦波代模塊和諧波合成模塊。正弦波代模塊是系統(tǒng)中關(guān)鍵的部分。它可分為階段累加器模塊和ROM壓縮模塊。Altera的FPGA EP2C5Q208C8是該系統(tǒng)的核心組成部分，VHDL語言用來設(shè)計(jì)整個系統(tǒng)。匯編和仿真使用Quartus 實(shí)現(xiàn)。4.1正弦波生成模塊相位累加器模塊由24位累加器和11位加法器組成的。系統(tǒng)時鐘所控制的是9位頻率控制字與24位累加器的相加的輸出。然后11位相位控制字增加了11位加法器和累加器的輸出。高13位的最

42、后結(jié)果被用作處理查詢正弦數(shù)據(jù)查詢ROM模塊。正弦數(shù)據(jù)查詢ROM模塊是由地址轉(zhuǎn)換，振幅轉(zhuǎn)換器和ROM模塊組成的。13位地址相位累加器模塊分為三部分。最高位被用作觸發(fā)信號的幅度變換器。第二個最高位被用作觸發(fā)信號的地址轉(zhuǎn)換。低11位是用來查詢正弦數(shù)據(jù)查詢ROM模塊。然后取樣振幅產(chǎn)生正弦波。正弦波信號發(fā)生器模塊的仿真結(jié)果正確。頻率控制字設(shè)置為50，而相位控制字設(shè)置為180。當(dāng)時鐘控制信號變成低電平時，第一個產(chǎn)生數(shù)值是ROM模塊中地址為180時所對應(yīng)的正弦波的值。系統(tǒng)時鐘的每個上升沿產(chǎn)生波形數(shù)據(jù)地址所對應(yīng)的180，181，182，183。其產(chǎn)生的數(shù)值分別為76，76，77，77。4.2諧波合成模塊諧波合

43、成模塊完成的是基波，第三次諧波，第五次諧波和第七次諧波的合成。第三次，第五次和第七次諧波數(shù)據(jù)分別乘以其比例控制字。然后其相乘的結(jié)果再加上基波數(shù)據(jù)。其結(jié)果實(shí)現(xiàn)的是增強(qiáng)電路模塊。因?yàn)榛贔PGA很難實(shí)施多元化的浮點(diǎn)格式，調(diào)和比例的劃分結(jié)果分為分子和分母。分子被定義為比例控制字而分母為100。首先,諧波的數(shù)據(jù)是乘以這個比例控制字的乘數(shù)。然后，這個相乘后的結(jié)果再在觸發(fā)其里除以100。最后，剩下的是余數(shù)和商被保存了下來。使用Altera IP工具、乘法器和除法來實(shí)現(xiàn)器諧波合成模塊?？驁D的諧波合成將被顯示。諧波合成模塊的仿真結(jié)果正確。使用2.0ms以內(nèi)的控制字的話。基波的頻率為50赫茲，其初始相位是0度。

44、第三次諧波頻率為150赫茲，其初始相位是45度和比例為50%。第五次諧波頻率是250赫茲, 其初始相位是90度和比例是25%。第七次諧波頻率是350Hz, 其初始相位是135度和比例是17%。當(dāng)時鐘控制信號轉(zhuǎn)變成低電平時，諧波合成模塊開始產(chǎn)生所合成的諧波的數(shù)據(jù)。5測試結(jié)果經(jīng)過系統(tǒng)的設(shè)計(jì)，整體功能的測試。圖7顯示雙通道正弦波，其頻率為50赫茲和相位差是180度。圖8顯示雙通道正弦波，其頻率為50赫茲和相位差是120度。圖9顯示了諧波合成波形，其基波比例為100，第三諧波的比例是25，和第5次諧波的比例是10。試驗(yàn)表明，波形參數(shù)可調(diào)諧波信號發(fā)生器滿足了設(shè)計(jì)要求。圖 7 雙通道正弦波（頻率50，相位差是180o ）圖 8 雙通道正弦波（頻率50，相位差是120o ）圖9 諧波合成波形6結(jié)論在電力系統(tǒng)的檢測領(lǐng)域，標(biāo)準(zhǔn)信號發(fā)生器模擬電力諧波非常精確的標(biāo)定功率檢測設(shè)備。為了解決這個問題，介紹了一種頻率，相位和諧波比例可調(diào)的諧波信號發(fā)