鍵盤掃描及計(jì)算器VHDL仿真

1、電子設(shè)計(jì)自動(dòng)化EDA簡(jiǎn)易計(jì)算器設(shè)計(jì)簡(jiǎn)易計(jì)算器設(shè)計(jì) EDA實(shí)驗(yàn)報(bào)告 一、 實(shí)驗(yàn)內(nèi)容實(shí)驗(yàn)要求：完成個(gè)位數(shù)的加減乘運(yùn)算，輸入用矩陣鍵盤，輸出用數(shù)碼管顯示，每輸入一次數(shù)據(jù)要顯示在數(shù)碼管上。矩陣鍵盤共16個(gè)按鍵，用其中10個(gè)做個(gè)位數(shù)的輸入，用3個(gè)分別做加減乘運(yùn)算，用其中1個(gè)做等于操作，各位數(shù)的運(yùn)算結(jié)果最多兩位，用動(dòng)態(tài)掃描數(shù)碼管顯示運(yùn)算結(jié)果。二、 小組成員三、 實(shí)現(xiàn)方法系統(tǒng)組成及連接原理如圖所示，主要由由七個(gè)功能模塊組成：分頻模塊（為鍵盤掃描模塊和防抖模塊提供時(shí)鐘）、鍵盤掃描驅(qū)動(dòng)模塊（依次置零）、鍵盤按鍵值編碼模塊、鍵盤編碼值防抖模塊、運(yùn)算模塊，數(shù)碼管顯示驅(qū)動(dòng)模塊、動(dòng)態(tài)掃描驅(qū)動(dòng)模塊。分頻鍵值編碼防抖鍵盤矩

2、陣行驅(qū)動(dòng)時(shí)鐘數(shù)碼管顯示運(yùn)算數(shù)碼管動(dòng)態(tài)顯示1.分頻模塊由于FPGA實(shí)驗(yàn)板的原始時(shí)鐘頻率高達(dá)33.8688MHz，所以不能直接接入設(shè)計(jì)模塊中使用，就需要用到分頻模塊。將33.8688MHz分頻到4KHz和10Hz來使用，一個(gè)用于行驅(qū)動(dòng)掃描時(shí)鐘，一個(gè)用于防抖模塊。所以，采用寫一個(gè)可變分頻元件來調(diào)用。元件視圖：主要代碼如下（完整代碼見附錄，下同）：architecture RTL of freq_division iscomponent fredivn isgeneric(n:positive); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);end

3、 component;beginU1:fredivngeneric map(n=3)port map(clkin=clk,clkout=clkout_kb);end RTL;仿真結(jié)果如下圖：達(dá)到預(yù)期的目的2.行驅(qū)動(dòng)模塊（依次對(duì)行置零）：鍵盤掃描的原理就是檢測(cè)行列信號(hào)然后判斷出具體是按下了哪一個(gè)按鍵。所以，對(duì)行依次置零，當(dāng)置零頻率較快時(shí)，按下某一個(gè)按鍵后，一定能得到某一列的信號(hào)輸出為零，如下圖：當(dāng)行信號(hào)為1110時(shí)，若按下了0鍵，就會(huì)得到1110的列信號(hào)，立馬就快可以譯碼出按鍵值，若按下4鍵、8鍵、C鍵則都不會(huì)有輸出。主要代碼如下：process(clkin)beginif clr=1 then

4、count=00; elsif rising_edge(clkin) thenif count=11 thencount=00;elsecount=count+1;end if;end if;end process;process(count)beginif count=01 thenkeydrv=1110;elsif count=10 thenkeydrv=1101;elsif count=11 then keydrv=1011; elsif count=00 thenkeydrv=0111;end if;end process;仿真結(jié)果如下圖：達(dá)到預(yù)期的目的3.鍵值編碼模塊依據(jù)行驅(qū)動(dòng)模塊，

5、當(dāng)按下某一個(gè)按鍵后，立馬可以根據(jù)行列和并位信號(hào)得到唯一的鍵盤編碼值，用5位矢量來保存結(jié)果，當(dāng)沒有按鍵按下時(shí)，編碼值一直保持著11111不變，并在后端的模塊中不對(duì)其做任何處理。以下列出部分編碼表（完整編碼表見附錄）：十進(jìn)制數(shù)行&列HEX七段碼HEX011101110EE11111107E411011110DE011001133511011101DD10110115B主要代碼如下：process(clk)beginif clr=0 thenif rising_edge(clk) thenif temp1=11101110 thenkeyvalue1=00000; -0elsif temp1=111

6、01101 thenkeyvalue1=00001; -1elsif temp1=11101011 thenkeyvalue1=00010; -2elsif temp1=11100111 thenkeyvalue1=00011; -3elsif temp1=11011110 thenkeyvalue1=00100; -4elsif temp1=11011101 thenkeyvalue1=00101; -5elsif temp1=11011011 thenkeyvalue1=00110; -6elsif temp1=11010111 thenkeyvalue1=00111; -7elsif t

7、emp1=10111110 thenkeyvalue1=01000; -8elsif temp1=10111101 thenkeyvalue1=01001; -9elsif temp1=10111011 thenkeyvalue1=01010; -10elsif temp1=10110111 thenkeyvalue1=01011; -11elsif temp1=01111110 thenkeyvalue1=01100; -12elsif temp1=01111101 thenkeyvalue1=01101; -13elsif temp1=01111011 thenkeyvalue1=0111

8、0; -14elsif temp1=01110111 thenkeyvalue1 test1 test2 test3 test4 test5 test6 test7 test8 test9 test10 test11 test12 test13 test14 test15 test16null;end case;if test1=test5 and test2=test6 and test3=test7 and test4=test8 and test5=test9 and test6=test10 and test7=test11 and test8=test12 and test9=tes

9、t13 and test10=test14 and test11=test15 and test12=test16 and test1 /= UUUUUUUU then仿真波形如下：從圖中可以看出最終temp1從臨時(shí)信號(hào)temp得到最終輸出，達(dá)到防抖：5.運(yùn)算模塊當(dāng)前段的模塊經(jīng)過防抖處理以后得到穩(wěn)定的按鍵信號(hào)，比如1+2=3,轉(zhuǎn)化為編碼值就是11101101 10111011 01111101 11100111 = ED BB EB 7D E7(具體編碼表見附錄)主要代碼如下：if ysfh=0 then result=first+second; elsif ysfh=1 then resul

10、t=first-second; elsif ysfh=2 then result=first*second; end if; n=n+1;elsif n=100 then n=000;end if;end if; end process; process (n) begin if n=001then keyvaluein=conv_std_logic_vector(first,8); elsif n=011then keyvaluein=conv_std_logic_vector(second,8); elsif n=100then keyvaluein=conv_std_logic_vect

11、or(result,8); end if; end process;仿真波形如下：以1+3=4 和 5x6=30為例：編碼：01 + 03 =04 05 X 06 =1E6.數(shù)碼管顯示模塊以及動(dòng)態(tài)掃描模塊由于次兩個(gè)模塊是密切相關(guān)的，所以統(tǒng)一到一起驗(yàn)證。經(jīng)過運(yùn)算得到最終的顯示結(jié)果后，要在七段數(shù)碼管中顯示，就必須有每一個(gè)數(shù)的七段碼，同時(shí)，由于前面的運(yùn)算模塊的結(jié)果最大可以達(dá)到81，也就是需要8位二進(jìn)制，兩位十進(jìn)制來表示，所以就必須通過顯示模塊來分離出十位和個(gè)位。分離出十位和個(gè)位以后，就必須要利用動(dòng)態(tài)掃描使兩個(gè)數(shù)都能顯示出來。因?yàn)?個(gè)七段數(shù)碼管的abcdefg位是連在一起的，只有利用分時(shí)間隔來顯示，一

12、次使能一個(gè)數(shù)碼管，顯示一位數(shù)，當(dāng)頻率較高時(shí)，就可以得到兩位數(shù)的顯示效果。數(shù)碼管顯示模塊主要代碼如下：if num=0 thenten:=0;one:=10;elsif num0thenten:=0;one:=num;elsif num9 thenten:=1;one:=num-10;elsif num19 thenten:=2;one:=num-20;elsif num29 thenten:=3;one:=num-30;elsif num39 thenten:=4;one:=num-40;elsif num49 thenten:=5;one:=num-50;elsif num59 thente

13、n:=6;one:=num-60;elsif num69 thenten:=7;one:=num-70;elsif num79 thenten:=8;one:=num-80;elsif num89 thenten:=9;one:=num-90;end if;t=conv_std_logic_vector(ten,4);o=conv_std_logic_vector(one,4);動(dòng)態(tài)掃描模塊主要代碼如下：if count=00 thenshowout=show1;en=00000010;elsif count=01 thenshowout=show2;en showout 0110000 30

14、02 = showout 1101101 6D03 = showout 1111001 79由以上波形可以看出：01 + 02 = 03的計(jì)算完成了。五、 總結(jié)本次EDA設(shè)計(jì)實(shí)踐，完成了從VHDL代碼編寫到硬件實(shí)現(xiàn)的整個(gè)流程，掌握了一些FPGA的相關(guān)概念以及ISE軟件和Active-HDL軟件的使用方法。最重要的就是組員之間的合作，因?yàn)閂HDL程序是模塊化編寫的，所以不同模塊是由不同人來完成編譯的，要達(dá)到各個(gè)模塊之間能夠良好的銜接通信，就必須有一個(gè)很好的溝通交流，把大家的思路集中起來，一起討論、編寫、調(diào)試程序。【附錄一】完整程序：分頻：library IEEE;use IEEE.STD_LOG

15、IC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fredivn is generic(n:integer:=3); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);end fredivn;architecture Behavioral of fredivn issignal clk1:std_logic:=0;signal counter:integer range 0 to n; beginprocess(clkin) begin

16、if rising_edge(clkin)then if counter=(n-1)/2 then clk1=not clk1; counter=0; else counter=counter+1; end if; end if; end process; clkout=clk1; end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity keyscan is Port ( clr:in std_logic

17、; clkin : in STD_LOGIC; keydrv :out STD_LOGIC_VECTOR(3 downto 0);end keyscan;architecture behavioral of keyscan issignal count : std_logic_vector(1 downto 0); beginprocess(clkin)beginif clr=1 then count=00;elsif rising_edge(clkin) thenif count=11 thencount=00; elsecount=count+1;end if;end if;end pro

18、cess;process(count)beginif count=01 thenkeydrv=1110;elsif count=10 thenkeydrv=1101;elsif count=11 thenkeydrv=1011; elsif count=00 thenkeydrvclkin,keydrv=keydrv1,clr=clr); tempclkin,temp=temp,temp1=temp1,clr=clr);process(clk)beginif clr=0 thenif rising_edge(clk) thenif temp1=11101110 thenkeyvalue1=00

19、000;elsif temp1=11101101 thenkeyvalue1=00001;elsif temp1=11101011 thenkeyvalue1=00010;elsif temp1=11100111 thenkeyvalue1=00011;elsif temp1=11011110 then keyvalue1=00100; elsif temp1=11011101 thenkeyvalue1=00101;elsif temp1=11011011 thenkeyvalue1=00110;elsif temp1=11010111 thenkeyvalue1=00111;elsif t

20、emp1=10111110 then keyvalue1=01000;elsif temp1=10111101 thenkeyvalue1=01001;elsif temp1=10111011 thenkeyvalue1=01010;elsif temp1=10110111 thenkeyvalue1=01011;elsif temp1=01111110 thenkeyvalue1=01100;elsif temp1=01111101 thenkeyvalue1=01101;elsif temp1=01111011 then keyvalue1=01110;elsif temp1=011101

21、11 thenkeyvalue1=01111;end if;end if;end if;end process;keycode=keyvalue1;end rtl;防抖：library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity fangdou is port(keycode:in std_logic_vector(4 downto 0);keycode1:out std_logic_ve

22、ctor(4 downto 0);start:out std_logic;clk_f,clr:in std_logic);end fangdou;architecture fangdou of fangdou issignal count1:std_logic_vector(2 downto 0);signal key1:std_logic_vector(4 downto 0);signal key2:std_logic_vector(4 downto 0);signal key3:std_logic_vector(4 downto 0);signal key4:std_logic_vecto

23、r(4 downto 0);signal key5:std_logic_vector(4 downto 0);signal key6:std_logic_vector(4 downto 0);signal key7:std_logic_vector(4 downto 0);signal key8:std_logic_vector(4 downto 0);signal start_1:std_logic;begin process(clk_f)beginif clr=1 thenkey1=00000;key2=00001;key3=00010;key4=00011;key5=00100;key6

24、=00101;key7=00110;key8=00111;count1=000;start_1=1;elseif rising_edge(clk_f) then if count1=111 thencount1=000; else count1key1key2key3key4key5key6key7key8null;end case;if key1=key2 and key2=key3 and key3=key4 and key4=key5 and key5=key6 and key6=key7 and key7=key8 and key1/=UUUUUthenkeycode1=key1;st

25、art_1=0 after 5ns;end if;end process;start=start_1;end fangdou;運(yùn)算：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity yunsuan isport(start: in std_logic;keycode1:in std_logic_vector(4 downto 0);keyvaluein:out std_logic

26、_vector(7 downto 0);end yunsuan;architecture Behavioral of yunsuan issignal first,second,result,ysfh: integer range 0 to 99;signal n:std_logic_vector(2 downto 0);begin process(start,keycode1)beginif start=1 thenn=000;else if n=000 thenif keycode1=00001then first=1;elsif keycode1=00010then first=2;el

27、sif keycode1=00011then first=3;elsif keycode1=00100then first=4;elsif keycode1=00101then first=5;elsif keycode1=00110then first=6;elsif keycode1=00111then first=7;elsif keycode1=01000then first=8;elsif keycode1=01001then first=9;elsif keycode1=00000 then first=0;end if;n=n+1;elsif n=001 then if keyc

28、ode1=01010then ysfh=0; elsif keycode1=01011then ysfh=1; elsif keycode1=01100then ysfh=2;end if; n=n+1;elsif n=010 thenif keycode1=00001then second=1;elsif keycode1=00010then second=2;elsif keycode1=00011then second=3;elsif keycode1=00100then second=4;elsif keycode1=00101then second=5;elsif keycode1=

29、00110then second=6;elsif keycode1=00111then second=7;elsif keycode1=01000then second=8;elsif keycode1=01001then second=9;elsif keycode1=00000then second=0;end if;n=n+1;elsif n=011 and keycode1=01101 then if ysfh=0 then result=first+second;elsif ysfh=1 then result=first-second;elsif ysfh=2 then resul

30、t=first*second; end if; n=n+1;elsif n=100 thenn=000;end if;end if;end process;process (n)beginif n=001then keyvaluein=conv_std_logic_vector(first,8);elsif n=011then keyvaluein=conv_std_logic_vector(second,8); elsif n=100then keyvaluein=conv_std_logic_vector(result,8);end if; end process;end Behavior

31、al;數(shù)碼管顯示：library IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity shumaguanxianshi isport(keyvaluein:in std_logic_vector(7 downto 0);clk:in std_logic;show1,show2:out std_logic_vector(6 downto 0);end shumaguanxianshi ;architecture shumaguanxianshi o

32、f shumaguanxianshi issignal t:std_logic_vector(3 downto 0); signal o:std_logic_vector(3 downto 0);beginprocess(clk)variable num:integer range 0 to 99;variable ten,one: integer range 0 to 15;beginif rising_edge(clk) thennum:=conv_integer(keyvaluein);if num=0 thenten:=0;one:=10;elsif num0then ten:=0;o

33、ne:=num;elsif num9 then ten:=1;one:=num-10;elsif num19then ten:=2;one:=num-20;elsif num29then ten:=3;one:=num-30;elsif num39then ten:=4;one:=num-40;elsif num49 then ten:=5;one:=num-50;elsif num59then ten:=6;one:=num-60;elsif num69 then ten:=7;one:=num-70;elsif num79then ten:=8;one:=num-80;elsif num8

34、9 then ten:=9;one:=num-90;end if;t=conv_std_logic_vector(ten,4); oshow1show1show1show1show1show1show1show1show1show1show1show2show2show2show2show2show2show2show2show2show2show2=0000000;end case;end if;end process;end shumaguanxianshi ;動(dòng)態(tài)顯示：library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity shaomiaoxianshi isport(clk,clr:in std_logic;show1:in std_logic_vector(6 downto 0);show2:in std_logic_vector(6 downto 0);show