北航電子電路設(shè)計(jì)數(shù)字部分實(shí)驗(yàn)報(bào)告北航電工電子實(shí)驗(yàn)報(bào)告

1、第12頁(yè) 共12頁(yè)北航電子電路設(shè)計(jì)數(shù)字部分實(shí)驗(yàn)報(bào)告北航電工電子實(shí)驗(yàn)報(bào)告電子電路設(shè)計(jì)數(shù)字部分實(shí)驗(yàn)報(bào)告 學(xué) 院： 姓名： 實(shí)驗(yàn)一 簡(jiǎn)單組合邏輯設(shè)計(jì) 實(shí)驗(yàn)內(nèi)容 描述一個(gè)可綜合的數(shù)據(jù)比較器，比較數(shù)據(jù)a 、b的大小，若相同，則給出結(jié)果1，否則給出結(jié)果0。 實(shí)驗(yàn)仿真結(jié)果 實(shí)驗(yàn)代碼 主程序 module pare(equal,a,b); input7:0 a,b; output equal; assign equal=(ab)?1:0; endmodule 測(cè)試程序 module t; reg7:0 a,b; reg clock,k; wire equal; initial begin a=0; b=0;

2、clock=0; k=0; end always _50 clock = clock; always (posedge clock) begin a0=$random%2; a1=$random%2; a2=$random%2; a3=$random%2; a4=$random%2; a5=$random%2; a6=$random%2; a7=$random%2; b0=$random%2; b1=$random%2; b2=$random%2; b3=$random%2; b4=$random%2; b5=$random%2; b6=$random%2; b7=$random%2; end

3、 initial begin _100000 $stop;end pare m(.equal(equal),.a(a),.b(b); endmodule 實(shí)驗(yàn)二 簡(jiǎn)單分頻時(shí)序邏輯電路的設(shè)計(jì) 實(shí)驗(yàn)內(nèi)容 用always塊和(posedge clk)或(negedge clk)的結(jié)構(gòu)表述一個(gè)1/2分頻器的可綜合模型，觀察時(shí)序仿真結(jié)果。 實(shí)驗(yàn)仿真結(jié)果 實(shí)驗(yàn)代碼 主程序 module fdivision(RESET,F10M,out); input F10M,RESET; output out; reg out; reg7:0 i; always (posedge F10M) if(!RESET) be

4、gin out=0; i=0; end else if(i=2|i=3) begin out=out; i=i+1; end else if(i=5) i=1; else i=i+1; endmodule 測(cè)試程序 timescale 1ns/100ps module division_top; reg F10M,RESET; wire out; always _50 F10M=F10M; initial begin RESET=1; F10M=0; _90 RESET=0; _100 RESET=1; _10000 $stop; end fdivision fdivision(.RESET(

5、RESET),.F10M(F10M),.out(out); endmodule 實(shí)驗(yàn)四 阻塞賦值與非阻塞賦值的區(qū)別 實(shí)驗(yàn)內(nèi)容 比較四種不同的寫(xiě)法，觀察阻塞與非阻塞賦值的區(qū)別。 Blocking： always (posedge clk) begin b=a; c=b; end Blocking1： always (posedge clk) begin c=b; b=a; end Blocking2： always (posedge clk) b=a; always (posedge clk) c=b; non_Blocking： always(posedge clk) begin b=a; c

6、=b; End 實(shí)驗(yàn)仿真結(jié)果 實(shí)驗(yàn)代碼 主程序 module blocking(clk,a,b,c); output3:0 b,c; input3:0 a; input clk; reg3:0 b,c; always (posedge clk) begin b=a; c=b; end endmodule 測(cè)試部分 timescale 1 ns/100 ps include “./blocking.v“ include “./blocking1.v“ include “./blocking2.v“ include “./non_blocking.v“ module pareTop; wire3:

7、0b11,c11,b12,c12,b13,c13,b2,c2; reg3:0a; reg clk; initial begin clk=0; forever_50 clk=clk; end initial begin a=4h3; $display(“%d“,a); _100 a=4h7; $display(“%d“,a); _100 a=4hf; $display(“%d“,a); _100 a=4ha; $display(“%d“,a); _100 a=4h2; $display(“%d“,a); _100 $stop; end blocking blocking(clk,a,b11,c1

8、1); blocking1 blocking1(clk,a,b12,c12); blocking2 blocking2(clk,a,b13,c13); non_blocking non_blocking(clk,a,b2,c2); endmodule 實(shí)驗(yàn)五 用always塊實(shí)現(xiàn)較復(fù)雜的組合邏輯 實(shí)驗(yàn)?zāi)康?運(yùn)用always塊設(shè)計(jì)一個(gè)8路數(shù)據(jù)選擇器。要求：每路輸入數(shù)據(jù)與輸出數(shù)據(jù)均為4位2進(jìn)制數(shù)，當(dāng)選擇開(kāi)關(guān)（至少3位）或輸入數(shù)據(jù)發(fā)生變化時(shí)，輸出數(shù)據(jù)也相應(yīng)地變化。 實(shí)驗(yàn)仿真結(jié)果 實(shí)驗(yàn)代碼 主程序 module alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8); outp

9、ut3:0 out; reg3:0 out; input3:0 a0,a1,a2,a3,a4,a5,a6,a7; input2:0 opcode; always(opcode or a1 or a2 or a3 or a4 or a5 or a6 or a7 or a0) begin case(opcode) 3d0: out=a0; 3d1: out=a1; 3d2: out=a2; 3d3: out=a3; 3d4: out=a4; 3d5: out=a5; 3d6: out=a6; 3d7: out=a7; default:out=4b0000; endcase end endmodul

10、e 測(cè)試程序 timescale 1ns/1ns include “./main5.v“ module alutext; wire3:0 out; reg3:0 a1,a2,a3,a4,a5,a6,a7,a8; reg2:0 opcode; initial begin a1=$random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; repeat(100) begin _100 opcode=$random%8; a1=$

11、random%16; a2=$random%16; a3=$random%16; a4=$random%16; a5=$random%16; a6=$random%16; a7=$random%16; a8=$random%16; end _100 $stop; end alu alu(out,opcode,a1,a2,a3,a4,a5,a6,a7,a8); endmodule 實(shí)驗(yàn)六 在 Verilog HDL中使用函數(shù) 實(shí)驗(yàn)?zāi)康?設(shè)計(jì)一個(gè)帶控制端的邏輯運(yùn)算電路，分別完成正整數(shù)的平方、立方和最大數(shù)為5的階乘運(yùn)算。 任務(wù)1：做出如上邏輯電路設(shè)計(jì)并仿真； 任務(wù)2：考慮去抖情況，對(duì)于感應(yīng)信號(hào)到達(dá)存

12、在毛刺(小于0.5s)，設(shè)計(jì)合適邏輯并剔出。 任務(wù)3：若為節(jié)約能，下一個(gè)燈點(diǎn)亮的同時(shí)將自動(dòng)關(guān)閉上一個(gè)燈，做出如上邏輯設(shè)計(jì)并仿真（僅考慮一個(gè)人的情況）實(shí)驗(yàn)仿真結(jié)果 實(shí)驗(yàn)代碼 主程序 module light_All(clk10,rst,switch,light); input clk10,rst; input2:0switch; output2:0light; reg2:0state1,state2,state3; reg7:0count1,count2,count3; reg2:0count_1,count_2,count_3; reg2:0light; parameter state1_st

13、art=3b000,state2_start=3b000,state3_start=3b000, state1_work=3b001,state2_work=3b001,state3_work=3b001, state1_up=3b010,state2_up=3b010,state3_up=3b010, state1_down=3b011,state2_down=3b011,state3_down=3b011, state1_other=3b100,state2_other=3b100,state3_other=3b100; always(posedge clk10) if(!rst) beg

14、in state1=state1_start; count1=8b0; count_1=3b0; end else if(switch0=b1&;&;count_14) count_1=count_1+1; else case(state1) state1_start: if(switch0=b1) begin state1=state1_up; count1=78; end else begin state1=state1_start; light00) begin count1=count1-1; if(switch0=b0&;&;(state2=3b010|state3=3b010) b

15、egin light0=b0; state1=state1_down; end end else if(switch0=b0) begin state1=state1_down; end else begin state1=state1_other; count1=39; end state1_other: if(switch0=b1) state10) begin count1=count1-1; if(switch0=b0&;&;(state2=3b010|state3=3b010) begin light0=b0; state1=state1_down; end end else sta

16、te1=state1_down; state1_down: begin light0=b0; count_1=3b0; state1=state1_start; end state1_up: begin light0=b1; state1=state1_work; end default: state1=state1_start; endcase always(posedge clk10) if(!rst) begin state2=state2_start; count2=8b0; count_2=3b0; end else if(switch1=b1&;&;count_24) count_

17、2=count_2+1; else case(state2) state2_start: if(switch1=b1) begin state2=state2_up; count2=78; end else begin state2=state2_start; light10) begin count2=count2-1; if(switch1=b0&;&;(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else if(switch1=b0) begin state2=state2_down; e

18、nd else begin state2=state2_other; count2=39; end state2_other: if(switch1=b1) state20) begin count2=count2-1; if(switch1=b0&;&;(state1=3b010|state3=3b010) begin light1=b0; state2=state2_down; end end else state2=state2_down; state2_down: begin light1=b0; count_2=3b0; state2=state2_start; end state2

19、_up: begin light1=b1; state2=state2_work; end default: state2=state2_start; endcase always(posedge clk10) if(!rst) begin state3=state3_start; count3=8b0; count_3=3b0; end else if(switch2=b1&;&;count_34) count_3=count_3+1; else case(state3) state3_start: if(switch2=b1) begin state3=state3_up; count3=

20、78; end else begin state3=state3_start; light20) begin count3=count3-1; if(switch2=b0&;&;(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down; end end else if(switch2=b0) begin state3=state3_down; end else begin state3=state3_other; count3=39; end state3_other: if(switch2=b1) state30) beg

21、in count3=count3-1; if(switch2=b0&;&;(state1=3b010|state2=3b010) begin light2=b0; state3=state3_down; end end else state3=state3_down; state3_down: begin light2=b0; count_3=3b0; state3=state3_start; end state3_up: begin light2=b1; state3=state3_work; end default: state3=state3_start; endcase endmodu

22、le 測(cè)試程序 timescale 100ns/10ns module test_light_All; reg clk10,rst; reg2:0 up,down; wire2:0 swh; wire2:0 light; parameter HALF_PERIOD = 5; always _HALF_PERIOD clk10=clk10; initial begin clk10 = 0; rst = 1; up = 3b000;down = 3b000; _1 rst = 0; _10 rst = 1; _100 up = 3b001; down = 3b000; _500 up = 3b010; down = 3b100; _600 up = 3b011; down = 3b010; _30 up = 3b010; _80 up = 3b011; _900 up = 3b010; down = 3b001; _500 up = 3b; down = 3b001; _600 up =