數(shù)字邏輯設(shè)計及應(yīng)用教學(xué)課件：7-5 同步狀態(tài)機(jī)設(shè)計2

1、7.4 Clocked Synchronous State-Machine Design時鐘同步狀態(tài)機(jī)設(shè)計-217.4 Clocked Synchronous State-Machine DesignConstruct a state/output table (狀態(tài)輸出表) corresponding to the word description.(Optional)Minimize the number of states.State assignment.（choose a set of state variables）Substitute the state-variable com

2、bination into a state/output table to create a transition/output tableChoose a flip-flop type for the state memory.Construct an excitation table ,get excitation equation and output equation.Draw a logic diagram.2Examples for Clocked Synchronous State-Machine DesignTwo simple examplesDesign a 3 bit m

3、odulo-8 binary counter設(shè)計一個3位二進(jìn)制模8計數(shù)器 Design a 110 sequence detector設(shè)計一個110序列檢測器 Examples for state table designExample 1（P558）；Example 2（P566）；Example 3（P570）State diagram design（T-bird tail-light ）The Guessing Game 3Examples for Clocked Synchronous State-Machine DesignTwo simple examplesDesign a 3

4、bit modulo-8 binary counter設(shè)計一個3位二進(jìn)制模8計數(shù)器 Design a 110 sequence detector設(shè)計一個110序列檢測器 Examples for state table designExample 1（P558）；Example 2（P566）；Example 3（P570）State diagram design（T-bird tail-light ）The Guessing Game 4State table design（example 1）(P554)Design a clocked synchronous state machine

5、with two inputs, A and B, and a single output Z that is 1 if: A had the same value at each of the two previous clock ticks, or B has been 1 since the last time that the first condition was true. Otherwise, the output should be 0.設(shè)計一個具有2個輸入（A、B），1個輸出（Z）的時鐘同步狀態(tài)機(jī)，Z為1的條件是：在前2個脈沖觸發(fā)沿上，A的值相同從上一次第1個條件為真起，B的

6、值一直為1500100111000011111006SAB00 01 11 10S*ZState ExpressInitial state INIT0A0A0A1A1A0Got a 0 on AGot a 1 on AA10OK0OK0Two equal,A=0 last OK0A1A10A0A0OK1Two equal,A=1 last OK1OK11OK0OK0OK1BA1因B而OK，A為1 OK1B1A0OK0BOK1OK1因B而OK，A為0 OK0B1A0OK0BOK1OK11OK0OK0OK1BA11、state table 7SAB00 01 11 10S*ZState Expre

7、ss1、state transition tableInitial state INIT0A0A0A1A1A0Got a 0 on A Got a 1 on A A10OK0OK0Two equal,A=0 last OK0A1A10A0A0OK1Two equal,A=1 last OK1OK11OK0OK0 OK1BA1因B而OK，A為1 OK1B1A0OK0BOK1OK1因B而OK，A為0 OK0B1A0OK0BOK1OK11OK0OK0OK1BA12、minimize the number of states OK1 OK1 OK0 OK0OK，A=0OK，=0OK，A=18初始狀態(tài)

8、INITA0A上捕獲一個0 A上捕獲一個1 A1OK，A值為0 OK0OK，A值為1 OK1SAB00 01 11 10S*Z0A0A0A1A10OK0OK0A1A10A0A0OK1OK11OK0OK0 A11A0OK1OK1OK0 OK11、transition table 2、minimize 真的需要一一嘗試嗎？合理的狀態(tài)賦值（P412）最簡單的分解的單熱點的準(zhǔn)單熱點的0001001011101113、 State assignment.從23中選5種一共有 種8!5!3!8!5!3!5種編碼5個狀態(tài)，又有5!種5!共有 94、transition /output tableINITA0

9、A1OK0OK1SAB00 01 11 10S*Z0A0A0A1A10OK0OK0A1A10A0A0OK1OK11OK0OK0 A11A0OK1OK1OK0 OK1 000100100100100100100101110101101101101101110110110110110111111111111111111Q1Q2Q3Q1*Q2*Q3*5 input variables： A,B,Q1,Q2,Q34 output variables ： Z,D1,D2,D3D1 D2 D3transition/excitationtable5、choice the Flip-Flop，get the

10、excitation equation and output equation.Use D Flip-Flop10AB00 01 11 10Z00011000100101110111Q1Q2Q3100100100100100101101101101110110110110101110111111111111111Q1*Q2*Q3*D1 D2 D3Q2Q3AB00 01 11 1000011110Q1=0D2Q2Q3AB00 01 11 1000011110Q1=100001100001101111110000000000000Minimal risk (最小冒險)，未用狀態(tài)初始狀態(tài)Output

11、 equation：Z = Q1Q211Q2Q3AB00 01 11 1000011110Q1=0D20000000000000000Minimal risk最小冒險，未用狀態(tài)初始狀態(tài)Q2Q3AB00 01 11 1000011110Q1=11100001101111110D2 = Q1Q3A + Q1Q3A + Q1Q2BQ2Q3AB00 01 11 1000011110Q1=0D20000dddddddddddd Minimal cost.最小成本，未用狀態(tài)作為無關(guān)項D2 = Q1Q3A + Q3A+ Q2B12D1D2 = Q1Q3A + Q1Q3A + Q1Q2BD1 = Q2Q3 +

12、 Q1思考：最小成本法D1？13D3D3 = Q2Q3A + Q1AD2 = Q1Q3A + Q1Q3A + Q1Q2BD1 = Q2Q3 + Q1激勵方程D3 = Q2Q3A + Q1A思考：最小成本法D3？146、draw the logic circuit（略）D3 = Q2Q3A + Q1AD2 = Q1Q3A + Q1Q3A + Q1Q2BD1 = Q2Q3 + Q1Excitation equationD3 = Q2Q3A + Q1AOutput equation：Z = Q1Q2說明： 最小冒險法 所有未用狀態(tài) “安全”狀態(tài). 最小成本法 所有未用狀態(tài)的下一狀態(tài)作為無關(guān)項 電路的

13、激勵方程簡單，不夠安全.15合理的狀態(tài)賦值選擇復(fù)位時容易進(jìn)入的狀態(tài)作為初始狀態(tài).使每次轉(zhuǎn)移時要發(fā)生改變的狀態(tài)變量數(shù)最小化使一組相關(guān)狀態(tài)中不變化的狀態(tài)變量數(shù)最大化發(fā)現(xiàn)和利用問題描述中的對稱性將狀態(tài)變量組分解為有明確含義的位或字段，相對于狀態(tài)機(jī)的輸入效果或者輸出特性可以使用多于最小值的狀態(tài)變量數(shù)（便于分解）未用狀態(tài)的考慮16Example 2： 1s-counting machine (“1”計數(shù)器)（P566）Design a clocked synchronous state machine with two inputs, X and Y, and one output, Z. The ou

14、tput should be 1 if the number of 1 inputs on X and Y since reset is a multiple of 4, and 0 otherwise.對兩個輸入X和Y同時計數(shù)，當(dāng)1的個數(shù)為4的整數(shù)倍時輸出為1.17Example 2 1s-counting machine （P567）1Got zero 1s S0S0XY 00 01 11 10Zmeaning SS*S1Got one 1s S1S2Got two 1s S2S10S1S2S3Got three 1s S3S20S2S3S0S3S3S0S1S000001111018Exa

15、mple 3：combination lock （P568）a “combination lock” state machine that activates an “unlock” output when a certain binary input sequence is received:Design a clocked synchronous state machine with one input, X, and two outputs, UNLK and HINT. The UNLK output should be 1 if and only if X is 0 and the

16、sequence of inputs received on X at the preceding seven clock ticks was 0110111. The HINT output should be 1 if and only if the current value of X is the correct one to move the machine closer to being in the “unlocked” state (with UNLK = 1).設(shè)計一個具有個輸入和個輸出（和）的時鐘同步狀態(tài)機(jī)當(dāng)且僅當(dāng)為并且前面?zhèn)€脈沖觸發(fā)沿到來時接收到的輸入序列為時，輸出為當(dāng)且

17、僅當(dāng)?shù)漠?dāng)前值是上述序列中的個正確值以使?fàn)顟B(tài)機(jī)逐步接近于“解鎖”（即）狀態(tài)時，輸出為19Example 3：combination lock （P568）注意：輸出是中間過程，應(yīng)用時應(yīng)隱藏207.5 Designing State Machines Using State Diagrams T-bird tail-light(570)LALBLCRARBRCINPUT：LEFT(左轉(zhuǎn))、RIGHT(右轉(zhuǎn))、HAZ（應(yīng)急閃爍) , that requests the tail lights to be operated in hazardmodeall six lights flashing on

18、 and off in unison. a free-running clock signal (時鐘信號)output：LC,LB,LA,RA,RB,RC(控制6個燈亮或滅 可以完全由狀態(tài)控制) 21Step 1: set up enough state with different meaning ;Examples : T-bird tail lights control 22IDLE：全滅L1：左邊1個燈亮L2：左邊2個燈亮L3：左邊3個燈亮R1：右邊1個燈亮R2：右邊2個燈亮R3：右邊3個燈亮LR3：全亮狀態(tài)輸 出直接利用狀態(tài)控制輸出231、Initial state diagram

19、and output table 構(gòu)造狀態(tài)圖IDLE：全滅L1：左邊1個燈亮L2：左邊2個燈亮L3：左邊3個燈亮R1：右邊1個燈亮R2：右邊2個燈亮R3：右邊3個燈亮LR3：全亮IDLEL1LL21L311R1RR21R311LR3H1HLRH+LRLHRRHL24IDLEL1LL21L311R1RR21R311LR3H1HLRH+LRLHRRHL1、構(gòu)造狀態(tài)圖完備性 離開某一狀態(tài)的弧線上的所有轉(zhuǎn)移表達(dá)式的邏輯和為1。無二義性的HRH+RH+RHRHLHLH+LH+L改進(jìn)互斥性 離開某一狀態(tài)的弧線上的任意一對轉(zhuǎn)移表達(dá)式的邏輯積為025Ambiguous(二義性) A state table i

20、s an exhaustive listing of the next states for each state/input combination. No ambiguity is possible. A state diagram contains a set of arcs labeled with transition expressions. Even when there are many inputs, only one transition expression is required per arc. However, when a state diagram is con

21、structed, there is no guarantee that the transition expressions written on the arcs leaving a particular state cover all the input combinations exactly once.26Ambiguous(二義性)In an improperly constructed (ambiguous) state diagram, the next state for some input combinations may be unspecified, which is

22、 generally undesirable, while multiple next states may be specified for others, which is just plain wrong. Thus, considerable care must be taken in the design of state diagrams; 272、狀態(tài)編碼Q2Q1Q00 0 00 0 10 1 10 1 01 0 11 1 11 1 01 0 01、構(gòu)造狀態(tài)圖IDLEL1L2L3R1R2R3LR3合理的狀態(tài)賦值3、得到轉(zhuǎn)移列表 P427Output-Coded State Ass

23、ignment 282、狀態(tài)編碼1、構(gòu)造狀態(tài)圖3、得到轉(zhuǎn)移列表 P427HLRLHRRHL0 0 00 0 00 0 00 0 0H+LR0 0 00 0 11 0 11 0 0IDLEQ2Q1Q0 S轉(zhuǎn)移表達(dá)式S* Q2*Q1*Q0*IDLEL1R1LR329Q2Q1Q0 S轉(zhuǎn)移表達(dá)式S* Q2*Q1*Q0*HLRLHRRHLH+LR0 0 00 0 00 0 00 0 00 0 00 0 11 0 11 0 0IDLEIDLEL1R1LR3L10 0 10 0 1L2LR30 1 11 0 0HRH+RL20 1 10 1 1L3LR30 1 01 0 0HRH+RL30 1 0IDLE0

24、 0 01R11 0 11 0 1R2LR31 1 11 0 0HLH+LR21 1 11 1 1R3LR31 1 01 0 0HLH+LR31 1 0IDLE0 0 01LR31 0 0IDLE0 0 011111Q0* = Q2Q1Q0(LHR)+ Q2Q1Q0(RHL)+ Q2Q1Q0(HR)+ Q2Q1Q0(HL)= Q2Q1Q0 H(LR) + Q2Q1Q0(HR) + Q2Q1Q0(HL)用轉(zhuǎn)移表綜合狀態(tài)機(jī) P57730The Guessing Game猜謎游戲機(jī)（P580）Design a clocked synchronous state machine with four i

25、nputs, G1G4, that are connected to pushbuttons. The machine has four outputs, L1L4, connected to lamps or LEDs located near the like-numbered pushbuttons. There is also an ERR output connected to a red lamp. In normal operation, the L1L4 outputs display a 1-out-of-4 pattern. At each clock tick, the

26、pattern is rotated by one position; the clock frequency is about 4 Hz. Guesses are made by pressing a pushbutton, which asserts an input Gi.When any Gi input is asserted, the ERR output is asserted if the “wrong” pushbutton was pressed, that is, if the Gi input detected at the clock tick does not ha

27、ve the same number as the lamp output that was asserted before the clock tick. Once a guess has been made, play stops and the ERR output maintains the same value for one or more clock ticks until the Gi input is negated, then play resumes. 31The Guessing Game猜謎游戲機(jī)（P580）4個燈（G1G4）由時鐘控制輪流亮起如果按下的按鈕（L1L4

28、）與亮的燈對應(yīng)，則猜對否則，ERR燈亮，表示猜錯輸入：G1、G2、G3、G4（4個按鈕）輸出：L1、L2、L3、L4、ERR（5個燈）狀態(tài)：6個，S1S4對應(yīng)L1L4 Serr對應(yīng)ERR；SOK表示猜對32G1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G44個燈（L1L4）由時鐘控制輪流亮起（沒有按鈕按下）S1L1=1S4L4=1S2L2=1S3L3=133G1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G4S1L1=1S4L4=1S2L2=1S3L3=1如果按下的按鈕與亮的燈對應(yīng)，則猜對（SOK）SOKG1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G4

29、34G1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G4S1L1=1S4L4=1S2L2=1S3L3=1SOKG1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G4否則猜錯（Serr）SerrERR=1G2+G3+G4G1+G3+G4G1+G2+G4G1+G2+G335G1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G4S1L1=1S4L4=1S2L2=1S3L3=1SOKG1G2G3G4G1G2G3G4G1G2G3G4G1G2G3G4SerrERR=1G2+G3+G4G1+G3+G4G1+G2+G4G1+G2+G3G1+G2+G3+G4G1G2G3G4G1G

30、2G3G4G1+G2+G3+G4狀態(tài)轉(zhuǎn)換圖361、狀態(tài)轉(zhuǎn)換圖2、狀態(tài)編碼3、轉(zhuǎn)移列表狀態(tài)S編碼Q2Q1Q0S1S2S3S4SOKSERR0 0 00 0 10 1 10 1 01 0 01 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 X X X X 0 1 X X X 0 0 1 X X 0 0 0 1 X 0 0 0 0 0 0 0 0 0 1用輸出作為狀態(tài)編碼L1 L2 L3 L4 ERR 無關(guān)項的使用L1 L2 L3 L4 ERRP585表7-16P585表7-17P434表7-1737Minimal risk.(P563)Minima