計(jì)算機(jī)組成原理 Lab2 寄存器堆與存儲(chǔ)器及其應(yīng)用

1、計(jì)算機(jī)組成原理Lab2 寄存器堆與存儲(chǔ)器及其應(yīng)用2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 12022/3/222022春季實(shí)驗(yàn)?zāi)繕?biāo)掌握寄存器堆（Register File）和存儲(chǔ)器的功能、時(shí)序及其應(yīng)用熟練掌握數(shù)據(jù)通路和控制器的設(shè)計(jì)和描述方法2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 22022/3/22實(shí)驗(yàn)內(nèi)容1. 寄存器堆（Register File）： - 行為方式參數(shù)化描述寄存器堆（Register File）； - 完成功能仿真clk：時(shí)鐘ra0, rd0：異步讀端口0ra1, rd1：異步讀端口1wa, wd, we：同步寫(xiě)端口ra1ra0RFwdward1rd0clkwe

2、2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 32022/3/22實(shí)驗(yàn)內(nèi)容2. RAM存儲(chǔ)器： - IP例化分布式和塊式16 x 8位單端口RAM； - 完成功能仿真和對(duì)比clk：時(shí)鐘en：總使能we：寫(xiě)使能addr: 讀/寫(xiě)地址din：輸入數(shù)據(jù)dout：輸出數(shù)據(jù)2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 42022/3/22dinaddrRAMenwedoutclk實(shí)驗(yàn)內(nèi)容3. 利用寄存器堆實(shí)現(xiàn)FIFO隊(duì)列：enq, deq：入隊(duì)列和出隊(duì)列使能，假定兩者是互斥的，高電平有效且均要求一次有效僅允許操作一項(xiàng)數(shù)據(jù)in, out：入/出隊(duì)列數(shù)據(jù)full, emp：隊(duì)列滿/空標(biāo)志，在滿或空時(shí)忽略

3、入/出隊(duì)操作an, seg：數(shù)碼管控制信號(hào)，顯示隊(duì)列數(shù)據(jù)clk, rst：時(shí)鐘，復(fù)位2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 52022/3/22enqinFIFOrstoutclkfullempdeqan, seg實(shí)驗(yàn)內(nèi)容3. 利用寄存器堆實(shí)現(xiàn)FIFO隊(duì)列： - 設(shè)計(jì)FIFO隊(duì)列電路的數(shù)據(jù)通路和控制器； - 結(jié)構(gòu)化方式描述數(shù)據(jù)通路，Moore型FSM描述控制器 - 完成功能仿真 - FIFO隊(duì)列電路下載至FPGA Online中測(cè)試2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 62022/3/22寄存器堆也稱(chēng)寄存器文件(Register File)例如，三端口的2m n位寄存器堆1個(gè)

4、寫(xiě)端口WA：寫(xiě)地址WD：寫(xiě)入數(shù)據(jù)WE：寫(xiě)使能2個(gè)讀端口RA0、RA1：讀地址RD0、RD1：讀出數(shù)據(jù)RFRD0RD1WDWARA0RA1WEnnnmmm2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 72022/3/22MUX0123 R0DE R1DE R2DE R3DEMUX0123Decoder0123AERD0RD1WDWARA0RA1WE222nnnnnn三端口4n寄存器堆n2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 82022/3/22寄存器堆-結(jié)構(gòu)/ 三端口84寄存器堆行為描述wire 2:0 wa, ra0, ra1;wire 3:0 wd, rd0, rd1;reg 3:

5、0 regfile0:7;assign rd0 = regfilera0, rd1 = regfilera1;always (posedeg clk) begin if (we) regfilewa Project Manager IP CatalogMemories & Storage Elements RAMs & ROMs Distributed Memory Generator或者 Basic Elements Memory Elements Distributed Memory Generator Memory config Memory Type: Simple Dual Port

6、 RAMRST & Initialization Load COE File同步寫(xiě)端口：a (地址)，d (數(shù)據(jù))，we (寫(xiě)使能)，clk異步讀端口：dpra (地址), dpo (數(shù)據(jù))2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 122022/3/222022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 132022/3/22存儲(chǔ)器IP核-生成方式分布式存儲(chǔ)器IP2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 142022/3/22分布式存儲(chǔ)器IP2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 152022/3/22分布式存儲(chǔ)器IP2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 162022

7、/3/22塊式存儲(chǔ)器IP2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 172022/3/22塊式存儲(chǔ)器IP2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 182022/3/22塊式存儲(chǔ)器IP2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 192022/3/22存儲(chǔ)器IP核-實(shí)例化模板Project Manager display Sources IP SourcesIP dist_mem_gen_0 Instantiation Template dist_mem_gen_0.veodist_mem_gen_0 your_instance_name ( .a(a), / input wire

8、15 : 0 a .d(d), / input wire 11 : 0 d .dpra(dpra), / input wire 15 : 0 dpra .clk(clk), / input wire clk .we(we), / input wire we .dpo(dpo) / output wire 11 : 0 dpo);實(shí)例化模板2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 202022/3/222022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 212022/3/22存儲(chǔ)器IP核-實(shí)例化模板存儲(chǔ)器IP核-COE文件格式An example COE file:; Sample Initi

9、alization file for a 32x16 distributed ROMmemory_initialization_radix = 16;memory_initialization_vector =23f4 0721 11ff ABe1 0001 1 0A 023f4 0721 11ff ABe1 0001 1 0A 023f4 721 11ff ABe1 0001 1 A 023f4 721 11ff ABe1 0001 1 A 0;逗號(hào)或空格分隔每項(xiàng)數(shù)據(jù) (不允許為負(fù)數(shù))2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 222022/3/22/ COE文件格式存儲(chǔ)器IP核-存儲(chǔ)器

10、時(shí)序（一）Read First Mode2022/3/222022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 23Write First Mode2022/3/222022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 24存儲(chǔ)器IP核-存儲(chǔ)器時(shí)序（二）No Change Mode2022/3/222022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 25存儲(chǔ)器IP核-存儲(chǔ)器時(shí)序（三）32132 121321FIFO隊(duì)列-功能要求用三端口84寄存器堆實(shí)現(xiàn)最大長(zhǎng)度為8的FIFO隊(duì)列deqinFIFOrstoutclkfullempenqan, segdeq, enq：出/入隊(duì)列使能 (互斥)，一次有效僅允許操作一

11、項(xiàng)數(shù)據(jù)out, in：出/入隊(duì)列數(shù)據(jù)full, emp：隊(duì)列滿/空，滿/空時(shí)忽略入/出隊(duì)操作an, seg：數(shù)碼管控制信號(hào)，顯示隊(duì)列狀態(tài) 復(fù)位(隊(duì)列空)數(shù)據(jù)1, 2, 3依次入隊(duì)列數(shù)據(jù)1出隊(duì)列2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 262022/3/22FIFO隊(duì)列-邏輯結(jié)構(gòu)隊(duì)列控制單元 LCU (List Control Unit)處理出/入隊(duì)操作，顯示隊(duì)列空/滿狀態(tài)數(shù)碼管顯示單元 SDU (Segment Display Unit)顯示隊(duì)列數(shù)據(jù)內(nèi)容rd0ra0wdward1ra1weRFLCUansegSDU* 省略了clk（100MHz）和 rst（button）enqindeq

12、validoutfullemp(sw6)(sw7)(sw3-0)(led3-0)(led7)(led6)2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 272022/3/22FIFO隊(duì)列-控制單元head：3位，隊(duì)頭，指向出隊(duì)列位置tail：3位，隊(duì)尾，指向入隊(duì)列位置full, empty：各1位，滿和空標(biāo)志valid：8位，有效標(biāo)志，第i位對(duì)應(yīng)Ri狀態(tài)out：4位，出隊(duì)列數(shù)據(jù)R0R1R2R3R4R5R6R7tailheademptyfullvalidoutIDLEDEQUENQUrstenq & !fullRFTin, VT1, TT+1, F(T+1)=H,E0;?2022春_計(jì)算機(jī)組成原

13、理實(shí)驗(yàn)_CS-USTC 282022/3/22apclkSEDGsclkastsptpaps兩級(jí)同步取邊沿2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 292022/3/22FIFO隊(duì)列-異步信號(hào)同步和取邊沿FIFO隊(duì)列-端口定義2022春_計(jì)算機(jī)組成原理實(shí)驗(yàn)_CS-USTC 302022/3/22module fifo (input clk, rst, /時(shí)鐘（上升沿有效）、同步復(fù)位（高電平有效）input enq, /入隊(duì)列使能，高電平有效input 3:0 in,/入隊(duì)列數(shù)據(jù)input deq,/出隊(duì)列使能，高電平有效output 3:0 out, /出隊(duì)列數(shù)據(jù)output 2:0 an,/數(shù)碼管選擇output 3:0 seg/數(shù)碼管數(shù)據(jù));deqinFIFOrstoutclkfullempe