教學課件第8周

1、北京理工大學微電子電路基礎(chǔ)8 數(shù)字電路Digital IC technologies and logic circuit families7 Digital circuit Design : An Overview7 Digital circuit Design : An OverviewCMOSReplaced NMOS (much lower power dissipation)Small size, ease of fabricationChannel length has decreased significantly (as short as 0.04 m or shorter) L

2、ow power dissipation than bipolar logic circuits ( can pack more) .High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar) High levels of integration for both logic and memory circuits.Dynamic logic to further reduce power dissipation and to increase speed

3、performance .BipolarTTL(Transistor-transistor logic) had been used for many years .ECL(Emitter Coupled Logic) : basic element is the differential BJT pair.BiCMOS: combines the high speed of BJTs with low power dissipation of CMOS .GaAs: for very high speed due to the high carrier mobility . Has not

4、demonstrated its potential commercially .7 Digital circuit Design : An OverviewFeatures to be ConsideredInterface circuits for different familiesLogic flexibilitySpeedComplex functionsNoise immunityTemperaturePower dissipationCost7 Digital circuit Design : An OverviewThe static operation of a logic-

5、circuit family is characterized by the voltage-transfer characteristic (VTC) of its basic inverter.7 Logic circuit characterizationFor ideal inverterTypical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.Low-to-high Propagation delayHigh

6、-to-lowPropagation delayDefinitions of propagation delays and switching times of the logic inverter Propagation delay7 Digital circuit Design : An OverviewPower dissipation per gate and per memory cell should be kept as low as possible, particularly the case for portable, battery-operated equipment.

7、Static : the power the gate dissipates in the absence of switching action.Dynamic: the power occurs only when the gate is switched. Power dissipation Two types in a logic gate:7 Digital circuit Design : An Overviewideal condition: high-speed low power dissipationlower power dissipation can be achiev

8、ed by decreasing supply voltage, supply current or both decrease of current-driving capability of the gate. Delay-power product is defined as:Delay-power product7 Digital circuit Design : An OverviewConflict to each otherdigital VLSI circuits: minimization of silicon area per logic gate.area reducti

9、on occurs in three different ways:processing technologydesign techniqueschip layoutSmall area - reducing parasitic capacitances - increasing speedLower current driving capability - Increasing delay Silicon area7 Digital circuit Design : An OverviewFan-in of a gate : number of inputs .Fan-out : maxim

10、um number of similar gates that a gate can drive while remaining within guaranteed specifications.Fan-In and Fan -Out7 Digital circuit Design : An OverviewThe CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion .7 Design and performance analysis of the

11、CMOS inverteris connected to through of pull-up Is connected to ground through of pull-down In static state, no direct-current path exist between Vdd and ground and the static current and the static power dissipation are both zero.7 Design and performance analysis of the CMOS inverterThe voltage tra

12、nsfer characteristic (VTC) of the CMOS inverter when QN and QP are matched 7 Design and performance analysis of the CMOS inverter7 Design and performance analysis of the CMOS inverterforThat is Devices are designed to have equal transconductance parameters. Matching7 Design and performance analysis

13、of the CMOS inverterMatching the conducting parameters provides transistors(inverter) with equal current driving capacity in pull-up and pull-down.Typically Vt=0.1-0.2Vddcapacity in pull-up and pull-downTherefore with matching transistors the inverter has the same propagation delay When7 Design and

14、performance analysis of the CMOS inverterC the sum of internal capacitance of MOSFETS Qn and Qp. The total value of C is given by Equivalent capacitance between the inverter output node and ground7 Design and performance analysis of the CMOS inverterEquivalent circuits for determining the propagatio

15、n delays 7 Design and performance analysis of the CMOS inverterVI goes high and QN discharges C from VDD to 0 7 Design and performance analysis of the CMOS inverterAt t=0, QN will be saturated At t= , QN will be in triode regionQN is in saturation mode but when below VDD Vt, Then goes into the triod

16、e region.For the period from t=0 to t=Discharge current iDN is obtained The discharge interval computed from The average discharge current is for7 Design and performance analysis of the CMOS inverterMatching W/L Kp Kn gives equalReduce C (change length, minimizing wiring and parasitic capacitance)La

17、rge transconductance parameters Kp,n Large W/L ratioLarge supply voltage Vdd (process technology and general trend in reducing Vdd) 7 Design and performance analysis of the CMOS inverterRepresentation of a three- input CMOS logic gate 7 CMOS Logic Gate CircuitsTransistors can be thought as a switch

18、controlled by its gate signalNMOS switch closes when switch control input is highNMOS Transistors in Series/Parallel Connection7 CMOS Logic Gate CircuitsPMOS Transistors in Series/Parallel Connection7 CMOS Logic Gate CircuitsThreshold Drops7 CMOS Logic Gate CircuitsComplementary CMOS Logic Style7 CM

19、OS Logic Gate CircuitsExample Gate: NAND7 CMOS Logic Gate CircuitsExample Gate: NOR7 CMOS Logic Gate CircuitsComplex CMOS Gate7 CMOS Logic Gate CircuitsConstructing a Complex Gate7 CMOS Logic Gate CircuitsProperties of Complementary CMOS Gates Snapshot7 CMOS Logic Gate CircuitsCMOS Properties7 CMOS Logic Gate CircuitsFull rail-to-rail swing; high noise marginsLogic levels not dependent upon the re