數(shù)字邏輯設(shè)計(jì)及應(yīng)用-18課件

1、Chapter 7 Sequential Logic Design Principles( 時(shí)序邏輯設(shè)計(jì)原理 ) Latches and Flip-Flops (鎖存器和觸發(fā)器 ) Clocked Synchronous State-Machine Analysis (同步時(shí)序分析) Clocked Synchronous State-Machine Design (同步時(shí)序設(shè)計(jì))Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)1Chapter 7 Sequential Logic DesReview of Last Class (內(nèi)容回顧)時(shí)序

2、邏輯電路輸出取決于輸入和過去狀態(tài)電路特點(diǎn)：有反饋回路、有記憶元件雙穩(wěn)態(tài)元件QQ_L0態(tài) 和 1態(tài)穩(wěn)態(tài)穩(wěn)態(tài)亞穩(wěn)態(tài)注意：亞穩(wěn)態(tài)特性Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)2Review of Last Class (內(nèi)容回顧)時(shí)序邏時(shí)序邏輯電路輸出取決于輸入和過去狀態(tài)電路特點(diǎn)：有反饋回路、有記憶元件雙穩(wěn)態(tài)元件QQ_L0態(tài) 和 1態(tài)如何加入控制信號(hào)？QQLRSReview of Last Class (內(nèi)容回顧)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)3時(shí)序邏輯電路QQ_L0態(tài) 和 1態(tài)如

3、何加入控制信號(hào)？QQLS - R latch（鎖存器）S_L = R_L = 11 11 00 10 0S_L R_L維持原態(tài)0 11 0 1* 1*Q QLS-R鎖存器功能表電路維持原態(tài)S_L = 1, R_L = 0Q = 0, QL = 1S_L = 0, R_L = 1Q = 1, QL = 0S_L = R_L = 0Q=QL=1，不定狀態(tài)QQLS_LR_LSR清0置1不定S QR Q邏輯符號(hào)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)4S - R latch（鎖存器）S_L = R_L = 11S-R Latch with Ena

4、ble(具有使能端的S-R鎖存器)SRCQQLS_LR_L0 X X1 0 01 0 11 1 01 1 1C S R維持原態(tài)維持原態(tài)0 11 0 1* 1*Q QL 功能表(1). C = 0時(shí)：維持原態(tài)(2). C = 1時(shí)：與S-R鎖存器相似注意：當(dāng)S=R=1時(shí)，若C由10， 則下一狀態(tài)不可預(yù)測(cè)。 邏 輯 符 號(hào)SCRQQ 又稱“時(shí)鐘S-R鎖存器”Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)5S-R Latch with Enable(具有使能端的S0 X X1 0 01 0 11 1 01 1 1C S R維持原態(tài)維持原態(tài)0 11 0

5、 1* 1*Q QL時(shí)鐘S-R鎖存器時(shí)序圖QSRC動(dòng)作特點(diǎn)：輸入信號(hào)在時(shí)鐘（使能端）有效期間，都能直接改變觸發(fā)器的狀態(tài)。Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)60 X XC S R維持原態(tài)Q QL時(shí)鐘S-RD Latch (D鎖存器)When D = 1，Q = 1C = 0，QQLSRDC數(shù)據(jù)輸入端控制端ENABLECLK輸出狀態(tài)保持不變輸出隨輸入狀態(tài)而改變C = 1，When D = 0，Q = 0Q = DTransparent Latch(透明鎖存器)C D Q QL1 0 0 11 1 1 00 X 保 持D鎖存器功能表D Q

6、C Q邏輯符號(hào)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)7D Latch (D鎖存器)When D = 1，Q = 1Level-Sensitive D LatchSR latch requires careful design to ensure SR=11 never occursD latch relieves designer of that burdenInserted inverter ensures R always opposite of SDQQCD latch symbolR1S1DCD latchQSR8Level-S

7、ensitive D LatchSR latcLevel-Sensitive D LatchR1S1DCD latchQSR10DCS1R1Q101010109Level-Sensitive D LatchR1S1DCD特征方程：Qn+1 = D（C=1）01D=1D=0D=1D=001D01Qn+1狀態(tài)轉(zhuǎn)移真值表Function Description of a D Latch(D鎖存器的功能描述)狀態(tài)圖Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)10特征方程：Qn+1 = D（C=1）01D=1D=0D=1Dtpw(min)0 00 11

8、 01 1S R維持原態(tài)0 11 0 0* 0*Q QLSRQtpLH(SQ)tpHL(RQ)SRQQL傳播延遲最小脈沖寬度Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)Figure 7-811tpw(min)0 0S R維持原態(tài)Q QLSRQtQDCtpLH(CQ)tpHL(DQ)tpLH(DQ)tpHL(CQ)在C的下降沿附近有一個(gè)時(shí)間窗這段時(shí)間內(nèi)D輸入一定不能變化tsetupSetup Time(建立時(shí)間)tholdHold Time(保持時(shí)間)Timing Parameters for a D Latch(D鎖存器的時(shí)序圖)Digita

9、l Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)12QDCtpLH(CQ)tpHL(DQ)tpLH(DQ)tpHD Latch with CMOS Transmission Gate(利用CMOS傳輸門的D鎖存器)QLQTGTGDCENEN_LABCMOS傳輸門TGDigital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)13D Latch with CMOS TransmissionQLQTG1TG2DCC = 0 TG1 斷開 TG2 連通保持原態(tài)Q_LQDigital Logic Design and Applic

10、ation (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)D Latch with CMOS Transmission Gate(利用CMOS傳輸門的D鎖存器)14QLQTG1TG2DCC = 0保持原態(tài)Q_LQDigitaQLQTG1TG2DCC = 1 TG1 連通 TG2 斷開 QL = D Q = DC D Q QL1 0 0 11 1 1 00 X 保 持功能表Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)D Latch with CMOS Transmission Gate(利用CMOS傳輸門的D鎖存器)15QLQTG1TG2DCC = 1C D Q QL

11、1 D QC QD QC QD QC QD QC QDIN3:0WRDOUT3:0RDApplicationsof Latches(鎖存器的應(yīng)用)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)16D QD QD QD Q DQ CXYCISiCi+1XiYiCiSCOCLK暫存X YCI COSCi+1SiXi YiCi時(shí)鐘控制串行輸入、串行輸出注意：時(shí)鐘同步再談串行輸入加法器的實(shí)現(xiàn)Applicationsof Latches(鎖存器的應(yīng)用)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)17Q

12、DXSiXiSCLK暫存X YStoring One Bit Example Requiring Bit StorageFlight attendant call buttonPress call: light turns onStays on after button releaseda3.2BitStorageBlue lightCallbuttonCancelbutton1. Call button pressed light turns onBitStorageBlue lightCallbuttonCancelbutton2. Call button released light s

13、tays on1118Storing One Bit Example Requi19Storing One Bit Flip-FlopsExample Requiring Bit StoragePress cancel: light turns offStays off after button releasedLogic gate circuit to implement this?QCallCancelDoesnt work. Q=1 when Call=1, but doesnt stay 1 when Call returns to 0Need some form of “feedba

14、ck” in the circuit3.2BitStorageBlue lightCallbuttonCancelbutton3. Cancel button pressed light turns off01919Storing One Bit Flip-Flops20First attempt at Bit StorageNeed some sort of feedbackDoes circuit below do what we want?QSt2020First attempt at Bit StorageFirst attempt at Bit StorageNo: Once Q b

15、ecomes 1 (when S=1), Q stays 1 forever no value of S can bring Q back to 0101010QtS0t1QS00t1QS11t1QS11t0QS10t0QS021First attempt at Bit StorageNoBit Storage Using an SR LatchQS (set)SR latchR (reset)Does the circuit to the right, with cross-coupled NOR gates, do what we want?Yes! How did someone com

16、e up with that circuit? Maybe just trial and error, a bit of insight.22Bit Storage Using an SR LatchQBit Storage Using an SR Latch001R=1S=0tQ1010RS10t10Q100101tQS=0R=0 t QS=1R=0011 t QR=0S=010100011X0Recall NOR23Bit Storage Using an SR Latch024Example Using SR Latch for Bit StorageSR latch can serve

17、 as bit storage in previous example of flight-attendant call buttonCall=1 : sets Q to 1Q stays 1 even after Call=0Cancel=1 : resets Q to 0BitStorageBlue lightCallbuttonCancelbutton2424Example Using SR Latch for B25Example Using SR Latch for Bit StorageBut, theres a problem.RSQCallbuttonBlue lightCan

18、celbutton1012525Example Using SR Latch for B26Problem with SR LatchProblemIf S=1 and R=1 simultaneously, we dont know what value Q will take2626Problem with SR LatchProblem27Problem with SR LatchProblemIf S=1 and R=1 simultaneously, we dont know what value Q will takeQ may oscillate. Then, because o

19、ne path will be slightly longer than the other, Q will eventually settle to 1 or 0 but we dont know which. Known as a race condition. 2727Problem with SR LatchProblemProblem with SR LatchDesigner might try to avoid problem using external circuitCircuit should prevent SR from ever being 11But 11 can

20、occur due to different path delaysRCnclCallSSR latchQCallbuttonCancelbuttonExternal circuit28Problem with SR LatchDesigner Problem with SR LatchAssume 1 ns delay per gate. The longer path from Call to R than from Call to S causes SR=11 for short time could be long enough to cause oscillation10101010

21、CallCnclSRSR = 112 ns29Problem with SR LatchAssume 1 Problem with SR LatchGlitch can also cause undesired set or resetRCnclCallSSR latchQCallbuttonCancelbuttonExternal circuitSuppose this wire has 4 ns delay30Problem with SR LatchGlitch caProblem with SR Latch10101010CallCnclSRSR = 01(undesiredglitc

22、h)4 ns31Problem with SR Latch10101010CSolution: Level-Sensitive SR LatchAdd enable input “C” Only let S and R change when C=0Ensure circuit in front of SR never sets SR=11, except briefly due to path delaysSet C=1 after time for S and R to be stableWhen C becomes 1, the stable S and R value passes t

23、hrough the two AND gates to the SR latchs S1 R1 inputs. R1S1SCRLevel-sensitive SR latchQSCQQRLevel-sensitive SR latch symbol32Solution: Level-Sensitive SR LSolution: Level-Sensitive SR LatchR1S1SCallCnclCClkRLevel-sensitive SR latchQGlitch on R (or S) doesnt affect R1 (or (S1)0101S1R1CorrectValues w

24、henenabled10101010CallCnclSR10C33Solution: Level-Sensitive SR LFlip-Flops (觸發(fā)器)Change its outputs only at the Rising or Falling Edge of a controlling CLK signal.(只在時(shí)鐘信號(hào)的邊沿改變其輸出狀態(tài))CLKPositive-EdgeRising-Edge(正邊沿上升沿)Negative-EdgeFalling-Edge(負(fù)邊沿下降沿)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)34Fli

25、p-Flops (觸發(fā)器)Change its outFlip-Flops (觸發(fā)器)從功能上分D觸發(fā)器、S-R觸發(fā)器、J-K觸發(fā)器、T觸發(fā)器從結(jié)構(gòu)上分主從結(jié)構(gòu)觸發(fā)器、邊沿觸發(fā)器其他類型觸發(fā)器帶使能端的觸發(fā)器、掃描觸發(fā)器施密特觸發(fā)器、單穩(wěn)態(tài)觸發(fā)器Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)35Flip-Flops (觸發(fā)器)從功能上分Digital LD Flip-FlopFlip-flop: Bit storage that stores on clock edgeOne design master-servantClk = 0 maste

26、r enabled, loads D, appears at Qm. Servant disabled.Clk = 1 Master disabled, Qm stays same. Servant latch enabled, loads Qm, appears at Qs. Thus, value at D (and hence at Qm) when Clk changes from 0 to 1 gets stored into servant 36D Flip-FlopFlip-flop: Bit storD Flip-FlopClkrising edgesNote: Hundred

27、s of different flip-flop designs existD latchmasterD latchservantDDmDsCsQmQsQsQQCmClkD flip-flopClkD/DmQm/DsCmCsQsCan we design bit storage that only stores a value on the rising edge of a clock signal?37D Flip-FlopClkrising edgesNoteD Flip-FlopSolves problem of not knowing through how many latches

28、a signal travels when C=1 In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_BWhy? Because on rising edge of Clk, all four flip-flops are loaded simultaneously then all four no longer pay attention to their input, until the next rising edge. Doesnt matter how long Clk is

29、 1. 38D Flip-FlopSolves problem of n39D Flip-FlopTwo latches inside each flip-flopD1Q1D2Q2D3Q3D4Q4YClkClk_AClk_B113939D Flip-FlopTwo latches insidD Flip-Flops (D觸發(fā)器)D QC QD QC QQQLDCLKCLK=0時(shí)，CLK=1時(shí)，主鎖存器工作，接收輸入信號(hào) Qm = D從鎖存器不工作，輸出 Q 保持不變主鎖存器不工作，Qm 保持不變從鎖存器工作，將 Qm 傳送到輸出端Master(主)Slave (從)Qm 主從結(jié)構(gòu)Digital

30、 Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)40D Flip-Flops (D觸發(fā)器)D QD DCLKQQmD QC QD QC QQQLDCLKQmDigital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)41DCLKQQmD QD QQDCLKQmDigiDCLKQD CLK Q QL0 0 11 1 0X 0 保 持X 1 保 持功能表D Q CLK Q邏輯符號(hào)表示邊沿觸發(fā)特性Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)42DCLKQD CLK Q QL0 D

31、CLKQDCLKQD鎖存器D觸發(fā)器 邊沿有效電平有效Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)43DCLKQDCLKQD鎖存器D觸發(fā)器 邊沿有效電平利用觸發(fā)器作為移位寄存器（圖1）思考：能否將觸發(fā)器改為鎖存器(圖2)DCLKQ1QD QC QD QC QQDCLKlatchlatch（圖2）Q1D Q CLK QD Q CLK QQDCLKF / FF / F（圖1）Q1Applications of Flip-Flops (觸發(fā)器的應(yīng)用)Digital Logic Design and Application (數(shù)字邏輯設(shè)計(jì)及應(yīng)用)44利

32、用觸發(fā)器作為移位寄存器（圖1）思考：能否將觸發(fā)器改為鎖存器45Problem with Level-Sensitive D LatchD latch still has problem (as does SR latch)When C=1, through how many latches will a signal travel?Depends on how long C=14545Problem with Level-SensitiveProblem with Level-Sensitive D LatchClk_A signal may travel through multiple l

33、atchesClk_B signal may travel through fewer latches11?1?1?D1Q1D2Q2D3Q3D4C4C3C2C1Q4YClkClk_AClk_B46Problem with Level-Sensitive DProblem with Level-Sensitive D LatchR2S2D2C2D latchQ2D4C4Q4R1S1D1C1ClkD latchQ101010110011001(a)D3C3Q30147Problem with Level-Sensitive DProblem with Level-Sensitive D Latch

34、(c)ClkD1Q1/D2S2R2Q2Short clockQ1 doesnt change(b)ClkD1Q1/D2S2R2Q22nd latch setLong clock48Problem with Level-Sensitive DFlight-Attendant Call Button Using D Flip-FlopD flip-flop will store bitInputs are Call, Cancel, and present value of D flip-flop, QTruth table shown belowDQQClkCallbuttonCancelbut

35、tonBluelightComb.CircuitCallCnclQDL49Flight-Attendant Call Button UFlight-Attendant Call Button Using D Flip-FlopPreserve value: if Q=0, make D=0; if Q=1, make D=1Cancel - make D=0Call - make D=1Lets give priority to Call - make D=1Circuit derived from truth table, using combinational logic design processDQQClkCallbuttonBluelightCallCancelQCancelbutton50Flight-Att