第十三講微處理器接口芯片設(shè)計(jì)實(shí)例-可編程并行接口芯片設(shè)計(jì)實(shí)例課件

第十三講

微處理器接口芯片設(shè)計(jì)實(shí)例

--可編程并行接口芯片設(shè)計(jì)實(shí)例曲阜師范大學(xué)電氣信息與自動(dòng)化學(xué)院第十三講

微處理器接口芯片設(shè)計(jì)實(shí)例

--可編程并行接1本講主要內(nèi)容8255的引腳及內(nèi)部結(jié)構(gòu)8255的工作方式及其控制字8255的結(jié)構(gòu)設(shè)計(jì)8255芯片的VHDL語言描述8255芯片VHDL語言描述模塊仿真本講主要內(nèi)容8255的引腳及內(nèi)部結(jié)構(gòu)28255的引腳及內(nèi)部結(jié)構(gòu)外部引腳8255的引腳及內(nèi)部結(jié)構(gòu)外部引腳3內(nèi)部結(jié)構(gòu)內(nèi)部結(jié)構(gòu)4控制字控制字5第十三講微處理器接口芯片設(shè)計(jì)實(shí)例-可編程并行接口芯片設(shè)計(jì)實(shí)例課件6LIBRARYIEEE;USEIEEE.STD_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPPIIS使用庫(kù)LIBRARYIEEE;使用庫(kù)7PORT(RESET,RD,WR,CS,A0,A1:INSTD_LOGIC;PA:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PB:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PCL:INOUTTD_LOGIC_VECTOR(3DOWNTO0);PCH:INOUTSTD_LOGIC_VECTOR(3DOWNTO0);D:INOUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDPPI;實(shí)體描述PORT(實(shí)體描述8構(gòu)造體描述ARCHITECTURERTLOFPPIISSIGNALINTERNAL_BUS_OUT:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALINTERNAL_BUS_IN:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALST,AD,FLAG:STD_ULOGIC_VECTOR(1DOWNTO0);SIGNALCTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALPA_LATCH,Pb_LATCH,Pc_LATCH:CTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);構(gòu)造體描述ARCHITECTURERTLOFPPII9讀進(jìn)程BEGINPROCESS(RD,CS)Beginst<=cttreg(3)&cttreg(0);if(cs=‘0’andrd=‘0’)thenif(a0=‘0’anda1=‘0’andcttreg(4)=‘1’)theninternal_bus_in<=pa;elsif(a0=‘0’anda1=‘0’andcttreg(1)=‘1’)theninternal_bus_in<=pb;讀進(jìn)程BEGIN10elsif(a0=‘0’anda1=‘1’andst=“01”)theninternal_bus_in(3downto0)<=pcl(3downto0);elsif(a0=‘0’anda1=‘1’andst=“10”)theninternal_bus_in(7downto4)<=pch(3downto0);elsif(a0=‘0’anda1=‘1’andst=“11”andctrreg(7)=‘1’)theninternal_bus_in（3downto0）<=pcl(3downto0);internal_bus_in（7downto4）<=pch(3downto0);elsif(a0=‘0’anda1=‘1’andst=11process(cs,wr,reset)variablectrregF:std_ulogic;variablebctrreg_v:std_ulogic_vector(3downto0);beginif(cs='0'andwr='0')thenad<=a1&a0;ctrregF:=d(7);iternal_bus_out<=d;endif;process(cs,wr,reset)12if(reset='1')thenpa_latch<="00000000";pb_latch<="00000000";pc_latch<="00000000";ctrreg<="10011011"bctrreg_v:="0000";ctrregF:='0';if(reset='1')then13elsif(wr'eventandwr='1')thenif(ctrregF='1'andad="11"andcs='0')thenctrreg<=internal_bus_out;elsif(ctrreg(7)='1'andad="00"andcs='0')thenpa_latch<=internal_bus_out;elsif(ctrreg(7)='1'andad="01"andcs='0')thenpb_latch<=internal_bus_out;elsif(ctrreg(7)='1'andad="10"andcs='0')thenpc_latch<=internal_bus_out;elsif(wr'eventandwr='1')then14

elsif(ctrregF='0'andad="11"andcs='0')thenbctrreg:=internal_bus_out(3downto0);casebctrreg_viswhen"0000"=>pc_latch(0)<='0';when"0010"=>pc_latch(1)<='0';when"0100"=>pc_latch(2)<='0';when"0110"=>pc_latch(3)<='0';when"1000"=>pc_latch(4)<='0';when"1010"=>pc_latch(5)<='0';when"1100"=>pc_latch(6)<='0';when"1110"=>pc_latch(7)<='0';

elsif(ctrregF='0'andad="11"15when"0001"=>pc_latch(0)<='1';when"0011"=>pc_latch(1)<='1';when"0101"=>pc_latch(2)<='1';when"0111"=>pc_latch(3)<='1';when"1001"=>pc_latch(4)<='1';when"1011"=>pc_latch(5)<='1';when"1101"=>pc_latch(6)<='1';when"1111"=>pc_latch(7)<='1';whenothers=>flag<="11";endcase;when"0001"=>pc_latch(0)<='1';16endif;endif;endprocess;endif;17process(pa_latch)beginif(ctrreg(4)='0')thenpa<=pa_latch;elsepa<="ZZZZZZZZ";endif;endprocess;process(pa_latch)18process(pb_latch)beginif(ctrreg(1)='0')thenpb<=pb_latch;elsepa<="ZZZZZZZZ";endif;endprocess;process(pb_latch)19process(pc_latch)beginif(ctrreg(0)='0')thenpcl<=pc_latch(3downto0);elsepcl<="ZZZZ";endif;endprocess;process(pc_latch)20process(pc_latch)beginif(ctrreg(3)='0')thenpch<=pc_latch(7downto4);elsepch<="ZZZZ";endif;endprocess;endrtl;process(pc_latch)218255構(gòu)造體設(shè)計(jì)鎖存器Pa_latcha口輸出鎖存器Pb_latchb口輸出鎖存器Pcl_latchc口低4位輸出鎖存器Pch_latchc口高4位輸出鎖存器Ctrreg方式控制字寄存器Bctrreg選擇標(biāo)志寄存器三態(tài)緩沖器d、pa、pb、pc組合邏輯電路8255構(gòu)造體設(shè)計(jì)鎖存器22Endif;Elseinternal_bus_in<=“ZZZZZZZZ”;Endif;D<=internal_bus_in;Endprocess;讀進(jìn)程Endif;23Std_logic_1164定義了一個(gè)9值模型，每個(gè)值為邏輯電平（0、1與未知）與強(qiáng)度（強(qiáng)制、弱、高阻、未定和無關(guān)）的組合，其中高阻、未定和無關(guān)只有一個(gè)電平值（未知）。其定義如下：

TypeStd_Ulogicis(

'U',－－未定(Uninitialized)

'X',－－強(qiáng)制未知(ForcingUnknown)

'0',－－強(qiáng)制0(Forcing0)

'1',－－強(qiáng)制1(Forcing1)

'Z',－－高阻(HighImpedance)

'W',－－弱未知(WeakUnknown)

'L',－－弱0(Weak0)

'H',－－弱1(Weak1)

'-'－－無關(guān)(Don'tCare)

);Std_logic_1164定義了一個(gè)9值模型，每個(gè)值為邏輯24第十三講

微處理器接口芯片設(shè)計(jì)實(shí)例

--可編程并行接口芯片設(shè)計(jì)實(shí)例曲阜師范大學(xué)電氣信息與自動(dòng)化學(xué)院第十三講

微處理器接口芯片設(shè)計(jì)實(shí)例

--可編程并行接25本講主要內(nèi)容8255的引腳及內(nèi)部結(jié)構(gòu)8255的工作方式及其控制字8255的結(jié)構(gòu)設(shè)計(jì)8255芯片的VHDL語言描述8255芯片VHDL語言描述模塊仿真本講主要內(nèi)容8255的引腳及內(nèi)部結(jié)構(gòu)268255的引腳及內(nèi)部結(jié)構(gòu)外部引腳8255的引腳及內(nèi)部結(jié)構(gòu)外部引腳27內(nèi)部結(jié)構(gòu)內(nèi)部結(jié)構(gòu)28控制字控制字29第十三講微處理器接口芯片設(shè)計(jì)實(shí)例-可編程并行接口芯片設(shè)計(jì)實(shí)例課件30LIBRARYIEEE;USEIEEE.STD_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPPIIS使用庫(kù)LIBRARYIEEE;使用庫(kù)31PORT(RESET,RD,WR,CS,A0,A1:INSTD_LOGIC;PA:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PB:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);PCL:INOUTTD_LOGIC_VECTOR(3DOWNTO0);PCH:INOUTSTD_LOGIC_VECTOR(3DOWNTO0);D:INOUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDPPI;實(shí)體描述PORT(實(shí)體描述32構(gòu)造體描述ARCHITECTURERTLOFPPIISSIGNALINTERNAL_BUS_OUT:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALINTERNAL_BUS_IN:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALST,AD,FLAG:STD_ULOGIC_VECTOR(1DOWNTO0);SIGNALCTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);SIGNALPA_LATCH,Pb_LATCH,Pc_LATCH:CTRREG:STD_ULOGIC_VECTOR(7DOWNTO0);構(gòu)造體描述ARCHITECTURERTLOFPPII33讀進(jìn)程BEGINPROCESS(RD,CS)Beginst<=cttreg(3)&cttreg(0);if(cs=‘0’andrd=‘0’)thenif(a0=‘0’anda1=‘0’andcttreg(4)=‘1’)theninternal_bus_in<=pa;elsif(a0=‘0’anda1=‘0’andcttreg(1)=‘1’)theninternal_bus_in<=pb;讀進(jìn)程BEGIN34elsif(a0=‘0’anda1=‘1’andst=“01”)theninternal_bus_in(3downto0)<=pcl(3downto0);elsif(a0=‘0’anda1=‘1’andst=“10”)theninternal_bus_in(7downto4)<=pch(3downto0);elsif(a0=‘0’anda1=‘1’andst=“11”andctrreg(7)=‘1’)theninternal_bus_in（3downto0）<=pcl(3downto0);internal_bus_in（7downto4）<=pch(3downto0);elsif(a0=‘0’anda1=‘1’andst=35process(cs,wr,reset)variablectrregF:std_ulogic;variablebctrreg_v:std_ulogic_vector(3downto0);beginif(cs='0'andwr='0')thenad<=a1&a0;ctrregF:=d(7);iternal_bus_out<=d;endif;process(cs,wr,reset)36if(reset='1')thenpa_latch<="00000000";pb_latch<="00000000";pc_latch<="00000000";ctrreg<="10011011"bctrreg_v:="0000";ctrregF:='0';if(reset='1')then37elsif(wr'eventandwr='1')thenif(ctrregF='1'andad="11"andcs='0')thenctrreg<=internal_bus_out;elsif(ctrreg(7)='1'andad="00"andcs='0')thenpa_latch<=internal_bus_out;elsif(ctrreg(7)='1'andad="01"andcs='0')thenpb_latch<=internal_bus_out;elsif(ctrreg(7)='1'andad="10"andcs='0')thenpc_latch<=internal_bus_out;elsif(wr'eventandwr='1')then38

elsif(ctrregF='0'andad="11"andcs='0')thenbctrreg:=internal_bus_out(3downto0);casebctrreg_viswhen"0000"=>pc_latch(0)<='0';when"0010"=>pc_latch(1)<='0';when"0100"=>pc_latch(2)<='0';when"0110"=>pc_latch(3)<='0';when"1000"=>pc_latch(4)<='0';when"1010"=>pc_latch(5)<='0';when"1100"=>pc_latch(6)<='0';when"1110"=>pc_latch(7)<='0';

elsif(ctrregF='0'andad="11"39when"0001"=>pc_latch(0)<='1';when"0011"=>pc_latch(1)<='1';when"0101"=>pc_latch(2)<='1';when"0111"=>pc_latch(3)<='1';when"1001"=>pc_latch(4)<='1';when"1011"=>pc_latch(5)<='1';when"1101"=>pc_latch(6)<='1';when"1111"=>pc_latch(7)<='1';whenothers=>flag<="11";endcase;when"0001"=>pc_latch(0)<='1';40endif;endif;endprocess;endif;41process(pa_latch)beginif(ctrreg(4)='0')thenpa<=pa_latch;elsepa<="ZZZZZZZZ";endif;endprocess;process(pa_latch)42process(pb_latch)beginif(ctrreg(1)='0')thenpb<=pb_latch;elsepa<="ZZZZZZZZ";endif;endprocess;process(pb_latch)43process(pc_latch)beginif(ctrreg(0)='0')thenpcl<=pc_latch(3downto0);els