組合邏輯電路設(shè)計設(shè)計05(第五章C-VHDL組合電路-設(shè)計實例)

數(shù)字電路與邏輯設(shè)計一、基于VHDL的組合邏輯分析二、VHDL基本語素及語法三、基于VHDL的組合邏輯設(shè)計數(shù)字電路與邏輯設(shè)計5-3-3基于VHDL的組合邏輯設(shè)計一、邏輯抽象分析因果關(guān)系，確定輸入/輸出變量定義邏輯狀態(tài)的含意（賦值）二、邏輯功能描述：列出真值表，布爾表達(dá)式，HDL語言等三、選定電路形式（器件類型）四、根據(jù)具體器件進(jìn)行調(diào)整：對邏輯式化簡（基本邏輯門）變換（中規(guī)模邏輯器件MSI）將HDL語句封裝為完整程序代碼（PLD）五、畫出邏輯電路圖，或下載到PLD組合邏輯設(shè)計步驟VHDL組合邏輯電路設(shè)計要領(lǐng)一、邏輯抽象分析邏輯問題，確定輸入、輸出邏輯變量；理清輸出變量如何隨輸入變量變化（邏輯關(guān)系）；二、VHDL程序代碼合成通過VHDL語句的規(guī)定語義來勾畫輸出信號的邏輯行為（輸出信號如何隨輸入信號變化）。（1）三態(tài)輸出電路（2）數(shù)據(jù)選擇器（3）比較器（4）編碼器（5）譯碼器一、常用組合邏輯電路設(shè)計（2）數(shù)據(jù)選擇器8選1MUXlibraryieee;useieee.std_logic_1164.all;entitymux81isPort(D:in

std_logic_vector(0to7);sel:in

std_logic_vector(2downto0);Y:out

std_logic);endmux81;architecture

archmux

ofmux41is

begin

with

sel

select

Y<=D(0)when"000",D(1)when"001",D(2)when"010",D(3)when"011",D(4)when"100",D(5)when"101",D(6)when"110",D(7)whenothers;end

archmux;

中規(guī)模集成數(shù)據(jù)選擇器74x151（8選1）中規(guī)模集成數(shù)據(jù)選擇器74x151（8選1）應(yīng)用1中規(guī)模集成數(shù)據(jù)選擇器74x151（8選1）應(yīng)用2中規(guī)模集成數(shù)據(jù)選擇器74x151（8選1）應(yīng)用2（1）三態(tài)輸出電路

（2）比較器（3）數(shù)據(jù)選擇器（4）編碼器（5）譯碼器一、常用組合邏輯電路設(shè)計（1）三態(tài)輸出電路(1位寬度)AENBEN=1B=A;EN=0B=高阻態(tài)libraryieee;useieee.std_logic_1164.all;entitytrioutisport(A:in

std_logic;en:in

std_logic;B:out

std_logic);endtriout;architecturebehaveoftrioutisbegin

B<=Awhenen='1'else

'Z';endbehave;

--注意此處的“Z”要大寫；三態(tài)輸出電路（多位寬度）

A7-A0ENB7-B0EN=1B=A;EN=0B=高阻態(tài)88libraryieee;useieee.std_logic_1164.all;entitytrioutisport(A:in

std_logic_vector(7downto0);en:in

std_logic;B:out

std_logic_vector(7downto0));endtriout;architecturebehaveoftrioutisbegin

B<=Awhenen='1'else

"ZZZZZZZZ";

endbehave;

--注意多位時用雙引號；（1）三態(tài)輸出電路

（2）數(shù)據(jù)選擇器（3）比較器（4）編碼器（5）譯碼器一、常用組合邏輯電路設(shè)計（3）比較器AGTBALTBAEQBAB如果a>b，輸出為：agtb=‘1‘，altb=’0’，aeqb=‘0’;如果a<b，輸出為：altb=‘1‘，agtb=’0’，aeqb=‘0’;如果a=b，輸出為：aeqb=‘1‘，agtb=’0’，altb=‘0’。Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;ENTITYcmpabIS

PORT

(A,B:in

std_logic_vector(7downto0); AGTB,ALTB,AEQB:out

std_logic); ENDcmpab;ARCHITECTUREaOFcmpabISBEGIN

aeqb<='1'when

a=belse'0';agtb<='1'whena>belse'0';altb<='1'whena<belse'0';ENDa;ARCHITECTUREbOFcmpabISBEGIN

process(a,b)begin

ifA>Bthenagtb<='1';

elsifA=Bthenaeqb<='1';

elsealtb<='1';

endif;

end

process;ENDb;（1）三態(tài)輸出電路

（2）比較器（3）數(shù)據(jù)選擇器（4）編碼器（5）譯碼器一、常用組合邏輯電路設(shè)計（4）編碼器(A普通8-3編碼器)I6I7I5I4I3I2I1I0Y2Y1Y08-3編碼器I7I6I5I4I3I2I1I0Y2Y1Y01111111000011111101001111110110101111011101111101111100110111111011011111111001111111111LIBRARYieee;USEieee.std_logic_1164.all;ENTITYencoderISPORT(i:IN

BIT_VECTOR(7DOWNTO0);y:OUT

BIT_VECTOR(2DOWNTO0));

ENDencoder;ARCHITECTURErtlOFencoderISBEGINy<="000"wheni="11111110"else"001"wheni="11111101"else"010"wheni="11111011"else"011"wheni="11110111"else"100"wheni="11101111"else"101"wheni="11011111"else"110"wheni="10111111"else"111"wheni="01111111"else

"000";ENDrtl;（4）編碼器(Ｂ優(yōu)先8-3編碼器)I6I7I5I4I3I2I1I0Y2Y1Y08-3編碼器I7I6I5I4I3I2I1I0Y2Y1Y0XXXXXXX0000XXXXXX01001XXXXX011010XXXX0111011XXX01111100XX011111101X011111111001111111111LIBRARYieee;USEieee.std_logic_1164.all;ENTITYencoderISPORT(i:IN

BIT_VECTOR(7DOWNTO0);y:OUT

BIT_VECTOR(2DOWNTO0));

ENDencoder;ARCHITECTURErtlOFencoderISBEGINy<="000"wheni(0)='0'

else"001"wheni(1)='0'

else"010"wheni(2)='0'

else"011"wheni(3)='0'

else"100"wheni(4)='0'

else"101"wheni(5)='0'

else"110"wheni(6)='0'

else"111"wheni(7)='0'

else"000";ENDrtl;STD_LOGIC類型信號的取值空間。

若A:OUTSTD_LOGIC；則A可賦予‘0’、‘1’、‘Z’、……，形式如下A<='0';

std_logic信號的取值空間{'0',-----Forcing0'1',-----Forcing1'Z',-----HignImpedance'W',-----WeakUnknown'L',-----Weak0;'H',-----Weak1;'U',-----Undefined'X',-----ForcingUnknown

'-',------Don’tCare;}“九值邏輯”

標(biāo)準(zhǔn)邏輯類型對數(shù)字邏輯電路的邏輯特性描述更加完整，真實，因此在VHDL程序中，對邏輯信號的定義通常采用標(biāo)準(zhǔn)邏輯類型（1）三態(tài)輸出電路

（2）比較器（3）數(shù)據(jù)選擇器（4）編碼器（5）譯碼器一、常用組合邏輯電路設(shè)計（5）譯碼器A.3－8譯碼器LIBRARYieee;USEieee.std_logic_1164.all;ENTITYdecode_3to8ISPORT(a,b,c,G1,G2A,G2B:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDdecode_3to8;ARCHITECTURErtlOFdecode_3to8ISSIGNALindata:STD_LOGIC_VECTOR(5DOWNTO0);BEGINindata<=G1&G2A&G2B&c&b&a;y<="11111110"whenindata="100000"else"11111101"whenindata="100001"else"11111011"whenindata="100010"else"11110111"whenindata="100011"else"11101111"whenindata="100100"else"11011111"whenindata="100101"else"10111111"whenindata="100110"else"01111111"whenindata="100111"else"11111111";ENDrtl;譯碼器（2）譯碼器B.數(shù)碼管譯碼器A3A2A1A0abcdefgLibraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitybcdisPort(A:instd_logic_vector(3downto0);Seven

:outstd_logic_vector(6downto0));Endbcd;ArchitectureaofbcdisBeginSeven<="0111111"whenA="0000"else

--0

"0000110"whenA="0001"else

--1

"1011011"whenA="0010"else

--2

"1001111"whenA="0011"else

--3

"1100110"whenA="0100"else

--4

"1101101"whenA="0101"else

--5

"1111101"whenA="0110"else

--6

"0000111"whenA="0111"else

--7

"1111111"whenA="1000"else

--8

"1101111"whenA="1001"else

--9

"0000000";Enda;例1：組合邏輯設(shè)計

四舍五入電路輸入8421BCD碼，輸出F。libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysswrisport(d:instd_logic_vector(3downto0);y:outstd_logic);endsswr;architecturebehaveofsswrisbeginy<='0'when0<=dandd<5else'1'when5<=dandd<10else'Z';endbehave;例2:設(shè)計組合邏輯電路設(shè)計一個1bit全加器。輸入X,Y,CI輸出Z,COlibraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityfull_bit_adderisport(a,b,ci:instd_logic;y,cout:outstd_logic);endfull_bit_adder;architecturebh1offull_bit_adderisbeginy<=((nota)and(notb)andci)or((nota)and(b)and(notci))or((a)and(notb)and(notci))or((a)and(b)and(ci));cout<=(bandci)or(aandci)or(aandb);endbh1;architecturebh2offull_bit_adderisbeginy<=axorbxorci;cout<=(aandb)or(aandci)or(bandci);endbh2;configurationcon1offull_bit_adderisforbh2endfor;endcon1;例3：四位二進(jìn)制數(shù)轉(zhuǎn)換為BCD碼。entitybin2bcdisport(d_bin:instd_logic_vector(3downto0);d_bcd_H,d_bcd_L:outstd_logic_vector(3downto0));endbin2bcd;architectureaa

ofbin2bcdisBegind_bcd_L<=d_binwhend_bin<10else

d_bin+6;d_bcd_H<=“0000”whend_bin<10else

“0001”;endaa;entitybcd2bisport(d:instd_logic_vector(3downto0);Bh,Bl:outstd_logic_vector(3downto0));endbcd2b;architectureaaofbcd2bissignala,b:std_logic_vector(7downto0);begina<="0000"&d;b<=awhend<10elsea+6;Bh<=b(7downto4);Bl<=b(3downto0);endaa;architectureabofbcd2bisbeginBh<="0001"whend>9else"0000";Bl<=d+6whend>9elsed;endab;例4：設(shè)計一位BCD碼加法器entitybcd_adderisport(d1,d2:instd_logic_vector(3downto0);Bh,Bl:outstd_logic_vector(3downto0));endbcd_adder;architectureaaofbcd_adderissignala,b,t,s:std_logic_vector(7downto0);begina<="0000"&d1;b<="0000"&d2;t<=a+b;s<=twhent<10elset+6;Bh<=s(7downto4);Bl<=s(3downto0);endaa;碼制轉(zhuǎn)換設(shè)計題：將4位自然二進(jìn)制數(shù)轉(zhuǎn)換為BCD碼，并通過數(shù)碼管顯示轉(zhuǎn)換結(jié)果。四位二進(jìn)制碼轉(zhuǎn)換為BCD碼，并譯碼顯示。

（數(shù)碼管為共陰極）Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitybcdisPort(A:instd_logic_vector(3downto0);bcd0,bcd1:outstd_logic_vector(3downto0);seven0,seven1:outstd_logic_vector(6downto0));Endbcd;Architectureaofbcdis

signaltmp:std_logic_vector(3downto0);Beginbcd0<=Awhen(A<10)elseA+6;bcd1<=“0000”when(A<10)else“0001”;tmp<=bcd0;

seven0<="011